coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: amdfwtool: Put all the steps for A/B recovery into one branches
by Bao Zheng (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84531?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Put all the steps for A/B recovery into one branches ...................................................................... amdfwtool: Put all the steps for A/B recovery into one branches Clean up the code to make it more logical. This is for later changes to reorder the PSP Level 1, Level 2, ISH and BIOS tables. TEST=Identical test on all AMD platform Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 6 insertions(+), 19 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/84531/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84531?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f7213fd42c7f0ff5ecd9e504a6654cdfb1e3513 Gerrit-Change-Number: 84531 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: amdfwtool: Move ISH before PSP L2
by Bao Zheng (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84533?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Move ISH before PSP L2 ...................................................................... amdfwtool: Move ISH before PSP L2 The amdfw.rom will be divided into 3 parts: PSP Level 1, PSP Level 2A, PSP Level 2B. The two ISHs are close to L1 and can be combined as a CBFS module. To do that, move the new_psp_dir for L1 and L2 to separated branches. The final sequence is EFS, PSP L1, ISH A, ISH B, PSP L2A, BIOS L2A, PSP L2B, BIOS L2B. Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84533/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75 Gerrit-Change-Number: 84533 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: amdfwtool: Move L1 before L2
by Bao Zheng (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84532?usp=email to look at the new patch set (#8). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Move L1 before L2 ...................................................................... amdfwtool: Move L1 before L2 It is more reasonable. And, in later change, the Level 1 should be splitted with Level 2 and combined with EFS. Change locate_bdt2_bios to locate_bdt_bios. This function is more flexibile and covers L1 first and L2 first. Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 16 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84532/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/84532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b Gerrit-Change-Number: 84532 Gerrit-PatchSet: 8 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: amdfwtool: Add injection corruption to call if necessary
by Bao Zheng (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84579?usp=email to look at the new patch set (#12). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Add injection corruption to call if necessary ...................................................................... amdfwtool: Add injection corruption to call if necessary Use hexeditor can put some random data into the image. Or we can inject corruption when the image is built. Enable the branch when you need it. Change-Id: I5be9456ad8b76c1b6b3975248ea18306acfa3e99 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 31 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/84579/12 -- To view, visit https://review.coreboot.org/c/coreboot/+/84579?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5be9456ad8b76c1b6b3975248ea18306acfa3e99 Gerrit-Change-Number: 84579 Gerrit-PatchSet: 12 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: amdfwtool: Set address mode to relative table
by Bao Zheng (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84535?usp=email to look at the new patch set (#9). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Set address mode to relative table ...................................................................... amdfwtool: Set address mode to relative table The address mode of all L2 table for A/B recovery should be relative table, otherwise the addresses would be different. For Cezanne, the L1 should be still relative BIOS or physical. So when we create level 2 tables, save address mode and restore. Change-Id: I85db43cde15e5b4b26fe9f38e647b31870ea51ac Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/84535/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/84535?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85db43cde15e5b4b26fe9f38e647b31870ea51ac Gerrit-Change-Number: 84535 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: amdfwtool: Split the A/B level 2 with PSP level 1
by Bao Zheng (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Marshall Dawson, Zheng Bao. Hello Felix Held, Julius Werner, Marshall Dawson, Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85467?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Split the A/B level 2 with PSP level 1 ...................................................................... amdfwtool: Split the A/B level 2 with PSP level 1 For later A/B recovery support, we put the A and B into seperated regions. The ROMSIG and PSP L2 table are in another region. Then, We split one amdfw.rom into three parts. TEST=Binary identical test on all AMD platform Change-Id: Ie9230e333dc5b1eca5beee1d3a57e815764c3cf3 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h M util/amdfwtool/handle_file.c M util/amdfwtool/opts.c 4 files changed, 64 insertions(+), 9 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/67/85467/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/85467?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9230e333dc5b1eca5beee1d3a57e815764c3cf3 Gerrit-Change-Number: 85467 Gerrit-PatchSet: 7 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/fatcat: Keep GSPIx interface default PCI
by Subrata Banik (Code Review) 21 Dec '24

21 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85686?usp=email ) Change subject: mb/google/fatcat: Keep GSPIx interface default PCI ...................................................................... mb/google/fatcat: Keep GSPIx interface default PCI BUG=b:377595986 TEST=Able to see 0x12.6 device is visible using `lspci`. Change-Id: Ia3348f78614e61259333ccf2babf20eaf4666a0e Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85686 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: YH Lin <yueherngl(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) Approvals: YH Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index f3a0a65..b9dcbbd 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -51,6 +51,12 @@ [PchSerialIoIndexUART2] = PchSerialIoDisabled, }" + register "serial_io_gspi_mode" = "{ + [PchSerialIoIndexGSPI0] = PchSerialIoPci, + [PchSerialIoIndexGSPI1] = PchSerialIoPci, + [PchSerialIoIndexGSPI0A] = PchSerialIoPci, + }" + register "pch_hda_dsp_enable" = "true" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" -- To view, visit https://review.coreboot.org/c/coreboot/+/85686?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia3348f78614e61259333ccf2babf20eaf4666a0e Gerrit-Change-Number: 85686 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Rename GSPI2 to GSPI0A
by Subrata Banik (Code Review) 21 Dec '24

21 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85685?usp=email ) Change subject: soc/intel/pantherlake: Rename GSPI2 to GSPI0A ...................................................................... soc/intel/pantherlake: Rename GSPI2 to GSPI0A Rename GSPI2 to GSPI0A to align with the latest Intel documentation and platform specifications (doc: 815002) BUG=b:377595986 TEST=Able to see 0x12.6 device is visible using `lspci`. Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85685 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: YH Lin <yueherngl(a)google.com> --- M src/soc/intel/pantherlake/chipset.cb M src/soc/intel/pantherlake/include/soc/serialio.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Pranava Y N: Looks good to me, approved YH Lin: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/chipset.cb b/src/soc/intel/pantherlake/chipset.cb index 67e0785..0f7967b 100644 --- a/src/soc/intel/pantherlake/chipset.cb +++ b/src/soc/intel/pantherlake/chipset.cb @@ -90,7 +90,7 @@ device pci 10.1 alias thc1 off end device pci 12.0 alias ish off end device pci 12.1 alias p2sb2 hidden end - device pci 12.6 alias gspi2 off end + device pci 12.6 alias gspi0a off end device pci 13.0 alias heci_1 off end device pci 13.1 alias heci_2 off end device pci 13.2 alias heci_3 off end diff --git a/src/soc/intel/pantherlake/include/soc/serialio.h b/src/soc/intel/pantherlake/include/soc/serialio.h index def5565..1c15001 100644 --- a/src/soc/intel/pantherlake/include/soc/serialio.h +++ b/src/soc/intel/pantherlake/include/soc/serialio.h @@ -23,7 +23,7 @@ enum { PchSerialIoIndexGSPI0, PchSerialIoIndexGSPI1, - PchSerialIoIndexGSPI2, + PchSerialIoIndexGSPI0A, }; enum { -- To view, visit https://review.coreboot.org/c/coreboot/+/85685?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9b87d38e44c07a053104b53df38ee1ce14a86c7f Gerrit-Change-Number: 85685 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add ACPI name for GSPI2
by Subrata Banik (Code Review) 21 Dec '24

21 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85712?usp=email ) Change subject: soc/intel/pantherlake: Add ACPI name for GSPI2 ...................................................................... soc/intel/pantherlake: Add ACPI name for GSPI2 This change adds the ACPI name "SPI2" for the GSPI2 device in the Panther Lake SOC. Replace space with tab for PCI_DEVFN_GSPI2 macro. w/o this patch: [ERROR] Missing ACPI Name for PCI: 00:12.6 [ERROR] Missing ACPI Name for PCI: 00:12.6 w/ this patch: No error Change-Id: I404ddb893b82836e06d0f52a6d6f2aff2273d8c6 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85712 Reviewed-by: YH Lin <yueherngl(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/chip.c M src/soc/intel/pantherlake/include/soc/pci_devs.h 2 files changed, 2 insertions(+), 1 deletion(-) Approvals: build bot (Jenkins): Verified YH Lin: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 2c79fe7..5fe2a37 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -86,6 +86,7 @@ case PCI_DEVFN_NPU: return "NPU"; case PCI_DEVFN_IPU: return "IPU0"; case PCI_DEVFN_ISH: return "ISHB"; + case PCI_DEVFN_GSPI2: return "SPI2"; case PCI_DEVFN_XHCI: return "XHCI"; case PCI_DEVFN_SRAM: return "SRAM"; case PCI_DEVFN_I2C0: return "I2C0"; diff --git a/src/soc/intel/pantherlake/include/soc/pci_devs.h b/src/soc/intel/pantherlake/include/soc/pci_devs.h index bff5bd3..5c74b6d 100644 --- a/src/soc/intel/pantherlake/include/soc/pci_devs.h +++ b/src/soc/intel/pantherlake/include/soc/pci_devs.h @@ -95,7 +95,7 @@ #define PCI_DEVFN_ISH _PCI_DEVFN(ISH, 0) #define PCI_DEVFN_P2SB2 _PCI_DEVFN(ISH, 1) #define PCI_DEVFN_IEH_1 _PCI_DEVFN(ISH, 3) -#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6) +#define PCI_DEVFN_GSPI2 _PCI_DEVFN(ISH, 6) #define PCI_DEV_ISH _PCI_DEV(ISH, 0) #define PCI_DEV_P2SB2 _PCI_DEV(ISH, 1) #define PCI_DEV_IEH_1 _PCI_DEV(ISH, 3) -- To view, visit https://review.coreboot.org/c/coreboot/+/85712?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I404ddb893b82836e06d0f52a6d6f2aff2273d8c6 Gerrit-Change-Number: 85712 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/system76/mtl: Enable NPU
by Paul Menzel (Code Review) 21 Dec '24

21 Dec '24

Attention is currently required from: Jeremy Soller, Tim Crawford. Paul Menzel has posted comments on this change by Tim Crawford. ( https://review.coreboot.org/c/coreboot/+/85721?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/system76/mtl: Enable NPU ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85721/comment/b8722c67_12d9b379?us… : PS1, Line 10: Please add a TEST= line. -- To view, visit https://review.coreboot.org/c/coreboot/+/85721?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b5c3030c6378c0998a2ac792126c15d2e17bbf9 Gerrit-Change-Number: 85721 Gerrit-PatchSet: 1 Gerrit-Owner: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Comment-Date: Sat, 21 Dec 2024 07:41:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit December 2024