coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove assert when creating DMAR component
by Patrick Rudolph (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Tim Chu. Patrick Rudolph has posted comments on this change by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/85737?usp=email ) Change subject: soc/intel/xeon_sp: Remove assert when creating DMAR component ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85737/comment/82d90644_f1a00a33?us… : PS1, Line 10: Remove > The leading IOAT domains of specific IIO stack will have VTD, but the remaining ones will not. You are writing that multiple domains *share* a VTD, how does that work when you iterate only over devices in the current domain? That doesn't answer the question. Let me rephrase: Can domains without VTD be safely ignored in DMAR handling? If so the code should be updated since on gen1-gen5 there are only domains that have a VTD and no domain is ever ignored. -- To view, visit https://review.coreboot.org/c/coreboot/+/85737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64256baf10abb509d48267e58e6a9e264b916e72 Gerrit-Change-Number: 85737 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 08:36:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Modify PLD for typeC and typeA
by Subrata Banik (Code Review) 23 Dec '24

23 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85618?usp=email ) Change subject: mb/google/nissa/var/telith: Modify PLD for typeC and typeA ...................................................................... mb/google/nissa/var/telith: Modify PLD for typeC and typeA Modify PLD according to the actual positions of typeC and typeA on the DUT. +----------------+ | | | Screen | | | +----------------+ C0 | | A0 | | C1 | | +----------------+ BUG=b:372506691 TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ifc5cd7c8e61b20632d2dcf4b7b2d506c42162063 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85618 Reviewed-by: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/telith/overridetree.cb 1 file changed, 8 insertions(+), 8 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Rui Zhou: Looks good to me, but someone else must approve Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb index 4f1b16e..b48d8a6 100644 --- a/src/mainboard/google/brya/variants/telith/overridetree.cb +++ b/src/mainboard/google/brya/variants/telith/overridetree.cb @@ -348,11 +348,11 @@ # TCP0 (DP-1) for port C0 register "device[2].name" = ""DD02"" register "device[2].use_pld" = "true" - register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(1, 1))" + register "device[2].pld" = "ACPI_PLD_TYPE_C(LEFT, LEFT, ACPI_PLD_GROUP(1, 1))" # TCP1 (DP-2) for port C1 register "device[3].name" = ""DD03"" register "device[3].use_pld" = "true" - register "device[3].pld" = "ACPI_PLD_TYPE_C(RIGHT, LEFT, ACPI_PLD_GROUP(2, 1))" + register "device[3].pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" device generic 0 on end end end @@ -570,10 +570,10 @@ device ref tcss_usb3_port2 on end end chip drivers/usb/acpi - register "desc" = ""USB3 Type-C Port C1 (DB)"" + register "desc" = ""USB3 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref tcss_usb3_port1 on end end end @@ -598,17 +598,17 @@ device ref usb2_port1 on end end chip drivers/usb/acpi - register "desc" = ""USB2 Type-C Port C1 (DB)"" + register "desc" = ""USB2 Type-C Port C1 (MLB)"" register "type" = "UPC_TYPE_C_USB2_SS_SWITCH" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_C(RIGHT, RIGHT, ACPI_PLD_GROUP(2, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_C(LEFT, RIGHT, ACPI_PLD_GROUP(2, 1))" device ref usb2_port2 on end end chip drivers/usb/acpi register "desc" = ""USB2 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(3, 1))" device ref usb2_port3 on end end chip drivers/usb/acpi @@ -637,7 +637,7 @@ register "desc" = ""USB3 Type-A Port A0 (MLB)"" register "type" = "UPC_TYPE_USB3_A" register "use_custom_pld" = "true" - register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, RIGHT, ACPI_PLD_GROUP(3, 1))" + register "custom_pld" = "ACPI_PLD_TYPE_A(LEFT, CENTER, ACPI_PLD_GROUP(3, 1))" device ref usb3_port1 on end end chip drivers/usb/acpi -- To view, visit https://review.coreboot.org/c/coreboot/+/85618?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifc5cd7c8e61b20632d2dcf4b7b2d506c42162063 Gerrit-Change-Number: 85618 Gerrit-PatchSet: 3 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ginger Zhang <zhangqingchun(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/alderlake: Remove superflous compiler argument
by Kapil Porwal (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Nick Vaccaro, Sean Rhodes, Subrata Banik. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84621?usp=email ) Change subject: soc/intel/alderlake: Remove superflous compiler argument ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I92f6d1b0a7fed4730f11e572b076f5dfdb91d96f Gerrit-Change-Number: 84621 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 23 Dec 2024 08:19:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/alderlake: Change the maximum C state to C8
by Kapil Porwal (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Michał Żygowski, Nick Vaccaro, Sean Rhodes, Subrata Banik. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84622?usp=email ) Change subject: soc/intel/alderlake: Change the maximum C state to C8 ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb3e4d34361c8ac25ef144c0d1cda9f801ed0c54 Gerrit-Change-Number: 84622 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 23 Dec 2024 08:18:59 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove assert when creating DMAR component
by Shuo Liu (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Tim Chu. Shuo Liu has posted comments on this change by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/85737?usp=email ) Change subject: soc/intel/xeon_sp: Remove assert when creating DMAR component ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85737/comment/c7b2916a_be4138af?us… : PS1, Line 10: Remove > It sounds like some IOAT domains will be skipped while other are not. […] The leading IOAT domains of specific IIO stack will have VTD, but the remaining ones will not. -- To view, visit https://review.coreboot.org/c/coreboot/+/85737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64256baf10abb509d48267e58e6a9e264b916e72 Gerrit-Change-Number: 85737 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 08:18:33 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove assert when creating DMAR component
by Patrick Rudolph (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Tim Chu. Patrick Rudolph has posted comments on this change by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/85737?usp=email ) Change subject: soc/intel/xeon_sp: Remove assert when creating DMAR component ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85737/comment/4030a51e_fc6e94cb?us… : PS1, Line 10: Remove It sounds like some IOAT domains will be skipped while other are not. Can IOAT domains always be skipped? -- To view, visit https://review.coreboot.org/c/coreboot/+/85737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64256baf10abb509d48267e58e6a9e264b916e72 Gerrit-Change-Number: 85737 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 08:14:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports
by Kapil Porwal (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Michał Żygowski, Nick Vaccaro, Sean Rhodes, Subrata Banik. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/84620?usp=email ) Change subject: soc/intel/alderlake: Add IRQ mapping for PEG PCI-E ports ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Could you please share the warning message? and also the output of ``` grep -E "00:00:0(1|6)." /proc/interrupts lspci -vv -s 00:06. | grep -E "(^00:06|Interrupt)" lspci -vv -s 00:01. | grep -E "(^00:01|Interrupt)" ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2e36cee37716d3b003b9ce250f28fdf5581a15bc Gerrit-Change-Number: 84620 Gerrit-PatchSet: 4 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 23 Dec 2024 08:12:17 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove assert when creating DMAR component
by Shuo Liu (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/85737?usp=email ) Change subject: soc/intel/xeon_sp: Remove assert when creating DMAR component ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64256baf10abb509d48267e58e6a9e264b916e72 Gerrit-Change-Number: 85737 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 08:09:09 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: [test] upgrade GCC to 15-20241215 Snapshot
by Elyes Haouas (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Martin L Roth. Hello Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85729?usp=email to look at the new patch set (#3). Change subject: [test] upgrade GCC to 15-20241215 Snapshot ...................................................................... [test] upgrade GCC to 15-20241215 Snapshot Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20241222_gnat.patch R util/crossgcc/patches/gcc-15-20241222_libcpp.patch R util/crossgcc/patches/gcc-15-20241222_libgcc.patch R util/crossgcc/patches/gcc-15-20241222_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-15-20241222_rv32iafc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20241222.tar.xz.cksum M util/xcompile/xcompile 10 files changed, 6 insertions(+), 91 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 3 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove assert when creating DMAR component
by Jincheng Li (Code Review) 23 Dec '24

23 Dec '24

Jincheng Li has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85737?usp=email ) Change subject: soc/intel/xeon_sp: Remove assert when creating DMAR component ...................................................................... soc/intel/xeon_sp: Remove assert when creating DMAR component Not all domains have VT-d device, e.g. for IOAT, domains under the same IIO stack share one VT-d device. Remove the asserts to directly continue when no VT-d device found. Change-Id: I64256baf10abb509d48267e58e6a9e264b916e72 Signed-off-by: Jincheng Li <jincheng.li(a)intel.com> --- M src/soc/intel/xeon_sp/uncore_acpi.c 1 file changed, 0 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/85737/1 diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index 8651944..2dbafe3 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -387,7 +387,6 @@ while ((domain = dev_find_path(domain, DEVICE_PATH_DOMAIN))) { dev = pcidev_path_behind(domain->downstream, PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)); - assert(dev); if (!dev) continue; /* Only add devices for the current socket */ @@ -445,7 +444,6 @@ while ((domain = dev_find_path(domain, DEVICE_PATH_DOMAIN))) { dev = pcidev_path_behind(domain->downstream, PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)); - assert(dev); if (!dev) continue; /* See if there is a resource with the appropriate index. */ @@ -539,7 +537,6 @@ while ((domain = dev_find_path(domain, DEVICE_PATH_DOMAIN))) { dev = pcidev_path_behind(domain->downstream, PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)); - assert(dev); if (!dev) continue; if (is_dev_on_domain0(dev)) { -- To view, visit https://review.coreboot.org/c/coreboot/+/85737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64256baf10abb509d48267e58e6a9e264b916e72 Gerrit-Change-Number: 85737 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com>

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coreboot-gerrit December 2024