coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: mb/google/nissa/var/telith: Disable stylus GPIOs
by Kun Liu (Code Review) 23 Dec '24

23 Dec '24

Kun Liu has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85738?usp=email ) Change subject: mb/google/nissa/var/telith: Disable stylus GPIOs ...................................................................... mb/google/nissa/var/telith: Disable stylus GPIOs Disable stylus GPIOs based on hardware schematic diagram. BUG=b:372506691 TEST=Local build successfully. Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Signed-off-by: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/telith/gpio.c M src/mainboard/google/brya/variants/telith/overridetree.cb 2 files changed, 4 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85738/1 diff --git a/src/mainboard/google/brya/variants/telith/gpio.c b/src/mainboard/google/brya/variants/telith/gpio.c index 7570d51..0043111 100644 --- a/src/mainboard/google/brya/variants/telith/gpio.c +++ b/src/mainboard/google/brya/variants/telith/gpio.c @@ -42,8 +42,10 @@ /* F6 : CNV_PA_BLANKING ==> NC */ PAD_NC(GPP_F6, NONE), - /* F15 : GSXSRESET# ==> SOC_PEN_DETECT_ODL */ - PAD_CFG_GPI_SCI_HIGH(GPP_F15, NONE, PLTRST, EDGE_BOTH), + /* F15 : GSXSRESET# ==> GPIO */ + PAD_CFG_GPO(GPP_F15, 0, DEEP), + /* F13 : GSXSLOAD ==> GPIO */ + PAD_CFG_GPO(GPP_F13, 0, DEEP), /* F18 : THC1_SPI2_INT# ==> NC */ PAD_NC(GPP_F18, NONE), /* F23 : V1P05_CTRL ==> NC*/ diff --git a/src/mainboard/google/brya/variants/telith/overridetree.cb b/src/mainboard/google/brya/variants/telith/overridetree.cb index b48d8a6..1d6cd45 100644 --- a/src/mainboard/google/brya/variants/telith/overridetree.cb +++ b/src/mainboard/google/brya/variants/telith/overridetree.cb @@ -388,18 +388,6 @@ register "has_power_resource" = "1" device i2c 10 on end end - chip drivers/generic/gpio_keys - register "name" = ""PENH"" - register "gpio" = "ACPI_GPIO_INPUT_ACTIVE_LOW(GPP_F13)" - register "key.wake_gpe" = "GPE0_DW2_15" - register "key.wakeup_route" = "WAKEUP_ROUTE_SCI" - register "key.wakeup_event_action" = "EV_ACT_ANY" - register "key.dev_name" = ""EJCT"" - register "key.linux_code" = "SW_PEN_INSERTED" - register "key.linux_input_type" = "EV_SW" - register "key.label" = ""pen_eject"" - device generic 0 on end - end end device ref i2c2 on chip drivers/intel/mipi_camera -- To view, visit https://review.coreboot.org/c/coreboot/+/85738?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7b72284ab173633405d5de9541f0ea7520d09658 Gerrit-Change-Number: 85738 Gerrit-PatchSet: 1 Gerrit-Owner: Kun Liu <liukun11(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/nissa/var/pujjo: Add new supported memory part
by Kapil Porwal (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Luca Lai, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by Luca Lai. ( https://review.coreboot.org/c/coreboot/+/85735?usp=email ) Change subject: mb/google/nissa/var/pujjo: Add new supported memory part ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/brya/variants/pujjo/memory/mem_parts_used.txt: https://review.coreboot.org/c/coreboot/+/85735/comment/1a3a1c8e_d9c57da8?us… : PS3, Line 22: + why `+`? -- To view, visit https://review.coreboot.org/c/coreboot/+/85735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idb48e849424aac79ef9af29f21b84194455c813e Gerrit-Change-Number: 85735 Gerrit-PatchSet: 3 Gerrit-Owner: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Luca Lai <luca.lai(a)lcfc.corp-partner.google.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 09:12:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: Add G2 touchscreen to devicetree
by Kapil Porwal (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, Kun Liu, Nick Vaccaro, Rui Zhou, Subrata Banik. Kapil Porwal has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85656?usp=email ) Change subject: mb/google/nissa/var/rull: Add G2 touchscreen to devicetree ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85656?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0d68b8d09f2fd280dea17a0542243b88618b5fa1 Gerrit-Change-Number: 85656 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 09:10:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Remove assert when creating DMAR component
by Shuo Liu (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Tim Chu. Shuo Liu has posted comments on this change by Jincheng Li. ( https://review.coreboot.org/c/coreboot/+/85737?usp=email ) Change subject: soc/intel/xeon_sp: Remove assert when creating DMAR component ...................................................................... Patch Set 1: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85737/comment/6e034568_034557d1?us… : PS1, Line 10: Remove > You are writing that multiple domains *share* a VTD, how does that work when you iterate only over d […] Good question. Got a quick check but agree that more checks are needed before moving ahead. 1 - For DRHD, The DRHD adding code is per VTD https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore…, While when it comes to cover the end points, it iterates the whole stack, https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore…. So IOAT domains without VTD are covered as well. (maybe some comments needed to be added here to be more clear). 2 - For RHSA, it is added per VTD, so no impact https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore… 3 - For SATC, it is added per domain, so no impact https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore… 4 - For ATSR, it is added per VTD but covers only PCIe root ports, so not impacting IOAT end points. (But here need to confirm for ATSR no need to add end-points) https://github.com/coreboot/coreboot/blob/main/src/soc/intel/xeon_sp/uncore… -- To view, visit https://review.coreboot.org/c/coreboot/+/85737?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64256baf10abb509d48267e58e6a9e264b916e72 Gerrit-Change-Number: 85737 Gerrit-PatchSet: 1 Gerrit-Owner: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 09:01:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Johannes Hahn (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Mario Scheithauer, Uwe Poeche, Werner Zeh. Johannes Hahn has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/common/block/power_limit/power_limit.c: https://review.coreboot.org/c/coreboot/+/85606/comment/eeadb0e1_f29881b3?us… : PS3, Line 95: * > Done Sorry. I forget to adhere to the right order. First push the changes and then resolve it here in gerrit. Change is contained in Patchset 5. -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 5 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 09:00:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com> Comment-In-Reply-To: Johannes Hahn <johannes-hahn(a)siemens.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Johannes Hahn (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Mario Scheithauer, Uwe Poeche, Werner Zeh. Hello Mario Scheithauer, Uwe Poeche, Werner Zeh, build bot (Jenkins), siemens-bot, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85606?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Code-Review+1 by Mario Scheithauer, Code-Review+1 by Uwe Poeche, Verified+1 by build bot (Jenkins), Verified-1 by siemens-bot Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... soc/intel/common/block/power_limit: Disable RAPL via MSR completely Disabling RAPL via Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS does not turn off RAPL completely (i.d. MMIO & MSR). In the past it was assumed disabling RAPL via MCHBAR is sufficient and the corresponding changes are also reflected in the related MSR (0x610-PACKAGE_POWER_LIMIT). This is not the case for Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still set although PL1 and PL2 were disabled through MCHBAR. Thus Bit[10]-POWER_LIMITATION_STATUS flag can be set in MSR 0x19C (THERM_STATUS) when the power limit of the SKU exceeds. This may lead to a throttling of the domain level frequency. Moreover related parameters within the same MSR (0x610-PACKAGE_POWER_LIMIT) like PKG_PWR_LIM_TIME, PKG_CLMP_LIM, PKG_PWR_LIM have to be cleared as well for both Power Limits (PL1 & PL2). This is due to the fact that these parameters stray in to the system and may effect different system settings. With this commit the PACKAGE_POWER_LIMIT MSR is cleared additionally to the MCHBAR setting when build for ElkhartLake. TEST=Verify MSR(0x610-PACKAGE_POWER_LIMIT) is set to zero during OS runtime except Bit[15]-PKG_PWR_LIM_1_EN (it is known as a bug that this bit will be set to 1 anyway). Moreover using a system stress test tool (e.g. Passmark's BurnInTest) and stressing the system hard should not lead to Bit[10]-POWER_LIMITATION_STATUS flag being set. This is the case when MSR (0x610-PACKAGE_POWER_LIMIT) is not cleared completely and the system is stressed intensively. Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/soc/intel/common/block/power_limit/power_limit.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85606/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 5 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

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[XL] Change in coreboot[main]: [test] upgrade GCC to 15-20241215 Snapshot
by Elyes Haouas (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Hello Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85729?usp=email to look at the new patch set (#6). Change subject: [test] upgrade GCC to 15-20241215 Snapshot ...................................................................... [test] upgrade GCC to 15-20241215 Snapshot And remove unmantained riscv & opensbi Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M .gitmodules D 3rdparty/opensbi M MAINTAINERS M Makefile.mk D configs/config.emulation_qemu_riscv_rv64 D configs/config.sifive_hifive-unleashed.opensbi M payloads/Kconfig M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile D payloads/external/LinuxBoot/riscv/defconfig-32 D payloads/external/LinuxBoot/riscv/defconfig-64 D payloads/external/LinuxBoot/riscv/kernel_fdt_lzma.its M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.mk M payloads/external/linux/Kconfig.name D src/arch/riscv/Kconfig D src/arch/riscv/Makefile.mk D src/arch/riscv/arch_timer.c D src/arch/riscv/boot.c D src/arch/riscv/bootblock.S D src/arch/riscv/fit_payload.c D src/arch/riscv/fp_asm.S D src/arch/riscv/include/arch/barrier.h D src/arch/riscv/include/arch/boot.h D src/arch/riscv/include/arch/byteorder.h D src/arch/riscv/include/arch/cache.h D src/arch/riscv/include/arch/cbconfig.h D src/arch/riscv/include/arch/cpu.h D src/arch/riscv/include/arch/encoding.h D src/arch/riscv/include/arch/errno.h D src/arch/riscv/include/arch/exception.h D src/arch/riscv/include/arch/header.ld D src/arch/riscv/include/arch/hlt.h D src/arch/riscv/include/arch/io.h D src/arch/riscv/include/arch/memlayout.h D src/arch/riscv/include/arch/mmio.h D src/arch/riscv/include/arch/pmp.h D src/arch/riscv/include/arch/smp/atomic.h D src/arch/riscv/include/arch/smp/smp.h D src/arch/riscv/include/arch/smp/spinlock.h D src/arch/riscv/include/bits.h D src/arch/riscv/include/mcall.h D src/arch/riscv/include/sbi.h D src/arch/riscv/include/vm.h D src/arch/riscv/mcall.c D src/arch/riscv/misc.c D src/arch/riscv/opensbi.c D src/arch/riscv/payload.c D src/arch/riscv/pmp.c D src/arch/riscv/ramstage.S D src/arch/riscv/romstage.S D src/arch/riscv/sbi.c D src/arch/riscv/smp.c D src/arch/riscv/tables.c D src/arch/riscv/trap_handler.c D src/arch/riscv/trap_util.S D src/arch/riscv/virtual_memory.c M src/commonlib/bsd/lz4_wrapper.c M src/drivers/uart/Kconfig M src/drivers/uart/Makefile.mk D src/drivers/uart/sifive.c M src/include/acpi/acpi.h M src/include/bootmem.h M src/include/program_loading.h M src/include/rules.h M src/lib/bootmem.c M src/lib/libgcc.c M src/mainboard/emulation/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig.name D src/mainboard/emulation/qemu-riscv/Makefile.mk D src/mainboard/emulation/qemu-riscv/board_info.txt D src/mainboard/emulation/qemu-riscv/cbmem.c D src/mainboard/emulation/qemu-riscv/chip.c D src/mainboard/emulation/qemu-riscv/clint.c D src/mainboard/emulation/qemu-riscv/devicetree.cb D src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h D src/mainboard/emulation/qemu-riscv/mainboard.c D src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/rom_media.c D src/mainboard/emulation/qemu-riscv/romstage.c D src/mainboard/emulation/qemu-riscv/uart.c D src/mainboard/emulation/spike-riscv/Kconfig D src/mainboard/emulation/spike-riscv/Kconfig.name D src/mainboard/emulation/spike-riscv/Makefile.mk D src/mainboard/emulation/spike-riscv/board_info.txt D src/mainboard/emulation/spike-riscv/clint.c D src/mainboard/emulation/spike-riscv/devicetree.cb D src/mainboard/emulation/spike-riscv/mainboard.c D src/mainboard/emulation/spike-riscv/memlayout.ld D src/mainboard/emulation/spike-riscv/rom_media.c D src/mainboard/emulation/spike-riscv/romstage.c D src/mainboard/emulation/spike-riscv/uart.c D src/mainboard/sifive/Kconfig D src/mainboard/sifive/Kconfig.name D src/mainboard/sifive/hifive-unleashed/Kconfig D src/mainboard/sifive/hifive-unleashed/Kconfig.name D src/mainboard/sifive/hifive-unleashed/Makefile.mk D src/mainboard/sifive/hifive-unleashed/board_info.txt D src/mainboard/sifive/hifive-unleashed/devicetree.cb D src/mainboard/sifive/hifive-unleashed/fixup_fdt.c D src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi D src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts D src/mainboard/sifive/hifive-unleashed/mainboard.c D src/mainboard/sifive/hifive-unleashed/media.c D src/mainboard/sifive/hifive-unleashed/romstage.c D src/mainboard/sifive/hifive-unmatched/Kconfig D src/mainboard/sifive/hifive-unmatched/Kconfig.name D src/mainboard/sifive/hifive-unmatched/Makefile.mk D src/mainboard/sifive/hifive-unmatched/board_info.txt D src/mainboard/sifive/hifive-unmatched/cbfs_spi.c D src/mainboard/sifive/hifive-unmatched/devicetree.cb D src/mainboard/sifive/hifive-unmatched/fixup_fdt.c D src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts D src/mainboard/sifive/hifive-unmatched/mainboard.c D src/mainboard/sifive/hifive-unmatched/romstage.c D src/soc/sifive/fu540/Kconfig D src/soc/sifive/fu540/Makefile.mk D src/soc/sifive/fu540/bootblock.c D src/soc/sifive/fu540/cbmem.c D src/soc/sifive/fu540/chip.c D src/soc/sifive/fu540/clint.c D src/soc/sifive/fu540/clock.c D src/soc/sifive/fu540/ddrregs.h D src/soc/sifive/fu540/include/soc/addressmap.h D src/soc/sifive/fu540/include/soc/clock.h D src/soc/sifive/fu540/include/soc/otp.h D src/soc/sifive/fu540/include/soc/sdram.h D src/soc/sifive/fu540/include/soc/spi.h D src/soc/sifive/fu540/memlayout.ld D src/soc/sifive/fu540/otp.c D src/soc/sifive/fu540/regconfig-ctl.h D src/soc/sifive/fu540/regconfig-phy.h D src/soc/sifive/fu540/sdram.c D src/soc/sifive/fu540/spi.c D src/soc/sifive/fu540/spi_internal.h D src/soc/sifive/fu540/uart.c D src/soc/sifive/fu540/ux00ddr.h D src/soc/sifive/fu740/Kconfig D src/soc/sifive/fu740/Makefile.mk D src/soc/sifive/fu740/TODO D src/soc/sifive/fu740/cbmem.c D src/soc/sifive/fu740/chip.c D src/soc/sifive/fu740/clint.c D src/soc/sifive/fu740/clock.c D src/soc/sifive/fu740/ddrregs.c D src/soc/sifive/fu740/gpio.c D src/soc/sifive/fu740/include/soc/addressmap.h D src/soc/sifive/fu740/include/soc/clock.h D src/soc/sifive/fu740/include/soc/gpio.h D src/soc/sifive/fu740/include/soc/otp.h D src/soc/sifive/fu740/include/soc/sdram.h D src/soc/sifive/fu740/include/soc/spi.h D src/soc/sifive/fu740/memlayout.ld D src/soc/sifive/fu740/otp.c D src/soc/sifive/fu740/sdram.c D src/soc/sifive/fu740/spi.c D src/soc/sifive/fu740/spi_internal.h D src/soc/sifive/fu740/uart.c D src/soc/ucb/riscv/Kconfig D src/soc/ucb/riscv/Makefile.mk D src/soc/ucb/riscv/cbmem.c D src/soc/ucb/riscv/chip.c M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch D util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch R util/crossgcc/patches/gcc-15-20241222_gnat.patch R util/crossgcc/patches/gcc-15-20241222_libcpp.patch R util/crossgcc/patches/gcc-15-20241222_libgcc.patch R util/crossgcc/patches/gcc-15-20241222_musl_poisoned_calloc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20241222.tar.xz.cksum D util/riscv/description.md D util/riscv/make-spike-elf.sh D util/riscv/sifive-gpt.py D util/riscv/spike-elf.ld M util/xcompile/xcompile 180 files changed, 15 insertions(+), 13,697 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 6 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

1 0

[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Johannes Hahn (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Mario Scheithauer, Werner Zeh. Johannes Hahn has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/common/block/power_limit/power_limit.c: https://review.coreboot.org/c/coreboot/+/85606/comment/8b884804_e34de51c?us… : PS3, Line 95: * > I think you don't need the star at this point. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 4 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 23 Dec 2024 08:54:34 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Mario Scheithauer <mario.scheithauer(a)siemens.com>

1 0

[XL] Change in coreboot[main]: [test] upgrade GCC to 15-20241215 Snapshot
by Elyes Haouas (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich. Hello Christian Walter, Martin L Roth, Maximilian Brune, Philipp Hug, ron minnich, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85729?usp=email to look at the new patch set (#5). Change subject: [test] upgrade GCC to 15-20241215 Snapshot ...................................................................... [test] upgrade GCC to 15-20241215 Snapshot And remove unmantained riscv & opensbi Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M .gitmodules D 3rdparty/opensbi M MAINTAINERS M Makefile.mk D configs/config.emulation_qemu_riscv_rv64 D configs/config.sifive_hifive-unleashed.opensbi M payloads/Kconfig M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile D payloads/external/LinuxBoot/riscv/defconfig-32 D payloads/external/LinuxBoot/riscv/defconfig-64 D payloads/external/LinuxBoot/riscv/kernel_fdt_lzma.its M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.mk M payloads/external/linux/Kconfig.name D src/arch/riscv/Kconfig D src/arch/riscv/Makefile.mk D src/arch/riscv/arch_timer.c D src/arch/riscv/boot.c D src/arch/riscv/bootblock.S D src/arch/riscv/fit_payload.c D src/arch/riscv/fp_asm.S D src/arch/riscv/include/arch/barrier.h D src/arch/riscv/include/arch/boot.h D src/arch/riscv/include/arch/byteorder.h D src/arch/riscv/include/arch/cache.h D src/arch/riscv/include/arch/cbconfig.h D src/arch/riscv/include/arch/cpu.h D src/arch/riscv/include/arch/encoding.h D src/arch/riscv/include/arch/errno.h D src/arch/riscv/include/arch/exception.h D src/arch/riscv/include/arch/header.ld D src/arch/riscv/include/arch/hlt.h D src/arch/riscv/include/arch/io.h D src/arch/riscv/include/arch/memlayout.h D src/arch/riscv/include/arch/mmio.h D src/arch/riscv/include/arch/pmp.h D src/arch/riscv/include/arch/smp/atomic.h D src/arch/riscv/include/arch/smp/smp.h D src/arch/riscv/include/arch/smp/spinlock.h D src/arch/riscv/include/bits.h D src/arch/riscv/include/mcall.h D src/arch/riscv/include/sbi.h D src/arch/riscv/include/vm.h D src/arch/riscv/mcall.c D src/arch/riscv/misc.c D src/arch/riscv/opensbi.c D src/arch/riscv/payload.c D src/arch/riscv/pmp.c D src/arch/riscv/ramstage.S D src/arch/riscv/romstage.S D src/arch/riscv/sbi.c D src/arch/riscv/smp.c D src/arch/riscv/tables.c D src/arch/riscv/trap_handler.c D src/arch/riscv/trap_util.S D src/arch/riscv/virtual_memory.c M src/commonlib/bsd/lz4_wrapper.c M src/include/acpi/acpi.h M src/include/bootmem.h M src/include/program_loading.h M src/include/rules.h M src/lib/bootmem.c M src/lib/libgcc.c M src/mainboard/emulation/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig.name D src/mainboard/emulation/qemu-riscv/Makefile.mk D src/mainboard/emulation/qemu-riscv/board_info.txt D src/mainboard/emulation/qemu-riscv/cbmem.c D src/mainboard/emulation/qemu-riscv/chip.c D src/mainboard/emulation/qemu-riscv/clint.c D src/mainboard/emulation/qemu-riscv/devicetree.cb D src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h D src/mainboard/emulation/qemu-riscv/mainboard.c D src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/rom_media.c D src/mainboard/emulation/qemu-riscv/romstage.c D src/mainboard/emulation/qemu-riscv/uart.c D src/mainboard/emulation/spike-riscv/Kconfig D src/mainboard/emulation/spike-riscv/Kconfig.name D src/mainboard/emulation/spike-riscv/Makefile.mk D src/mainboard/emulation/spike-riscv/board_info.txt D src/mainboard/emulation/spike-riscv/clint.c D src/mainboard/emulation/spike-riscv/devicetree.cb D src/mainboard/emulation/spike-riscv/mainboard.c D src/mainboard/emulation/spike-riscv/memlayout.ld D src/mainboard/emulation/spike-riscv/rom_media.c D src/mainboard/emulation/spike-riscv/romstage.c D src/mainboard/emulation/spike-riscv/uart.c D src/mainboard/sifive/hifive-unleashed/Kconfig D src/mainboard/sifive/hifive-unleashed/Kconfig.name D src/mainboard/sifive/hifive-unleashed/Makefile.mk D src/mainboard/sifive/hifive-unleashed/board_info.txt D src/mainboard/sifive/hifive-unleashed/devicetree.cb D src/mainboard/sifive/hifive-unleashed/fixup_fdt.c D src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi D src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts D src/mainboard/sifive/hifive-unleashed/mainboard.c D src/mainboard/sifive/hifive-unleashed/media.c D src/mainboard/sifive/hifive-unleashed/romstage.c D src/mainboard/sifive/hifive-unmatched/Kconfig D src/mainboard/sifive/hifive-unmatched/Kconfig.name D src/mainboard/sifive/hifive-unmatched/Makefile.mk D src/mainboard/sifive/hifive-unmatched/board_info.txt D src/mainboard/sifive/hifive-unmatched/cbfs_spi.c D src/mainboard/sifive/hifive-unmatched/devicetree.cb D src/mainboard/sifive/hifive-unmatched/fixup_fdt.c D src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts D src/mainboard/sifive/hifive-unmatched/mainboard.c D src/mainboard/sifive/hifive-unmatched/romstage.c D src/soc/sifive/fu540/Kconfig D src/soc/sifive/fu540/Makefile.mk D src/soc/sifive/fu540/bootblock.c D src/soc/sifive/fu540/cbmem.c D src/soc/sifive/fu540/chip.c D src/soc/sifive/fu540/clint.c D src/soc/sifive/fu540/clock.c D src/soc/sifive/fu540/ddrregs.h D src/soc/sifive/fu540/include/soc/addressmap.h D src/soc/sifive/fu540/include/soc/clock.h D src/soc/sifive/fu540/include/soc/otp.h D src/soc/sifive/fu540/include/soc/sdram.h D src/soc/sifive/fu540/include/soc/spi.h D src/soc/sifive/fu540/memlayout.ld D src/soc/sifive/fu540/otp.c D src/soc/sifive/fu540/regconfig-ctl.h D src/soc/sifive/fu540/regconfig-phy.h D src/soc/sifive/fu540/sdram.c D src/soc/sifive/fu540/spi.c D src/soc/sifive/fu540/spi_internal.h D src/soc/sifive/fu540/uart.c D src/soc/sifive/fu540/ux00ddr.h D src/soc/sifive/fu740/Kconfig D src/soc/sifive/fu740/Makefile.mk D src/soc/sifive/fu740/TODO D src/soc/sifive/fu740/cbmem.c D src/soc/sifive/fu740/chip.c D src/soc/sifive/fu740/clint.c D src/soc/sifive/fu740/clock.c D src/soc/sifive/fu740/ddrregs.c D src/soc/sifive/fu740/gpio.c D src/soc/sifive/fu740/include/soc/addressmap.h D src/soc/sifive/fu740/include/soc/clock.h D src/soc/sifive/fu740/include/soc/gpio.h D src/soc/sifive/fu740/include/soc/otp.h D src/soc/sifive/fu740/include/soc/sdram.h D src/soc/sifive/fu740/include/soc/spi.h D src/soc/sifive/fu740/memlayout.ld D src/soc/sifive/fu740/otp.c D src/soc/sifive/fu740/sdram.c D src/soc/sifive/fu740/spi.c D src/soc/sifive/fu740/spi_internal.h D src/soc/sifive/fu740/uart.c D src/soc/ucb/riscv/Kconfig D src/soc/ucb/riscv/Makefile.mk D src/soc/ucb/riscv/cbmem.c D src/soc/ucb/riscv/chip.c M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch D util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch R util/crossgcc/patches/gcc-15-20241222_gnat.patch R util/crossgcc/patches/gcc-15-20241222_libcpp.patch R util/crossgcc/patches/gcc-15-20241222_libgcc.patch R util/crossgcc/patches/gcc-15-20241222_musl_poisoned_calloc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20241222.tar.xz.cksum M util/xcompile/xcompile 171 files changed, 15 insertions(+), 13,309 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com>

1 0

[XL] Change in coreboot[main]: [test] upgrade GCC to 15-20241215 Snapshot
by Elyes Haouas (Code Review) 23 Dec '24

23 Dec '24

Attention is currently required from: Martin L Roth. Hello Martin L Roth, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85729?usp=email to look at the new patch set (#4). Change subject: [test] upgrade GCC to 15-20241215 Snapshot ...................................................................... [test] upgrade GCC to 15-20241215 Snapshot And remove unmantained riscv & opensbi Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M .gitmodules D 3rdparty/opensbi M MAINTAINERS M Makefile.mk D configs/config.emulation_qemu_riscv_rv64 D configs/config.sifive_hifive-unleashed.opensbi M payloads/Kconfig M payloads/external/LinuxBoot/Kconfig M payloads/external/LinuxBoot/Kconfig.name M payloads/external/LinuxBoot/Makefile D payloads/external/LinuxBoot/riscv/defconfig-32 D payloads/external/LinuxBoot/riscv/defconfig-64 D payloads/external/LinuxBoot/riscv/kernel_fdt_lzma.its M payloads/external/LinuxBoot/targets/u-root.mk M payloads/external/Makefile.mk M payloads/external/linux/Kconfig.name D src/arch/riscv/Kconfig D src/arch/riscv/Makefile.mk D src/arch/riscv/arch_timer.c D src/arch/riscv/boot.c D src/arch/riscv/bootblock.S D src/arch/riscv/fit_payload.c D src/arch/riscv/fp_asm.S D src/arch/riscv/include/arch/barrier.h D src/arch/riscv/include/arch/boot.h D src/arch/riscv/include/arch/byteorder.h D src/arch/riscv/include/arch/cache.h D src/arch/riscv/include/arch/cbconfig.h D src/arch/riscv/include/arch/cpu.h D src/arch/riscv/include/arch/encoding.h D src/arch/riscv/include/arch/errno.h D src/arch/riscv/include/arch/exception.h D src/arch/riscv/include/arch/header.ld D src/arch/riscv/include/arch/hlt.h D src/arch/riscv/include/arch/io.h D src/arch/riscv/include/arch/memlayout.h D src/arch/riscv/include/arch/mmio.h D src/arch/riscv/include/arch/pmp.h D src/arch/riscv/include/arch/smp/atomic.h D src/arch/riscv/include/arch/smp/smp.h D src/arch/riscv/include/arch/smp/spinlock.h D src/arch/riscv/include/bits.h D src/arch/riscv/include/mcall.h D src/arch/riscv/include/sbi.h D src/arch/riscv/include/vm.h D src/arch/riscv/mcall.c D src/arch/riscv/misc.c D src/arch/riscv/opensbi.c D src/arch/riscv/payload.c D src/arch/riscv/pmp.c D src/arch/riscv/ramstage.S D src/arch/riscv/romstage.S D src/arch/riscv/sbi.c D src/arch/riscv/smp.c D src/arch/riscv/tables.c D src/arch/riscv/trap_handler.c D src/arch/riscv/trap_util.S D src/arch/riscv/virtual_memory.c M src/commonlib/bsd/lz4_wrapper.c M src/include/acpi/acpi.h M src/include/bootmem.h M src/include/program_loading.h M src/include/rules.h M src/lib/bootmem.c M src/lib/libgcc.c M src/mainboard/emulation/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig D src/mainboard/emulation/qemu-riscv/Kconfig.name D src/mainboard/emulation/qemu-riscv/Makefile.mk D src/mainboard/emulation/qemu-riscv/board_info.txt D src/mainboard/emulation/qemu-riscv/cbmem.c D src/mainboard/emulation/qemu-riscv/chip.c D src/mainboard/emulation/qemu-riscv/clint.c D src/mainboard/emulation/qemu-riscv/devicetree.cb D src/mainboard/emulation/qemu-riscv/include/mainboard/addressmap.h D src/mainboard/emulation/qemu-riscv/mainboard.c D src/mainboard/emulation/qemu-riscv/memlayout.ld D src/mainboard/emulation/qemu-riscv/rom_media.c D src/mainboard/emulation/qemu-riscv/romstage.c D src/mainboard/emulation/qemu-riscv/uart.c D src/mainboard/emulation/spike-riscv/Kconfig D src/mainboard/emulation/spike-riscv/Kconfig.name D src/mainboard/emulation/spike-riscv/Makefile.mk D src/mainboard/emulation/spike-riscv/board_info.txt D src/mainboard/emulation/spike-riscv/clint.c D src/mainboard/emulation/spike-riscv/devicetree.cb D src/mainboard/emulation/spike-riscv/mainboard.c D src/mainboard/emulation/spike-riscv/memlayout.ld D src/mainboard/emulation/spike-riscv/rom_media.c D src/mainboard/emulation/spike-riscv/romstage.c D src/mainboard/emulation/spike-riscv/uart.c D src/mainboard/sifive/hifive-unleashed/Kconfig D src/mainboard/sifive/hifive-unleashed/Kconfig.name D src/mainboard/sifive/hifive-unleashed/Makefile.mk D src/mainboard/sifive/hifive-unleashed/board_info.txt D src/mainboard/sifive/hifive-unleashed/devicetree.cb D src/mainboard/sifive/hifive-unleashed/fixup_fdt.c D src/mainboard/sifive/hifive-unleashed/fu540-c000.dtsi D src/mainboard/sifive/hifive-unleashed/hifive-unleashed-a00.dts D src/mainboard/sifive/hifive-unleashed/mainboard.c D src/mainboard/sifive/hifive-unleashed/media.c D src/mainboard/sifive/hifive-unleashed/romstage.c D src/mainboard/sifive/hifive-unmatched/Kconfig D src/mainboard/sifive/hifive-unmatched/Kconfig.name D src/mainboard/sifive/hifive-unmatched/Makefile.mk D src/mainboard/sifive/hifive-unmatched/board_info.txt D src/mainboard/sifive/hifive-unmatched/cbfs_spi.c D src/mainboard/sifive/hifive-unmatched/devicetree.cb D src/mainboard/sifive/hifive-unmatched/fixup_fdt.c D src/mainboard/sifive/hifive-unmatched/fu740-c000.dtsi D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00-mod.dts D src/mainboard/sifive/hifive-unmatched/hifive-unmatched-a00.dts D src/mainboard/sifive/hifive-unmatched/mainboard.c D src/mainboard/sifive/hifive-unmatched/romstage.c D src/soc/sifive/fu540/Kconfig D src/soc/sifive/fu540/Makefile.mk D src/soc/sifive/fu540/bootblock.c D src/soc/sifive/fu540/cbmem.c D src/soc/sifive/fu540/chip.c D src/soc/sifive/fu540/clint.c D src/soc/sifive/fu540/clock.c D src/soc/sifive/fu540/ddrregs.h D src/soc/sifive/fu540/include/soc/addressmap.h D src/soc/sifive/fu540/include/soc/clock.h D src/soc/sifive/fu540/include/soc/otp.h D src/soc/sifive/fu540/include/soc/sdram.h D src/soc/sifive/fu540/include/soc/spi.h D src/soc/sifive/fu540/memlayout.ld D src/soc/sifive/fu540/otp.c D src/soc/sifive/fu540/regconfig-ctl.h D src/soc/sifive/fu540/regconfig-phy.h D src/soc/sifive/fu540/sdram.c D src/soc/sifive/fu540/spi.c D src/soc/sifive/fu540/spi_internal.h D src/soc/sifive/fu540/uart.c D src/soc/sifive/fu540/ux00ddr.h D src/soc/sifive/fu740/Kconfig D src/soc/sifive/fu740/Makefile.mk D src/soc/sifive/fu740/TODO D src/soc/sifive/fu740/cbmem.c D src/soc/sifive/fu740/chip.c D src/soc/sifive/fu740/clint.c D src/soc/sifive/fu740/clock.c D src/soc/sifive/fu740/ddrregs.c D src/soc/sifive/fu740/gpio.c D src/soc/sifive/fu740/include/soc/addressmap.h D src/soc/sifive/fu740/include/soc/clock.h D src/soc/sifive/fu740/include/soc/gpio.h D src/soc/sifive/fu740/include/soc/otp.h D src/soc/sifive/fu740/include/soc/sdram.h D src/soc/sifive/fu740/include/soc/spi.h D src/soc/sifive/fu740/memlayout.ld D src/soc/sifive/fu740/otp.c D src/soc/sifive/fu740/sdram.c D src/soc/sifive/fu740/spi.c D src/soc/sifive/fu740/spi_internal.h D src/soc/sifive/fu740/uart.c D src/soc/ucb/riscv/Kconfig D src/soc/ucb/riscv/Makefile.mk D src/soc/ucb/riscv/cbmem.c D src/soc/ucb/riscv/chip.c M util/crossgcc/buildgcc D util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch R util/crossgcc/patches/gcc-15-20241222_gnat.patch R util/crossgcc/patches/gcc-15-20241222_libcpp.patch R util/crossgcc/patches/gcc-15-20241222_libgcc.patch R util/crossgcc/patches/gcc-15-20241222_musl_poisoned_calloc.patch R util/crossgcc/patches/gcc-15-20241222_rv32iafc.patch D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20241222.tar.xz.cksum M util/xcompile/xcompile 171 files changed, 15 insertions(+), 13,254 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85729/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85729?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I644fae70488c26ba833c2332059e805e50764c2a Gerrit-Change-Number: 85729 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

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coreboot-gerrit December 2024