coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[XS] Change in coreboot[main]: soc/intel/cmn/block/smbus: Keep TCO WDT timeout flag if ACPI_WDAT_WDT=y
by Filip Brozovic (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Paul Menzel. Filip Brozovic has posted comments on this change by Filip Brozovic. ( https://review.coreboot.org/c/coreboot/+/84875?usp=email ) Change subject: soc/intel/cmn/block/smbus: Keep TCO WDT timeout flag if ACPI_WDAT_WDT=y ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84875?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d35a8f8bcbcc3aaaadcc936fab028641dfd6e2c Gerrit-Change-Number: 84875 Gerrit-PatchSet: 4 Gerrit-Owner: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: Filip Brozovic <fbrozovic(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 31 Dec 2024 08:53:47 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: mb/starlabs/starbook: Put options in CFR cbtable
by Sean Rhodes (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Angel Pons, Christian Walter. Hello Angel Pons, Christian Walter, Lean Sheng Tan, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/74743?usp=email to look at the new patch set (#30). Change subject: mb/starlabs/starbook: Put options in CFR cbtable ...................................................................... mb/starlabs/starbook: Put options in CFR cbtable Change-Id: I816893e5c2663ed55ae9fa5dd662489b27332aa6 Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> --- M src/mainboard/starlabs/starbook/Kconfig M src/mainboard/starlabs/starbook/Makefile.mk A src/mainboard/starlabs/starbook/cfr.c M src/mainboard/starlabs/starbook/cmos.default M src/mainboard/starlabs/starbook/cmos.layout D src/mainboard/starlabs/starbook/variants/tgl/cmos.default D src/mainboard/starlabs/starbook/variants/tgl/cmos.layout 7 files changed, 383 insertions(+), 231 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/43/74743/30 -- To view, visit https://review.coreboot.org/c/coreboot/+/74743?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I816893e5c2663ed55ae9fa5dd662489b27332aa6 Gerrit-Change-Number: 74743 Gerrit-PatchSet: 30 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Lean Sheng Tan <tanleansheng(a)outlook.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: nb/sandybridge: Implement automatic DRAM voltage setting
by Patrick Rudolph (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Angel Pons, Riku Viitanen. Patrick Rudolph has posted comments on this change by Riku Viitanen. ( https://review.coreboot.org/c/coreboot/+/85793?usp=email ) Change subject: nb/sandybridge: Implement automatic DRAM voltage setting ...................................................................... Patch Set 9: (1 comment) File src/northbridge/intel/sandybridge/raminit.c: https://review.coreboot.org/c/coreboot/+/85793/comment/2b0fc336_b45e84b9?us… : PS9, Line 196: VOLTAGE_MIN_MV Mainboard should provide the maximum/minimum voltage that it supports when MAINBOARD_HAS_ADJUSTABLE_DRAM_VOLTAGE is selected. -- To view, visit https://review.coreboot.org/c/coreboot/+/85793?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1a8857deee85fd635429afd3cbf93cad7a7d589b Gerrit-Change-Number: 85793 Gerrit-PatchSet: 9 Gerrit-Owner: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Riku Viitanen <riku.viitanen(a)protonmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Dec 2024 07:49:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/google/brya/baseboard/trulo: Disable GPIO dynamic clock gating
by Subrata Banik (Code Review) 31 Dec '24

31 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85818?usp=email ) Change subject: mb/google/brya/baseboard/trulo: Disable GPIO dynamic clock gating ...................................................................... mb/google/brya/baseboard/trulo: Disable GPIO dynamic clock gating This change disables dynamic clock gating for GPIO on the Trulo baseboard by overriding the weak function `variant_update_soc_chip_config()`. This is necessary to ensure that short interrupt pulses can be reliably captured. With dynamic clock gating enabled, the GPIO clocks may be gated off, preventing the interrupt from being detected. This change sets bits 0-5 in the MISC_CONFIGURATION register for each GPIO community to disable dynamic clock gating. TEST=Verified that GPIO dynamic clock gating is disabled by dumping the GPIO community MISC_CONFIGURATION registers. Change-Id: I5e853f12a0c78d8d179faba0cef4c99128296f2f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk A src/mainboard/google/brya/variants/baseboard/trulo/trulo.c 2 files changed, 16 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/85818/1 diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk index cc62f1d..5084b09 100644 --- a/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk +++ b/src/mainboard/google/brya/variants/baseboard/trulo/Makefile.mk @@ -2,3 +2,4 @@ romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads romstage-y += memory.c +ramstage-y += trulo.c diff --git a/src/mainboard/google/brya/variants/baseboard/trulo/trulo.c b/src/mainboard/google/brya/variants/baseboard/trulo/trulo.c new file mode 100644 index 0000000..3d6c373 --- /dev/null +++ b/src/mainboard/google/brya/variants/baseboard/trulo/trulo.c @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <baseboard/variants.h> + +void variant_update_soc_chip_config(struct soc_intel_alderlake_config *config) +{ + printk(BIOS_INFO, "Disabling GPIO PM inside %s for Trulo baseboard\n", __func__); + config->gpio_override_pm = 1; + config->gpio_pm[COMM_0] = 0; + config->gpio_pm[COMM_1] = 0; + config->gpio_pm[COMM_2] = 0; + config->gpio_pm[COMM_3] = 0; + config->gpio_pm[COMM_4] = 0; + config->gpio_pm[COMM_5] = 0; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85818?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e853f12a0c78d8d179faba0cef4c99128296f2f Gerrit-Change-Number: 85818 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[L] Change in coreboot[main]: soc/inte/{adl,mtl}: Move ASPM helper functions to common
by Kapil Porwal (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Nick Vaccaro, Sean Rhodes, Subrata Banik, Tarun. Kapil Porwal has posted comments on this change by Sean Rhodes. ( https://review.coreboot.org/c/coreboot/+/83679?usp=email ) Change subject: soc/inte/{adl,mtl}: Move ASPM helper functions to common ...................................................................... Patch Set 10: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/83679?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic6876e920d75abbbbb27d4ce3a4f2c08a8db9410 Gerrit-Change-Number: 83679 Gerrit-PatchSet: 10 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Dec 2024 06:48:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
by Kapil Porwal (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Jérémy Compostella, Pranava Y N. Kapil Porwal has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email ) Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS1: > Document #813032 Panther Lake H I/O RegistersLink Capabilities (LCAP) – Offset 4c does not p […] PCI root port number for TBT starts from 16 for MTL and from 21 for PTL as per respective EDS docs (Section 2.3 Device IDs). MTL EDS #640228 PTL EDS #815002 -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 31 Dec 2024 06:47:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15
by Subrata Banik (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Jérémy Compostella, Kapil Porwal, Pranava Y N. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85781?usp=email ) Change subject: soc/intel/pantherlake: Update the Thunderbolt lcap_port_base to 0x15 ...................................................................... Patch Set 2: (1 comment) Patchset: PS1: > Document #813032 Panther Lake H I/O RegistersLink Capabilities (LCAP) – Offset 4c does not provide much information on the encoding of the port number field (see extract below). > > > **Port Number (PN)** > > Indicates the port number for the root port. This value is different for each implemented port: > > Port # Value of PN field > > 1 01h > > 2 02h > > 3 03h > > > > > > > > X 0Xh > > > > **Note**: Depending on the platform, the number of Root Ports supported may vary. In this case, the encodings defined in this register will be scaled accordingly. > > The final note provides a clue to why it may start with a shift. I determined the value of 0x15 through empirical experiments and verified its consistency across different Panther Lake SKUs. I could not find the specification of the TBT Link Capabilities register for Meteor Lake, but according to [81841 soc/intel/mtl: Fixed TBT PCIe devtree remapping](https://review.coreboot.org/c/coreboot/+/81841), port numbers start at 0x10 on Meteor Lake. > > I added some information to the commit message. > > The fact that we used a non-specified value on Meteor Lake, in my opinion, is an endorsement to submit this CL. However, I would like to know if there is a way to determine this value through a hardware specification and, in particular, for the following SoC generations. document 815002, Table 8 ``` USB Type-C Subsystem PCIe Root Port #21 ``` can you please add this notes in the comment section ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85781?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I44f91f954a4ec06c56dcc90d97e7da2193e9acf2 Gerrit-Change-Number: 85781 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Tue, 31 Dec 2024 06:41:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: Documentation: Add Erying Polestar G613 Pro
by Nicholas Chin (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Alicja Michalska, Angel Pons, Felix Singer. Nicholas Chin has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/81611?usp=email ) Change subject: Documentation: Add Erying Polestar G613 Pro ...................................................................... Patch Set 7: (9 comments) Patchset: PS7: The content looks fine to me. Just some things I noticed about the rendered output. File Documentation/mainboard/erying/tgl/tgl_matx.md: https://review.coreboot.org/c/coreboot/+/81611/comment/486c447e_2530cafb?us… : PS7, Line 37: By going to `Chipset -> Include CPU microcode in CBFS (Include external microcode binary)`. Markdown ignores new lines without a blank line in between, so this renders as part of the above bullet point. Adding a blank line after the bullets so that this renders as a new line at the same indent level as the main text. https://review.coreboot.org/c/coreboot/+/81611/comment/9e7bf842_c8594eba?us… : PS7, Line 66: If you're using [flashrom] or [flashprog] (fork of flashrom), you can skip extracting `SI_BIOS` and `SI_ME` regions from your ROM, and flash coreboot to `SI_BIOS` region by issuing the following command: Please reflow to 72 characters https://review.coreboot.org/c/coreboot/+/81611/comment/e45d9435_90702d50?us… : PS7, Line 112: `modprobe it87 force_id=0x8603 Missing closing backtick? ```suggestion - Configure automatic fan control using pwmconfig (`modprobe it87 force_id=0x8603`) ``` https://review.coreboot.org/c/coreboot/+/81611/comment/a13e23b3_7e707432?us… : PS7, Line 117: - Intel Flash Descriptor (IFD) is required if you wish to flash the entire chip. : - Intel Management Engine blob is required if you wish to flash the entire chip. These render a bit awkwardly (the bullets are at the same indent level as the numbering, and have a paragraph break with the prior text). Indenting them so that the dashes are at the same level as "Required blobs" (i.e. indent by 3 spaces) makes it render as part of note 1. https://review.coreboot.org/c/coreboot/+/81611/comment/1e579e86_4c0cfb74?us… : PS7, Line 119: Both blobs included in `3rdparty/blobs` repository have been extracted from vendor's firmware. : IFD region has been modified using `ifdtool` to flip `MeAltDisable` flag. As above; this renders as part of the bullet point about the Intel ME. Adding a blank line after the bullets and indenting to the same level as "Required blobs" make it look better. https://review.coreboot.org/c/coreboot/+/81611/comment/bdbd026b_f9ecf8a4?us… : PS7, Line 123: It is possible to replace Winbond 16MB chip with 32MB equivalent, which would allow you to use LinuxBoot or implement RO + A/B VBOOT update scheme. This renders on the same line as Modifications. Add a blank line before this and indent to the same level as "Modifications" (3 spaces) https://review.coreboot.org/c/coreboot/+/81611/comment/98562534_9a8e4fc8?us… : PS7, Line 126: If you are using an external graphics card (AMD Radeon, Nvidia GeForce, Intel Arc), you will see output in your OS as soon as kernel initializes the card (called "modprobing" in Linux) regardless of payload you chose. : This board have been tested with: : - EDK2 : - U-Boot : - LinuxBoot (U-Root + Linux kernel) As above. I'd recommend indenting this to the same level as "Payload and ..." (i.e. 3 spaces) so that it looks like a part of note 3 https://review.coreboot.org/c/coreboot/+/81611/comment/67f9d3c6_213f5868?us… : PS7, Line 122: 2. Modifications : It is possible to replace Winbond 16MB chip with 32MB equivalent, which would allow you to use LinuxBoot or implement RO + A/B VBOOT update scheme. : : 3. Payload and pre-OS display output : If you are using an external graphics card (AMD Radeon, Nvidia GeForce, Intel Arc), you will see output in your OS as soon as kernel initializes the card (called "modprobing" in Linux) regardless of payload you chose. : This board have been tested with: : - EDK2 : - U-Boot : - LinuxBoot (U-Root + Linux kernel) : : If you would like to see output on your iGPU before that stage (for picking a different boot medium or toggling Secure Boot setting), you need to use [MrChromebox's EDK2] fork and include [GOP driver] for TigerLake iGPU in your build. : This will allow you to see output of EDK2 (payload, boot picker) on your monitor connected to iGPU. : : If you're planning to primarly use an external card, disable iGPU by toggling `Chipset -> Disable Integrated GFX Controller (0:2:0)` and use [elly's EDK2] tree. : In order to enable loading OpROMs from PCIe devices, go to `Payload -> edk2 additional custom build parameters` and add the string: `-D LOAD_OPTION_ROMS=TRUE`. : This functionality has been tested with following GPUs, with following results: : - Nvidia GeForce RTX3080;RTX3090: Works perfectly : - AMD Radeon RX6600XT;RX7800XT: Works with ReBAR disabled, no output in EDK2 with ReBAR enabled : - Intel Arc A580: Works with ReBAR disabled, glitched framebuffer before modprobing Please reflow to 72 characters -- To view, visit https://review.coreboot.org/c/coreboot/+/81611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d60508dbde10373b0da2fb4ece0992760d3121c Gerrit-Change-Number: 81611 Gerrit-PatchSet: 7 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Angel Pons <th3fanbus(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Tue, 31 Dec 2024 06:08:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in blobs[main]: soc/mediatek/mt8196: Add GPUEB firmware v1.0
by Yu-Ping Wu (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Andy Hsu, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/blobs/+/85763?usp=email ) Change subject: soc/mediatek/mt8196: Add GPUEB firmware v1.0 ...................................................................... Patch Set 4: (3 comments) File soc/mediatek/mt8196/README.md: https://review.coreboot.org/c/blobs/+/85763/comment/9ea6e7ab_357a2413?usp=e… : PS4, Line 207: tinysys-gpueb-RV33_A.mkpt_fw.img gpueb_fw.img https://review.coreboot.org/c/blobs/+/85763/comment/3902f710_c66fc813?usp=e… : PS4, Line 216: tinysys-gpueb-RV33_A.mkpt_fw.img gpueb_fw.img File soc/mediatek/mt8196/gpueb_fw.img.md5: https://review.coreboot.org/c/blobs/+/85763/comment/55d5f99f_a20fcc17?usp=e… : PS4, Line 1: There should be a `*` if you used `md5sum -b`. -- To view, visit https://review.coreboot.org/c/blobs/+/85763?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: blobs Gerrit-Branch: main Gerrit-Change-Id: I470f1575beea481cac2dcb5f3eb77587739ff2dc Gerrit-Change-Number: 85763 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Andy Hsu <andy.hsu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 31 Dec 2024 04:55:00 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/mediatek/mt8196: Add delay in pmif_spmi.c
by Yu-Ping Wu (Code Review) 31 Dec '24

31 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85799?usp=email ) Change subject: soc/mediatek/mt8196: Add delay in pmif_spmi.c ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85799/comment/53b0a8eb_f698037c?us… : PS2, Line 7: Add delay in pmif_spmi.c Can we be more specific? For example, `Delay 0.5ms before enabling cmd issue`. Also, does the delay need to be put between `pmif_spmi_enable_swinf` and `pmif_spmi_enable_cmd_issue`? If I read the code correctly, the calibration happens within `spmi_mst_init`. I wonder if we can put the delay at the end of the `if (arb->is_pmif_init_done(arb) != 0)` clause in `pmif_spmi_init()`. -- To view, visit https://review.coreboot.org/c/coreboot/+/85799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I63df384061e4ed2629238f1843decd18d1ad1ac4 Gerrit-Change-Number: 85799 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 31 Dec 2024 04:45:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit December 2024