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Change subject: drivers/option: Add forms in cbtables
......................................................................
Patch Set 22:
(2 comments)
File src/drivers/option/cfr.h:
https://review.coreboot.org/c/coreboot/+/74121/comment/432e4d97_72ec2d06?us… :
PS22, Line 10: /* Front-end */
That front-end should be split to a different header
File src/drivers/option/cfr.c:
https://review.coreboot.org/c/coreboot/+/74121/comment/815915a6_ba8993da?us… :
PS22, Line 39: lb_cfr_varbinary
Where did this struct definition go?
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Change subject: mb/ocp/tiogapass: Wait for BMC
......................................................................
Patch Set 6:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85492/comment/a8763da6_3b221ddf?us… :
PS6, Line 15: lot's
typo: "lots"
https://review.coreboot.org/c/coreboot/+/85492/comment/fe1befcf_7f3cffa6?us… :
PS6, Line 15: error messages
From coreboot? From the payload (which one)? From the OS (which one)?
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Change subject: drivers/option: Add forms in cbtables
......................................................................
drivers/option: Add forms in cbtables
Introduce a mechanism so that coreboot can provide a list of options to
post-coreboot code. The options are grouped together into forms and
have a meaning name and optional help text. This can be used to let
payloads know which options should be displayed in a setup menu,
for instance. Although this system was written to be used with edk2,
it has been designed with flexibility in mind so that other payloads
can also make use of this mechanism. The system currently lacks a way
to describe where to find option values.
This information is stored in a set of data structures specifically
created for this purpose. This format is known as CFR, which means
"coreboot forms representation" or "cursed forms representation".
Although the "forms representation" is borrowed from UEFI, CFR can
be used in non-UEFI scenarios as well.
The data structures are implemented as an extension of cbtables records
to support nesting. It should not break backwards compatibility because
the CFR root record (LB_TAG_CFR_ROOT) size includes all of its children
records. The concept of record nesting is borrowed from the records for
CMOS options. It is not possible to reuse the CMOS records because they
are too closely coupled with CMOS options; using these structures would
needlessly restrict more capable backends to what can be done with CMOS
options, which is undesired.
Because CFR supports variable-length components, directly transforming
options into CFR structures is not a trivial process. Furthermore, CFR
structures need to be written in one go. Because of this, abstractions
exist to generate CFR structures from a set of "setup menu" structures
that are coreboot-specific and could be integrated with the devicetree
at some point. Note that `struct sm_object` is a tagged union. This is
used to have lists of options in an array, as building linked lists of
options at runtime is extremely impractical because options would have
to be added at the end of the linked list to maintain option order. To
avoid mistakes defining `struct sm_object` values, helper macros exist
for supported option types. The macros also provide some type checking
as they initialise specific union members.
It should be possible to extend CFR support for more sophisticated
options like fan curve points. Feedback about this is highly
appreciated.
Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772
Signed-off-by: Angel Pons <th3fanbus(a)gmail.com>
---
A Documentation/drivers/cfr_internal.md
M Documentation/drivers/index.md
A src/drivers/option/Kconfig
A src/drivers/option/Makefile.inc
A src/drivers/option/cfr.c
A src/drivers/option/cfr.h
M src/include/boot/coreboot_tables.h
M src/lib/coreboot_table.c
M src/lib/program.ld
9 files changed, 604 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/74121/22
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Change subject: [RFC] drivers/option: Add forms in cbtables
......................................................................
Patch Set 21:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/74121/comment/6a4a5974_be222929?us… :
PS18, Line 15: The system currently lacks a way
: to describe where to find option values.
> Because storage areas could differ completely from one mainboard to another, so I think it would be […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/74121/comment/d10d9cf1_017d29f2?us… :
PS18, Line 20: cursed forms representation
> How about we keep the acronym, but using different words? […]
Acknowledged
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Change subject: soc/intel/xeon_sp/lbg: Add support to hide HDA
......................................................................
Patch Set 7:
(1 comment)
File src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h:
https://review.coreboot.org/c/coreboot/+/85496/comment/42440559_6afd7f39?us… :
PS2, Line 9: #define PID_PSF3 0xBC
> There's no preexisting order, sorting these defines would be unrelated.
Acknowledged
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Change subject: mb/ocp/tiogapass: Wait for BMC
......................................................................
Patch Set 6:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85492/comment/850957a4_77e13b94?us… :
PS5, Line 15: Fixes lot's of error messages about not working IPMI.
> Paste one of these error messages?
to do this he has to revert the patch and just reflash and reboot the whole thing just for this error messages.. i think we could accept this for now.
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Hello Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier, Matt DeVillier, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84915?usp=email
to look at the new patch set (#13).
Change subject: soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls
......................................................................
soc/amd/phoenix/chip.c: Add PHX OpenSIL POC TP2/TP3 calls
Call OpenSIL timepoint 2 for further initialization of AMD SoC after
coreboot has performed PCIe enumeration, and timepoint 3 for late SoC
IPs programming and register locking closer to payload load prior to OS
handoff.
Change-Id: I8c335211bf36118fe1d6b7dacbf4064c1d7d3a38
Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com>
---
M src/soc/amd/phoenix/chip.c
1 file changed, 16 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/15/84915/13
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Change subject: src/soc/intel/cmn/blk/cse: Log cse sync information
......................................................................
Patch Set 2:
(3 comments)
Patchset:
PS1:
> there should be an equivalent change in payload as well.
Yes, CL:6038473 has already been raised but is being kept as WIP until the coreboot changes reach downstream.
Commit Message:
https://review.coreboot.org/c/coreboot/+/85219/comment/3c7642cc_60ec6b65?us… :
PS1, Line 14: TEST=elog verified on rex0
> Paste an example of the new log lines?
Acknowledged
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/85219/comment/1f26c11e_6540dde5?us… :
PS1, Line 838: if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE))
: elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, ELOG_FW_RAMSTAGE_CSE_SYNC);
: else
: elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, ELOG_FW_ROMSTAGE_CSE_SYNC);
> `elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, ENV_RAMSTAGE ? ... […]
Acknowledged
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Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place
......................................................................
Patch Set 4:
(1 comment)
File src/soc/intel/alderlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85111/comment/ead9e3cb_c4a3734d?us… :
PS3, Line 442: if (CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE) && is_cse_fw_update_required()) {
> `&& !is_cse_boot_to_rw()` to ensure that there are no redundant logs in the event logs. […]
Acknowledged
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Dinesh Gehlot has posted comments on this change by Dinesh Gehlot. ( https://review.coreboot.org/c/coreboot/+/85218?usp=email )
Change subject: util/cbfstool: Add eventLog support for ELOG_TYPE_FW_CSE_SYNC
......................................................................
Patch Set 2:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85218/comment/bb4e0c3f_54d69735?us… :
PS1, Line 14: TEST=boot verified on google/rex0
> Paste the new log lines?
This patch just adds support for the new events log. These events will be used in subsequent patches and output has pasted there.
File util/cbfstool/eventlog.c:
https://review.coreboot.org/c/coreboot/+/85218/comment/71397cc3_b903656b?us… :
PS1, Line 173: cse
> `CSE` this an acronym
Acknowledged
https://review.coreboot.org/c/coreboot/+/85218/comment/3da6ce9e_6ef0079a?us… :
PS1, Line 494: {ELOG_FW_ROMSTAGE_CSE_SYNC, "ROMSTAGE performed CSE sync"},
: {ELOG_FW_RAMSTAGE_CSE_SYNC, "RAMSTAGE performed CSE sync"},
: {ELOG_FW_PAYLOAD_CSE_SYNC, "PAYLOAD performed CSE sync"},
> https://review.coreboot. […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/85218/comment/0be1d3c1_c9e98f48?us… :
PS1, Line 522: [ELOG_TYPE_FW_CSE_SYNC] = sizeof(uint8_t),
> Nit: Add extra tabs to align `= RHS` with the rest of the lines.
Acknowledged
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