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Change subject: src/soc/intel/cmn/blk/cse: Log cse sync information
......................................................................
Patch Set 2:
(2 comments)
File src/soc/intel/common/block/cse/cse_lite.c:
https://review.coreboot.org/c/coreboot/+/85219/comment/2038e862_f3a9c266?us… :
PS2, Line 809: elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)?
> `spaces required around that '?' (ctx:VxE)`
Please fix. Also mentioned to use `ENV_RAMSTAGE` and not `CONFIG(SOC_INTEL_CSE_LITE_SYNC_IN_RAMSTAGE)`.
https://review.coreboot.org/c/coreboot/+/85219/comment/1337a1c1_be2b2d4e?us… :
PS2, Line 810: ELOG_FW_LATE_CSE_SYNC:ELOG_FW_EARLY_CSE_SYNC);
> `labels should not be indented`
Please fix. Without space before and after `:`, checkpatch is treating this line as a label.
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Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place
......................................................................
Patch Set 4: Code-Review+1
(1 comment)
File src/soc/intel/meteorlake/romstage/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/85111/comment/a2a21b2e_3a01df84?us… :
PS4, Line 459: if (CONFIG(SOC_INTEL_CSE_LITE_SKU) && is_cse_fw_update_required()) {
Should we check here too whether CSE is in RO and not in RW, to avoid redundant ESOL_CSE_SYNC event logs?
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Change subject: soc/intel/lockdown: Allow locking down SPI and LPC in SMM
......................................................................
Patch Set 3: Code-Review+1
(1 comment)
File src/soc/intel/alderlake/finalize.c:
https://review.coreboot.org/c/coreboot/+/85278/comment/e19caa76_c8d3a8db?us… :
PS3, Line 88: if (CONFIG(INTEL_CHIPSET_LOCKDOWN) || acpi_is_wakeup_s3())
> Excuse my ignorance, why is `acpi_is_wakeup_s3()` added?
As I understand it, it's because the payload is not executed in the S3 resume path, so it won't have the chance to call APM_CNT_FINALIZE itself.
src/southbridge/intel/lynxpoint for example handles it the same way.
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Change subject: mb/google/brox/var/jubilant: Apply ISH_FW_VERSION in Kconfig
......................................................................
Patch Set 2:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85580/comment/99676b12_c72a3179?us… :
PS2, Line 16: form
Nit: from
File src/mainboard/google/brox/Kconfig:
https://review.coreboot.org/c/coreboot/+/85580/comment/79b92352_6f873e07?us… :
PS1, Line 89: select SOC_INTEL_STORE_ISH_FW_VERSION if DRIVERS_INTEL_ISH
> do you mind following the alphabetic order ?>
Also it feels better to move it under BOARD_GOOGLE_BROX_COMMON. That way it applies to all Brox Boards. I am pretty sure all Brox variants have UFS SKUs.
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Change subject: soc/intel/pantherlake: Add core scaling factors read support
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Change subject: soc/intel/common: Read core scaling factors at runtime support
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Change subject: mb/google/fatcat: Limit Power Limit when battery is missing
......................................................................
Patch Set 17:
(1 comment)
Patchset:
PS17:
> I would like to of course as I do not enjoy having pending CLs. However, I would like to have a good understanding of the side effects. I am going to consult internally. I will keep you posted.
we are also exploring implementing an EC API to understand if barrel attached if yes, then we should be able to apply some W/A to skip such limiting of power. But that is nothing POR as this moment
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