coreboot-gerrit December 2024

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[S] Change in coreboot[main]: amdfwtool: Add combo_index into context
by Bao Zheng (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85590?usp=email to review the following change. Change subject: amdfwtool: Add combo_index into context ...................................................................... amdfwtool: Add combo_index into context It will be checked in function in later change. Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c M util/amdfwtool/amdfwtool.h 2 files changed, 14 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/90/85590/1 diff --git a/util/amdfwtool/amdfwtool.c b/util/amdfwtool/amdfwtool.c index c742242..3e0aba4 100644 --- a/util/amdfwtool/amdfwtool.c +++ b/util/amdfwtool/amdfwtool.c @@ -1705,7 +1705,6 @@ int main(int argc, char **argv) { int retval = 0; - int combo_index = 0; int targetfd; context ctx = { 0 }; uint32_t romsig_offset; @@ -1796,17 +1795,17 @@ ctx.bhd_combo_dir = new_combo_dir(&ctx, BHD2_COOKIE); } - combo_index = 0; + ctx.combo_index = 0; if (cb_config.config) cb_config.combo_config[0] = cb_config.config; do { if (cb_config.use_combo && cb_config.debug) - printf("Processing %dth combo entry\n", combo_index); + printf("Processing %dth combo entry\n", ctx.combo_index); /* The pspdir level 1 is special. For new combo layout, all the combo entries share one pspdir L1. It should not be cleared at each iteration. */ - if (!cb_config.combo_new_rab || combo_index == 0) { + if (!cb_config.combo_new_rab || ctx.combo_index == 0) { ctx.pspdir = NULL; ctx.pspdir_bak = NULL; } @@ -1823,14 +1822,14 @@ * and make it clear this will not affect non-combo * case. */ - if (cb_config.use_combo && combo_index > 0) { + if (cb_config.use_combo && ctx.combo_index > 0) { /* Restore the table as clean data. */ memcpy(amd_psp_fw_table, ctx.amd_psp_fw_table_clean, sizeof(amd_psp_fw_table)); memcpy(amd_bios_table, ctx.amd_bios_table_clean, sizeof(amd_bios_table)); - assert_fw_entry(combo_index, MAX_COMBO_ENTRIES, &ctx); - open_process_config(cb_config.combo_config[combo_index], &cb_config); + assert_fw_entry(ctx.combo_index, MAX_COMBO_ENTRIES, &ctx); + open_process_config(cb_config.combo_config[ctx.combo_index], &cb_config); /* In most cases, the address modes are same. */ if (cb_config.need_ish) @@ -1840,7 +1839,7 @@ else ctx.address_mode = AMD_ADDR_PHYSICAL; - register_apcb_combo(&cb_config, combo_index, &ctx); + register_apcb_combo(&cb_config, ctx.combo_index, &ctx); } if (cb_config.multi_level) { @@ -1858,7 +1857,7 @@ } integrate_bios_levels(&ctx, &cb_config); } - if (!cb_config.combo_new_rab || combo_index == 0) + if (!cb_config.combo_new_rab || ctx.combo_index == 0) integrate_psp_firmwares(&ctx, amd_psp_fw_table, PSP_COOKIE, &cb_config); integrate_psp_levels(&ctx, &cb_config); @@ -1868,13 +1867,13 @@ amd_psp_fw_table, PSP_COOKIE, &cb_config); } - if (!cb_config.use_combo || (cb_config.combo_new_rab && combo_index == 0)) { + if (!cb_config.use_combo || (cb_config.combo_new_rab && ctx.combo_index == 0)) { /* For new combo layout, there is only 1 PSP level 1 directory. */ fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir, &ctx, &cb_config); fill_psp_bak_directory_to_efs(ctx.amd_romsig_ptr, ctx.pspdir_bak, &ctx, &cb_config); } else if (cb_config.use_combo && !cb_config.combo_new_rab) { fill_psp_directory_to_efs(ctx.amd_romsig_ptr, ctx.psp_combo_dir, &ctx, &cb_config); - add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, combo_index, &ctx, &cb_config); + add_combo_entry(ctx.psp_combo_dir, ctx.pspdir, ctx.combo_index, &ctx, &cb_config); } if (have_bios_tables(amd_bios_table) && !cb_config.recovery_ab) { @@ -1899,13 +1898,13 @@ */ fill_bios_directory_to_efs(ctx.amd_romsig_ptr, ctx.bhd_combo_dir, &ctx, &cb_config); - add_combo_entry(ctx.bhd_combo_dir, ctx.biosdir, combo_index, &ctx, &cb_config); + add_combo_entry(ctx.bhd_combo_dir, ctx.biosdir, ctx.combo_index, &ctx, &cb_config); } } if (cb_config.debug) dump_image_addresses(&ctx); - } while (cb_config.use_combo && ++combo_index < MAX_COMBO_ENTRIES && - cb_config.combo_config[combo_index] != NULL); + } while (cb_config.use_combo && ++ctx.combo_index < MAX_COMBO_ENTRIES && + cb_config.combo_config[ctx.combo_index] != NULL); targetfd = open(cb_config.output, O_RDWR | O_CREAT | O_TRUNC, 0666); if (targetfd >= 0) { diff --git a/util/amdfwtool/amdfwtool.h b/util/amdfwtool/amdfwtool.h index f87fbf5..3c773f7 100644 --- a/util/amdfwtool/amdfwtool.h +++ b/util/amdfwtool/amdfwtool.h @@ -447,6 +447,7 @@ uint32_t current; /* pointer within flash & proxy buffer */ uint32_t current_pointer_saved; uint32_t current_table; + uint32_t combo_index; void *amd_psp_fw_table_clean; void *amd_bios_table_clean; struct _combo_apcb { -- To view, visit https://review.coreboot.org/c/coreboot/+/85590?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b026b0630a18d1f46bff98ffe5f11e7f930d7a8 Gerrit-Change-Number: 85590 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

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[XS] Change in coreboot[main]: amdfwtool: Set address mode of BIOS binary as context defines
by Bao Zheng (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Bao Zheng, Zheng Bao. Hello Zheng Bao, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85466?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Set address mode of BIOS binary as context defines ...................................................................... amdfwtool: Set address mode of BIOS binary as context defines TEST=Binary identical test on platforms before mendocino Tested on Skyrim Change-Id: I9c2f2983d03c913b28fbd87aa0925a32a4649d62 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/85466/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85466?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c2f2983d03c913b28fbd87aa0925a32a4649d62 Gerrit-Change-Number: 85466 Gerrit-PatchSet: 3 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Zheng Bao

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[S] Change in coreboot[main]: amdfwtool: Move ISH before PSP L2
by Bao Zheng (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Bao Zheng, Felix Held, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84533?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Move ISH before PSP L2 ...................................................................... amdfwtool: Move ISH before PSP L2 The amdfw.rom will be divided into 3 parts: PSP L1, PSP L2A, PSP L2B The two ISHs are close to L1 and can be combined as a cbfs module. To do that, move the new_psp_dir for L1 and L2 to separated branches. Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 24 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/84533/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84533?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id69268619893d78d9b5330052a4fd5b501263f75 Gerrit-Change-Number: 84533 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: amdfwtool: Move L1 before L2
by Bao Zheng (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Bao Zheng, Felix Held, Marshall Dawson, Zheng Bao, ritul guru. Hello Felix Held, Marshall Dawson, Zheng Bao, build bot (Jenkins), ritul guru, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84532?usp=email to look at the new patch set (#5). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: amdfwtool: Move L1 before L2 ...................................................................... amdfwtool: Move L1 before L2 It is more reasonable. Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M util/amdfwtool/amdfwtool.c 1 file changed, 16 insertions(+), 14 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/84532/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/84532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I74605013cf53a38686f4e1e5a89a4e6a870f1f4b Gerrit-Change-Number: 84532 Gerrit-PatchSet: 5 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Configuration USB ports and mapping
by Kapil Porwal (Code Review) 14 Dec '24

14 Dec '24

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Configuration serial_io and I2C
by Kapil Porwal (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85581?usp=email ) Change subject: mb/trulo/var/uldrenite: Configuration serial_io and I2C ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/85581/comment/62b7d5e1_118f88a5?us… : PS2, Line 615: select SOC_INTEL_TWINLAKE > Move it to another CL. May be a new CL. You can remove it. It is already selected by BOARD_GOOGLE_BASEBOARD_TRULO -- To view, visit https://review.coreboot.org/c/coreboot/+/85581?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c1b6028c7e4392a2142851d5fd0199954e2272d Gerrit-Change-Number: 85581 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 14 Dec 2024 04:26:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Enable eMMC and DLL tuning parameters
by Kapil Porwal (Code Review) 14 Dec '24

14 Dec '24

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Configuration serial_io and I2C
by Kapil Porwal (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Nick Vaccaro, Subrata Banik. Kapil Porwal has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85581?usp=email ) Change subject: mb/trulo/var/uldrenite: Configuration serial_io and I2C ...................................................................... Patch Set 2: (7 comments) File src/mainboard/google/brya/Kconfig: https://review.coreboot.org/c/coreboot/+/85581/comment/ae4359e7_7f1c4846?us… : PS2, Line 615: select SOC_INTEL_TWINLAKE Move it to another CL. May be a new CL. File src/mainboard/google/brya/variants/uldrenite/overridetree.cb: https://review.coreboot.org/c/coreboot/+/85581/comment/5d86aabf_603b8b4f?us… : PS2, Line 96: # FIXME: To be enabled in future based on PNP impact data. : # Disable Package C-state demotion for nissa baseboard. : register "disable_package_c_state_demotion" = "true" Move to PnP CL https://review.coreboot.org/c/coreboot/+/85581/comment/2b7ccaad_314be38e?us… : PS2, Line 221: probed Change it to `detect` https://review.coreboot.org/c/coreboot/+/85581/comment/0a446ae7_76992e83?us… : PS2, Line 237: 280 Same as below https://review.coreboot.org/c/coreboot/+/85581/comment/e04c85ff_989eea71?us… : PS2, Line 255: 300 This is very high. This will impact s0ix suspend/resume time. https://review.coreboot.org/c/coreboot/+/85581/comment/b6aa4708_39bf0eec?us… : PS2, Line 306: device ref heci1 on end Move to PnP CL https://review.coreboot.org/c/coreboot/+/85581/comment/938f68f4_e0a79fc6?us… : PS2, Line 314: device ref pmc hidden end Move to PnP CL -- To view, visit https://review.coreboot.org/c/coreboot/+/85581?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c1b6028c7e4392a2142851d5fd0199954e2272d Gerrit-Change-Number: 85581 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 14 Dec 2024 04:23:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Yidi Lin (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Xiwen Shao. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 26: Code-Review+2 (1 comment) Patchset: PS26: ``` src/soc/mediatek/mt8196/tracker.c:82:11: error: use of undeclared identifier 'VLP_AO_BASE'; did you mean 'VLPCFG_BASE'? 82 | write32p(VLP_AO_BASE + VLP_CON_AO, val); | ^~~~~~~~~~~ | VLPCFG_BASE src/soc/mediatek/mt8196/include/soc/addressmap.h:145:2: note: 'VLPCFG_BASE' declared here 145 | VLPCFG_BASE = IO_PHYS + 0x0C001000, | ^ 1 error generated. make[2]: *** [Makefile:430: /cb-build/coreboot-gerrit.0/clang-chromeos/GOOGLE_HYLIA/bootblock/soc/mediatek/mt8196/tracker.o] Error 1 make[2]: Leaving directory '/home/coreboot/node-root/workspace/coreboot-gerrit' ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 26 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Sat, 14 Dec 2024 03:16:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: lib/{fit,fit_payload}.c: Enhance support for FIT images
by Benjamin Doron (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Lean Sheng Tan, Matt DeVillier, Maximilian Brune. Benjamin Doron has posted comments on this change by Benjamin Doron. ( https://review.coreboot.org/c/coreboot/+/84796?usp=email ) Change subject: lib/{fit,fit_payload}.c: Enhance support for FIT images ...................................................................... Patch Set 5: (1 comment) File src/lib/fit_payload.c: https://review.coreboot.org/c/coreboot/+/84796/comment/057728f0_d7f08b1c?us… : PS5, Line 105: load_secondaries This doesn't even make an effort to check if a load address was requested. And as I comment on the x86 code, we may want to check if relocation is needed and then at least do *something*: either relocation, or print an error. Generally, we should consume more of the image properties, perhaps config's `require-fit` too, and either handle them properly or print errors if the system is getting into an unexpected state. -- To view, visit https://review.coreboot.org/c/coreboot/+/84796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a21954c0dc5fd820d135e8cd0599ce87903a1c0 Gerrit-Change-Number: 84796 Gerrit-PatchSet: 5 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Fri, 13 Dec 2024 19:59:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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coreboot-gerrit December 2024