coreboot-gerrit December 2024

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[S] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Patrick Rudolph (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Jérémy Compostella, Patrick Rudolph, Shuo Liu, Subrata Banik, Uwe Poeche, yuchi.chen(a)intel.com. Hello Christian Walter, Jincheng Li, Jérémy Compostella, Shuo Liu, Subrata Banik, Uwe Poeche, build bot (Jenkins), siemens-bot, yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85568?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Jérémy Compostella, Code-Review+1 by Uwe Poeche, Code-Review+2 by Christian Walter, Code-Review+2 by Shuo Liu, Verified+1 by build bot (Jenkins), Verified+1 by siemens-bot The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... cpu/intel/car/romstage: Fix false-positive stack corruption Fix regression introduced in commit 03518727313119a8c7a273eb745663c99f8e4d22 ("arch/x86: Add breakpoint to stack canary"). romstage_main writes to the stack-canary, but since that's expected temporarily disable the breakpoint. This only caused a warning on platforms that do select IDT_IN_EVERY_STAGE, since those install the stack canary breakpoint. TEST: No more exceptions are printed in romstage when IDT_IN_EVERY_STAGE is enabled. Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 18 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/85568/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 2 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com>

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[XS] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Shuo Liu (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Jincheng Li, Patrick Rudolph, Subrata Banik, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 1: Code-Review+2 (1 comment) File src/cpu/intel/car/romstage.c: https://review.coreboot.org/c/coreboot/+/85568/comment/c0e725e7_fd31dd06?us… : PS1, Line 44: > Maybe add comments to specify stack canary and stack guard servers different purposes? e.g. […] Unblock the merge so that the regression could be fixed soon. -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Sat, 14 Dec 2024 09:43:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[XS] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Shuo Liu (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Jincheng Li, Patrick Rudolph, Subrata Banik, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 1: (1 comment) File src/cpu/intel/car/romstage.c: https://review.coreboot.org/c/coreboot/+/85568/comment/d1d909fd_4174acb9?us… : PS1, Line 40: stack_canary_breakpoint_remove(); > It cannot be enabled without an IDT in place. Acknowledged -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Sat, 14 Dec 2024 09:34:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Angel Pons (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Mark Chang, Patrick Rudolph, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85532/comment/5716ad9e_b0b3f21b?us… : PS4, Line 7: Add support for MiTAC Computing Whitestone-2 mainboard > > mainboard: Add support for MiTAC Computing Whitestone-2 As for mentioning the SOC/processor/socket in the summary, it won't fit. This info should be in the commit message body, though. -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wilson-MiTACComputing <wilson.chien(a)mitaccomputing.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Sat, 14 Dec 2024 09:30:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Angel Pons (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Mark Chang, Patrick Rudolph, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85532/comment/3e01d697_eaf287cd?us… : PS4, Line 7: Add support for MiTAC Computing Whitestone-2 mainboard > mainboard: Add support for MiTAC Computing Whitestone-2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wilson-MiTACComputing <wilson.chien(a)mitaccomputing.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Sat, 14 Dec 2024 09:29:37 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Paul Menzel (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Mark Chang, Patrick Rudolph, yuchi.chen(a)intel.com. Paul Menzel has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85532/comment/520b283b_de9eef7f?us… : PS4, Line 7: Add support for MiTAC Computing Whitestone-2 mainboard 1. Add prefix *mainboard*. 2. Mention the SOC/processor/socket in the summary/title? -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Wilson-MiTACComputing <wilson.chien(a)mitaccomputing.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Sat, 14 Dec 2024 09:24:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels
by Paul Menzel (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Eric Lai, Jamie Chen, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford. Paul Menzel has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add function to force disable memory channels ...................................................................... Patch Set 6: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85529/comment/022a2819_2ba09ef3?us… : PS3, Line 8: > Looking at DMI info is a simple way to show what happens when using the channel disable mask. Yes, I understand. The motivation could still be better described. I guess “memory channel” is ambiguous, and it’s not directly clear, that FSP or some other mechanism hides this from coreboot already. -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Sat, 14 Dec 2024 09:23:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[L] Change in coreboot[main]: [test] upgrade crossgcc
by Elyes Haouas (Code Review) 14 Dec '24

14 Dec '24

Elyes Haouas has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85591?usp=email ) Change subject: [test] upgrade crossgcc ...................................................................... [test] upgrade crossgcc Change-Id: Ic325b9af34c113843d664c9b781b60177b6f4b32 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc D util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch D util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch D util/crossgcc/patches/gcc-14.2.0_gnat.patch D util/crossgcc/patches/gcc-14.2.0_libcpp.patch D util/crossgcc/patches/gcc-14.2.0_libgcc.patch D util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch D util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch D util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/clang-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/clang-tools-extra-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/cmake-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum A util/crossgcc/sum/cmake-3.31.2.tar.gz.cksum D util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/compiler-rt-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum A util/crossgcc/sum/gcc-15-20241208.tar.xz.cksum D util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum D util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/lld-19.1.5.src.tar.xz.cksum D util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum A util/crossgcc/sum/llvm-19.1.5.src.tar.xz.cksum 25 files changed, 12 insertions(+), 524 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/91/85591/1 diff --git a/util/crossgcc/buildgcc b/util/crossgcc/buildgcc index 029abce..cd86d64 100755 --- a/util/crossgcc/buildgcc +++ b/util/crossgcc/buildgcc @@ -38,12 +38,12 @@ GMP_VERSION=6.3.0 MPFR_VERSION=4.2.1 MPC_VERSION=1.3.1 -GCC_VERSION=14.2.0 +GCC_VERSION=15-20241208 BINUTILS_VERSION=2.43.1 IASL_VERSION=20241212 # CLANG version number -CLANG_VERSION=18.1.8 -CMAKE_VERSION=3.30.2 +CLANG_VERSION=19.1.5 +CMAKE_VERSION=3.31.2 NASM_VERSION=2.16.03 # Filename for each package @@ -72,7 +72,7 @@ GMP_BASE_URL="https://ftpmirror.gnu.org/gmp" MPFR_BASE_URL="https://ftpmirror.gnu.org/mpfr" MPC_BASE_URL="https://ftpmirror.gnu.org/mpc" -GCC_BASE_URL="https://ftpmirror.gnu.org/gcc/gcc-${GCC_VERSION}" +GCC_BASE_URL="https://gcc.gnu.org/pub/gcc/snapshots/15-20241208" BINUTILS_BASE_URL="https://ftpmirror.gnu.org/binutils" IASL_BASE_URL="https://github.com/acpica/acpica/releases/download/R2024_12_12" # CLANG toolchain archive locations diff --git a/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch b/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch deleted file mode 100644 index 61c608c..0000000 --- a/util/crossgcc/patches/clang-18.1.8.src_x86_baremetal.patch +++ /dev/null @@ -1,29 +0,0 @@ -diff --git a/lib/Driver/ToolChains/BareMetal.cpp b/lib/Driver/ToolChains/BareMetal.cpp -index 852e0442..eb84a785 100644 ---- a/lib/Driver/ToolChains/BareMetal.cpp -+++ b/lib/Driver/ToolChains/BareMetal.cpp -@@ -169,6 +169,12 @@ static bool isPPCBareMetal(const llvm::Triple &Triple) { - Triple.getEnvironment() == llvm::Triple::EABI; - } - -+/// Is the triple x86_32 or x86_64 -*-none-elf? -+static bool isX86BareMetal(const llvm::Triple &Triple) { -+ return Triple.isX86() && Triple.getOS() == llvm::Triple::UnknownOS && -+ Triple.getEnvironmentName() == "elf"; -+} -+ - static void findMultilibsFromYAML(const ToolChain &TC, const Driver &D, - StringRef MultilibPath, const ArgList &Args, - DetectedMultilibs &Result) { -@@ -234,9 +240,10 @@ void BareMetal::findMultilibs(const Driver &D, const llvm::Triple &Triple, - - bool BareMetal::handlesTarget(const llvm::Triple &Triple) { - return isARMBareMetal(Triple) || isAArch64BareMetal(Triple) || -- isRISCVBareMetal(Triple) || isPPCBareMetal(Triple); -+ isRISCVBareMetal(Triple) || isPPCBareMetal(Triple) || isX86BareMetal(Triple); - } - -+ - Tool *BareMetal::buildLinker() const { - return new tools::baremetal::Linker(*this); - } diff --git a/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch b/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch deleted file mode 100644 index d446025..0000000 --- a/util/crossgcc/patches/gcc-14.2.0_asan_shadow_offset_callback.patch +++ /dev/null @@ -1,88 +0,0 @@ -From 41a82fb711f3637b4b7f57756492b628058f9d5f Mon Sep 17 00:00:00 2001 -From: Harshit Sharma <harshitsharmajs(a)gmail.com> -Date: Fri, 10 Jul 2020 13:06:08 -0700 -Subject: [PATCH] crossgcc: Enable GCC to get asan shadow offset at runtime - -Unlike Linux kernel which has a static shadow region layout, we have multiple stages in -coreboot and thus require a different shadow offset address. Unfortunately, GCC currently -only supports adding a static shadow offset at compile time using -fasan-shadow-offset flag. - -For this reason, we enable GCC to determine asan shadow offset address at runtime using a -callback function named __asan_shadow_offset(). This supersedes the need to specify this -address at compile time. GCC then makes use of this shadow offset to protect stack buffers -by inserting red zones around them. - -Some other benefits of having this GCC patch are: -a. We can place the shadow region in a separate linker section with all its advantages like - automatic fit insurance. This ensures if a platform doesn't have enough memory space to - hold shadow region, the build will fail. (However, if we use a fixed shadow offset on a - platform that actually doesn't have enough memory, it may still build without any errors.) -b. We don't modify the memory layout compared to the current one, as we are placing the - shadow region at the end of the space already occupied by the program. -c. We can be much more flexible later if needed (thinking of other stages like bootblock). -d. Since we are appending the shadow buffer to the region already occupied, we make efficient - use of the limited memory available which is highly beneficial when using cache as ram. - -Further, we have made sure that if you compile you tree with ASan enabled but missed this -patch, it will end up in the following compilation error: -"invalid --param name 'asan-use-shadow-offset-callback'" -So, you cannot accidentally enable the feature without having your compiler patched. - -[pgeorgi: Updated for gcc 11.1] - -Signed-off-by: Harshit Sharma <harshitsharmajs(a)gmail.com> -Signed-off-by: Patrick Georgi <pgeorgi(a)google.com> - -diff --git a/gcc/asan.c b/gcc/asan.c -index 235e21947..713bf994d 100644 ---- a/gcc/asan.cc -+++ b/gcc/asan.cc -@@ -1389,13 +1389,28 @@ asan_emit_stack_protection (rtx base, rtx pbase, unsigned int alignb, - TREE_ASM_WRITTEN (decl) = 1; - TREE_ASM_WRITTEN (id) = 1; - emit_move_insn (mem, expand_normal (build_fold_addr_expr (decl))); -- shadow_base = expand_binop (Pmode, lshr_optab, base, -- gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -- NULL_RTX, 1, OPTAB_DIRECT); -- shadow_base -- = plus_constant (Pmode, shadow_base, -- asan_shadow_offset () -- + (base_align_bias >> ASAN_SHADOW_SHIFT)); -+ if (param_asan_use_shadow_offset_callback) { -+ rtx addr, shadow_offset_rtx; -+ ret = init_one_libfunc ("__asan_shadow_offset"); -+ addr = convert_memory_address (ptr_mode, base); -+ ret = emit_library_call_value (ret, NULL_RTX, LCT_NORMAL, ptr_mode, -+ addr, ptr_mode); -+ shadow_offset_rtx = convert_memory_address (Pmode, ret); -+ shadow_base = expand_binop (Pmode, lshr_optab, base, -+ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -+ NULL_RTX, 1, OPTAB_DIRECT); -+ shadow_base = expand_binop (Pmode, add_optab, shadow_base, -+ shadow_offset_rtx, NULL_RTX, 1, OPTAB_LIB_WIDEN); -+ shadow_base = plus_constant (Pmode, shadow_base, -+ (base_align_bias >> ASAN_SHADOW_SHIFT)); -+ } else { -+ shadow_base = expand_binop (Pmode, lshr_optab, base, -+ gen_int_shift_amount (Pmode, ASAN_SHADOW_SHIFT), -+ NULL_RTX, 1, OPTAB_DIRECT); -+ shadow_base = plus_constant (Pmode, shadow_base, -+ asan_shadow_offset () -+ + (base_align_bias >> ASAN_SHADOW_SHIFT)); -+ } - gcc_assert (asan_shadow_set != -1 - && (ASAN_RED_ZONE_SIZE >> ASAN_SHADOW_SHIFT) == 4); - shadow_mem = gen_rtx_MEM (SImode, shadow_base); ---- gcc-11.1.0/gcc/params.opt~ 2021-05-11 09:02:51.897508677 +0200 -+++ gcc-11.1.0/gcc/params.opt 2021-05-11 09:10:43.692610696 +0200 -@@ -50,6 +50,10 @@ - Common Joined UInteger Var(param_asan_instrumentation_with_call_threshold) Init(7000) Param Optimization - Use callbacks instead of inline code if number of accesses in function becomes greater or equal to this number. - -+-param=asan-use-shadow-offset-callback= -+Common Joined UInteger Var(param_asan_use_shadow_offset_callback) Init(0) IntegerRange(0, 1) Param Optimization -+Use shadow offset callback function at runtime instead of fixed value at compile time at the cost of runtime overhead. -+ - -param=asan-memintrin= - Common Joined UInteger Var(param_asan_memintrin) Init(1) IntegerRange(0, 1) Param Optimization - Enable asan builtin functions protection. diff --git a/util/crossgcc/patches/gcc-14.2.0_gnat.patch b/util/crossgcc/patches/gcc-14.2.0_gnat.patch deleted file mode 100644 index 2a37b15..0000000 --- a/util/crossgcc/patches/gcc-14.2.0_gnat.patch +++ /dev/null @@ -1,108 +0,0 @@ -From b1b16478729aea709e7ef81224995b6d26b38a87 Mon Sep 17 00:00:00 2001 -From: Nico Huber <nico.h(a)gmx.de> -Date: Sun, 16 Jul 2023 00:30:03 +0200 -Subject: [PATCH] GNAT: Build cross compilers with host runtime - -When building with an older host toolchain, the shipped libgnat -sources may not be compatible. So rely on the host runtime just -like we do for a stage1 build. - -Signed-off-by: Nico Huber <nico.h(a)gmx.de> ---- - gcc/ada/gcc-interface/Make-lang.in | 16 +++++++++++++--- - gcc/ada/init.c | 4 ++++ - 2 files changed, 17 insertions(+), 3 deletions(-) - -diff --git a/gcc/ada/gcc-interface/Make-lang.in b/gcc/ada/gcc-interface/Make-lang.in -index 9507f2f09203..cf7ec4cc1662 100644 ---- a/gcc/ada/gcc-interface/Make-lang.in -+++ b/gcc/ada/gcc-interface/Make-lang.in -@@ -57,18 +57,21 @@ WARN_ADAFLAGS= -W -Wall - # checks fully active. - - STAGE1=False -+HOST_RT=False - GNATBIND_FLAGS= - GNATLIB= - -+ADAFLAGS=$(COMMON_ADAFLAGS) -gnatwns - ifeq ($(CROSS),) -- ADAFLAGS=$(COMMON_ADAFLAGS) -gnatwns - - ifeq ($(if $(wildcard ../stage_current),$(shell cat ../stage_current),stage1),stage1) - STAGE1=True - GNATBIND_FLAGS=-t -+ HOST_RT=True - endif - else -- ADAFLAGS=$(COMMON_ADAFLAGS) -+ GNATBIND_FLAGS=-t -+ HOST_RT=True - endif - - ALL_ADAFLAGS = \ -@@ -87,7 +89,7 @@ ifeq ($(strip $(filter-out hpux%,$(host_os))),) - STAGE1_LIBS=/usr/lib/libcl.a - endif - --ifeq ($(STAGE1),True) -+ifeq ($(HOST_RT),True) - ADA_INCLUDES=$(COMMON_ADA_INCLUDES) - adalib=$(dir $(shell $(CC) -print-libgcc-file-name))adalib - GNATLIB=$(adalib)/$(if $(wildcard $(adalib)/libgnat.a),libgnat.a,libgnat.so) $(STAGE1_LIBS) -@@ -485,6 +487,7 @@ GNAT1_C_OBJS+= \ - ada/rtinit.o \ - ada/seh_init.o - -+ifeq ($(HOST_RT),False) - GNAT_ADA_OBJS+= \ - ada/gcc-interface/system.o \ - ada/libgnat/a-assert.o \ -@@ -555,6 +558,7 @@ GNAT_ADA_OBJS+= \ - ada/libgnat/s-wchstw.o \ - ada/libgnat/s-widuns.o - endif -+endif - - # Object files for gnat executables - GNAT1_ADA_OBJS = $(GNAT_ADA_OBJS) ada/back_end.o ada/gnat1drv.o -@@ -656,6 +660,9 @@ GNATBIND_OBJS += \ - ada/rtfinal.o \ - ada/rtinit.o \ - ada/seh_init.o \ -+ -+ifeq ($(HOST_RT),False) -+GNATBIND_OBJS += \ - ada/gcc-interface/system.o \ - ada/libgnat/a-assert.o \ - ada/libgnat/a-elchha.o \ -@@ -707,6 +714,9 @@ GNATBIND_OBJS += \ - ada/libgnat/s-wchjis.o \ - ada/libgnat/s-wchstw.o \ - ada/libgnat/s-widuns.o \ -+ -+endif -+GNATBIND_OBJS += \ - ada/adaint.o \ - ada/argv.o \ - ada/cio.o \ -diff --git a/gcc/ada/init.c b/gcc/ada/init.c -index 5212a38490d3..5ae2efd32ef3 100644 ---- a/gcc/ada/init.c -+++ b/gcc/ada/init.c -@@ -93,8 +93,12 @@ extern struct Exception_Data storage_error; - #ifdef CERT - #define Raise_From_Signal_Handler __gnat_raise_exception - #else -+#if __GNUC__ < 12 -+#define Raise_From_Signal_Handler ada__exceptions__raise_from_signal_handler -+#else - #define Raise_From_Signal_Handler __gnat_raise_from_signal_handler - #endif -+#endif - - extern void Raise_From_Signal_Handler (struct Exception_Data *, const void *) - ATTRIBUTE_NORETURN; --- -2.39.0 - diff --git a/util/crossgcc/patches/gcc-14.2.0_libcpp.patch b/util/crossgcc/patches/gcc-14.2.0_libcpp.patch deleted file mode 100644 index 2b0c953..0000000 --- a/util/crossgcc/patches/gcc-14.2.0_libcpp.patch +++ /dev/null @@ -1,56 +0,0 @@ -GCC with `-Wformat-security -Werror=format-security` hardening options enabled -by default rejects some codes in libcpp. This patch fixes them. - ---- gcc-8.3.0/libcpp/expr.cc.bak 2020-09-11 15:44:45.770000000 +0900 -+++ gcc-8.3.0/libcpp/expr.cc 2020-09-11 15:46:22.370000000 +0900 -@@ -794,10 +794,10 @@ - - if (CPP_OPTION (pfile, c99)) - cpp_warning_with_line (pfile, CPP_W_LONG_LONG, virtual_location, -- 0, message); -+ 0, "%s", message); - else - cpp_pedwarning_with_line (pfile, CPP_W_LONG_LONG, -- virtual_location, 0, message); -+ virtual_location, 0, "%s", message); - } - - result |= CPP_N_INTEGER; ---- gcc-8.3.0/libcpp/macro.cc.bak 2020-09-11 16:01:42.550000000 +0900 -+++ gcc-8.3.0/libcpp/macro.cc 2020-09-11 16:03:47.850000000 +0900 -@@ -160,7 +160,7 @@ - if (m_state == 2 && token->type == CPP_PASTE) - { - cpp_error_at (m_pfile, CPP_DL_ERROR, token->src_loc, -- vaopt_paste_error); -+ "%s", vaopt_paste_error); - return ERROR; - } - /* Advance states before further considering this token, in -@@ -189,7 +189,7 @@ - if (was_paste) - { - cpp_error_at (m_pfile, CPP_DL_ERROR, token->src_loc, -- vaopt_paste_error); -+ "%s", vaopt_paste_error); - return ERROR; - } - -@@ -3361,7 +3361,7 @@ - function-like macros, but not at the end. */ - if (following_paste_op) - { -- cpp_error (pfile, CPP_DL_ERROR, paste_op_error_msg); -+ cpp_error (pfile, CPP_DL_ERROR, "%s", paste_op_error_msg); - goto out; - } - if (!vaopt_tracker.completed ()) -@@ -3374,7 +3374,7 @@ - function-like macros, but not at the beginning. */ - if (macro->count == 1) - { -- cpp_error (pfile, CPP_DL_ERROR, paste_op_error_msg); -+ cpp_error (pfile, CPP_DL_ERROR, "%s", paste_op_error_msg); - goto out; - } - diff --git a/util/crossgcc/patches/gcc-14.2.0_libgcc.patch b/util/crossgcc/patches/gcc-14.2.0_libgcc.patch deleted file mode 100644 index 2f75c92..0000000 --- a/util/crossgcc/patches/gcc-14.2.0_libgcc.patch +++ /dev/null @@ -1,60 +0,0 @@ -This enables building on Mac OS and FreeBSD by adding support to their -variants of the sed utility. - -diff -urN gcc-5.2.0.orig/libgcc/config/t-hardfp gcc-5.2.0/libgcc/config/t-hardfp ---- gcc-5.2.0.orig/libgcc/config/t-hardfp 2015-01-05 04:33:28.000000000 -0800 -+++ gcc-8.1.0/libgcc/config/t-hardfp 2016-04-06 12:04:51.000000000 -0700 -@@ -59,21 +59,52 @@ - - hardfp_func_list := $(filter-out $(hardfp_exclusions),$(hardfp_func_list)) - -+HOST_OS ?= $(shell uname) -+ - # Regexp for matching a floating-point mode. -+ifeq ($(HOST_OS), Darwin) -+hardfp_mode_regexp := $(shell echo $(hardfp_float_modes) | sed 's/ /|/g') -+else -+ifeq ($(HOST_OS), FreeBSD) -+hardfp_mode_regexp := $(shell echo $(hardfp_float_modes) | sed 's/ /|/g') -+else - hardfp_mode_regexp := $(shell echo $(hardfp_float_modes) | sed 's/ /\\|/g') -+endif -+endif - - # Regexp for matching the end of a function name, after the last - # floating-point mode. -+ifeq ($(HOST_OS), Darwin) -+hardfp_suffix_regexp := $(shell echo $(hardfp_int_modes) 2 3 | sed 's/ /|/g') -+else -+ifeq ($(HOST_OS), FreeBSD) -+hardfp_suffix_regexp := $(shell echo $(hardfp_int_modes) 2 3 | sed 's/ /|/g') -+else - hardfp_suffix_regexp := $(shell echo $(hardfp_int_modes) 2 3 | sed 's/ /\\|/g') -+endif -+endif - - # Add -D options to define: - # FUNC: the function name (e.g. __addsf3) - # OP: the function name without the leading __ and with the last - # floating-point mode removed (e.g. add3) - # TYPE: the last floating-point mode (e.g. sf) -+ -+ifeq ($(HOST_OS), Darwin) - hardfp_defines_for = \ - $(shell echo $1 | \ -- sed 's/$.*$$$(hardfp_mode_regexp)$$$(hardfp_suffix_regexp)\|$$$/-DFUNC=__& -DOP_\1\3 -DTYPE=\2/') -+ sed -E 's/(.*)($(hardfp_mode_regexp))($(hardfp_suffix_regexp)|.*)$$/-DFUNC=__& -DOP_\1\3 -DTYPE=\2/') -+else -+ifeq ($(HOST_OS), FreeBSD) -+hardfp_defines_for = \ -+ $(shell echo $1 | \ -+ sed -r 's/(.*)($(hardfp_mode_regexp))($(hardfp_suffix_regexp)|.*)$$/-DFUNC=__& -DOP_\1\3 -DTYPE=\2/') -+else -+hardfp_defines_for = \ -+ $(shell echo $1 | \ -+ sed 's/$.*$$$(hardfp_mode_regexp)$$$(hardfp_suffix_regexp)\|$$$/-DFUNC=__& -DOP_\1\3 -DTYPE=\2/') -+endif -+endif - - hardfp-o = $(patsubst %,%$(objext),$(hardfp_func_list)) - $(hardfp-o): %$(objext): $(srcdir)/config/hardfp.c diff --git a/util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch b/util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch deleted file mode 100644 index b66380d..0000000 --- a/util/crossgcc/patches/gcc-14.2.0_musl_poisoned_calloc.patch +++ /dev/null @@ -1,115 +0,0 @@ -Musl's <sched.h> uses calloc() which is marked as poisoned by GCC's -"system.h". Work around that by making sure that <sched.h> gets -included first. - ---- gcc-13.2.0/gcc/ada/adaint.c -+++ gcc-13.2.0.musl/gcc/ada/adaint.c -@@ -101,6 +101,10 @@ - #include <sys/time.h> - #endif - -+#if defined (__linux__) -+#include <sched.h> -+#endif -+ - #ifdef IN_RTS - - #ifdef STANDALONE -@@ -3441,7 +3445,6 @@ - #endif - - #if defined (__linux__) --#include <sched.h> - - /* glibc versions earlier than 2.7 do not define the routines to handle - dynamically allocated CPU sets. For these targets, we use the static ---- gcc-14-20240211/gcc/ada/argv.c -+++ gcc-14-20240211.musl/gcc/ada/argv.c -@@ -51,10 +51,6 @@ - #include "system.h" - #endif - --#ifndef LIGHT_RUNTIME --#include "adaint.h" --#endif -- - #ifdef __cplusplus - extern "C" { - #endif ---- gcc-13.2.0/gcc/ada/cio.c -+++ gcc-13.2.0.musl/gcc/ada/cio.c -@@ -29,6 +29,8 @@ - * * - ****************************************************************************/ - -+#include "adaint.h" -+ - #ifdef IN_RTS - #include "runtime.h" - #include <sys/stat.h> -@@ -36,8 +38,6 @@ - #include "config.h" - #include "system.h" - #endif -- --#include "adaint.h" - - /* We need L_tmpnam definition */ - #include <stdio.h> ---- gcc-13.2.0/gcc/ada/cstreams.c -+++ gcc-13.2.0.musl/gcc/ada/cstreams.c -@@ -58,14 +58,14 @@ - #include "vxWorks.h" - #endif - -+#include "adaint.h" -+ - #ifdef IN_RTS - #include <string.h> - #else - #include "config.h" - #include "system.h" - #endif -- --#include "adaint.h" - - #ifdef __cplusplus - extern "C" { ---- gcc-13.2.0/gcc/ada/init.c -+++ gcc-13.2.0.musl/gcc/ada/init.c -@@ -53,6 +53,8 @@ - #undef __linux__ - #endif - -+#include "adaint.h" -+ - #ifdef IN_RTS - - #ifdef STANDALONE -@@ -71,7 +73,6 @@ - #include "system.h" - #endif - --#include "adaint.h" - #include "raise.h" - - #ifdef __cplusplus ---- gcc-13.2.0/gcc/ada/raise.c -+++ gcc-13.2.0.musl/gcc/ada/raise.c -@@ -32,6 +32,8 @@ - /* Shared routines to support exception handling. __gnat_unhandled_terminate - is shared between all exception handling mechanisms. */ - -+#include "adaint.h" -+ - #ifdef IN_RTS - #include "runtime.h" - #else -@@ -39,7 +41,6 @@ - #include "system.h" - #endif - --#include "adaint.h" - #include "raise.h" - - #ifdef __cplusplus diff --git a/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch b/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch deleted file mode 100644 index 5b0d715..0000000 --- a/util/crossgcc/patches/gcc-14.2.0_rv32iafc.patch +++ /dev/null @@ -1,55 +0,0 @@ -From 88bc675eab98cea388daf40396686178ca5fcdb3 Mon Sep 17 00:00:00 2001 -From: Peter Marheine <pmarheine(a)chromium.org> -Date: Mon, 15 Aug 2022 11:01:50 +1000 -Subject: [PATCH] riscv: elf-multilib: add rv32iafc to defaults - -rv32iafc-ilp32 is compatible with rv32iac-ilp32 for library -implementation, so add a reuse rule allowing the default configuration -to support rv32iafc. - --IAFC is an unusual configuration (much less common than -IMAFC), but -multilib reuse has essentially no cost: this change is useful to users -of platforms that support hardware floating-point but cannot use -hardware multiply/divide for any reason. To avoid generating a new set -of libraries this is limited to the soft-float ABI. - -Tested by verifying that `gcc -march=rv32iafc -mabi=ilp32 ---print-search-dirs` refers to the rv32iac/ilp32 library directory as -expected, rather than just the root library directory as occurs when an -unsupported target is selected (for instance, rv32id). - -Signed-off-by: Peter Marheine <pmarheine(a)chromium.org> ---- - gcc/config/riscv/t-elf-multilib | 6 ++++-- - 1 file changed, 4 insertions(+), 2 deletions(-) - -diff --git a/gcc/config/riscv/t-elf-multilib b/gcc/config/riscv/t-elf-multilib -index 19f9434616c..6e74b1811be 100644 ---- a/gcc/config/riscv/t-elf-multilib -+++ b/gcc/config/riscv/t-elf-multilib -@@ -1,11 +1,12 @@ - # This file was generated by multilib-generator with the command: --# ./multilib-generator rv32i-ilp32--c rv32im-ilp32--c rv32iac-ilp32-- rv32imac-ilp32-- rv32imafc-ilp32f-rv32imafdc- rv64imac-lp64-- rv64imafdc-lp64d-- --MULTILIB_OPTIONS = march=rv32i/march=rv32ic/march=rv32im/march=rv32imc/march=rv32iac/march=rv32imac/march=rv32imafc/march=rv32imafdc/march=rv32gc/march=rv64imac/march=rv64imafdc/march=rv64gc mabi=ilp32/mabi=ilp32f/mabi=lp64/mabi=lp64d -+# ./multilib-generator rv32i-ilp32--c rv32im-ilp32--c rv32iac-ilp32--f rv32imac-ilp32-- rv32imafc-ilp32f-rv32imafdc- rv64imac-lp64-- rv64imafdc-lp64d-- -+MULTILIB_OPTIONS = march=rv32i/march=rv32ic/march=rv32im/march=rv32imc/march=rv32iac/march=rv32iafc/march=rv32imac/march=rv32imafc/march=rv32imafdc/march=rv32gc/march=rv64imac/march=rv64imafdc/march=rv64gc mabi=ilp32/mabi=ilp32f/mabi=lp64/mabi=lp64d - MULTILIB_DIRNAMES = rv32i \ - rv32ic \ - rv32im \ - rv32imc \ - rv32iac \ -+rv32iafc \ - rv32imac \ - rv32imafc \ - rv32imafdc \ -@@ -25,6 +26,7 @@ march=rv64imac/mabi=lp64 \ - march=rv64imafdc/mabi=lp64d - MULTILIB_REUSE = march.rv32i/mabi.ilp32=march.rv32ic/mabi.ilp32 \ - march.rv32im/mabi.ilp32=march.rv32imc/mabi.ilp32 \ -+march.rv32iac/mabi.ilp32=march.rv32iafc/mabi.ilp32 \ - march.rv32imafc/mabi.ilp32f=march.rv32imafdc/mabi.ilp32f \ - march.rv32imafc/mabi.ilp32f=march.rv32gc/mabi.ilp32f \ - march.rv64imafdc/mabi.lp64d=march.rv64gc/mabi.lp64d --- -2.37.1.595.g718a3a8f04-goog - diff --git a/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum deleted file mode 100644 index a517ab9..0000000 --- a/util/crossgcc/sum/clang-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -581e929ba0d9fafc555081ab18d8c3fdf4478ac2 tarballs/clang-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/clang-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..e47ebce --- /dev/null +++ b/util/crossgcc/sum/clang-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +97d171d45738b07788864b79304d0128feca0596 tarballs/clang-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 6b9b67c..0000000 --- a/util/crossgcc/sum/clang-tools-extra-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -32923b812700526b76451384e4662ca45360d564 tarballs/clang-tools-extra-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/clang-tools-extra-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/clang-tools-extra-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..6ef2059 --- /dev/null +++ b/util/crossgcc/sum/clang-tools-extra-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +a445ba274276f3fa470ae765e774b2ed922d98e8 tarballs/clang-tools-extra-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum deleted file mode 100644 index d0e6331..0000000 --- a/util/crossgcc/sum/cmake-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -1ea03e355b705b4cada3051bd7301a57daa19283 tarballs/cmake-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/cmake-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/cmake-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..b6ada93 --- /dev/null +++ b/util/crossgcc/sum/cmake-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +7bf3c141bd5797ce6885b4b52c9dcab778c41e40 tarballs/cmake-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum deleted file mode 100644 index f3ddfba..0000000 --- a/util/crossgcc/sum/cmake-3.30.2.tar.gz.cksum +++ /dev/null @@ -1 +0,0 @@ -7cf72aa27d1a7791e035060031aebfdcf0a10e5a tarballs/cmake-3.30.2.tar.gz diff --git a/util/crossgcc/sum/cmake-3.31.2.tar.gz.cksum b/util/crossgcc/sum/cmake-3.31.2.tar.gz.cksum new file mode 100644 index 0000000..e3cb166 --- /dev/null +++ b/util/crossgcc/sum/cmake-3.31.2.tar.gz.cksum @@ -0,0 +1 @@ +b87bd9de209a60d7bc81b8fed594ea26adb4f716 tarballs/cmake-3.31.2.tar.gz diff --git a/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 711ef35..0000000 --- a/util/crossgcc/sum/compiler-rt-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -6ecbfa5516b60adb4e4e60f991b0d8ddf5aab12a tarballs/compiler-rt-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/compiler-rt-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/compiler-rt-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..ceccaa9 --- /dev/null +++ b/util/crossgcc/sum/compiler-rt-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +1caa4598ec1752afe537a63e797a9b0fb2819266 tarballs/compiler-rt-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum b/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum deleted file mode 100644 index f81c535..0000000 --- a/util/crossgcc/sum/gcc-14.2.0.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -d91ecc3d20ce6298bd95f9b09cc51dc6d3c73ae3 tarballs/gcc-14.2.0.tar.xz diff --git a/util/crossgcc/sum/gcc-15-20241208.tar.xz.cksum b/util/crossgcc/sum/gcc-15-20241208.tar.xz.cksum new file mode 100644 index 0000000..81a1d9a --- /dev/null +++ b/util/crossgcc/sum/gcc-15-20241208.tar.xz.cksum @@ -0,0 +1 @@ +c88dd85ec2dba7f51eed438ffceedf7aa20f3733 tarballs/gcc-15-20241208.tar.xz diff --git a/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum deleted file mode 100644 index d3819e3..0000000 --- a/util/crossgcc/sum/libunwind-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -5bee6cd2847f6d468861c78a21236e1c6fdc8374 tarballs/libunwind-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 490a835..0000000 --- a/util/crossgcc/sum/lld-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -1cf1fa9848b05a07d3d52e69949d44003f2ab2af tarballs/lld-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/lld-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/lld-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..7634bd5 --- /dev/null +++ b/util/crossgcc/sum/lld-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +10307ae0b5cab4fb8b9d2daf1a58230af7ee104b tarballs/lld-19.1.5.src.tar.xz diff --git a/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum b/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum deleted file mode 100644 index 4845fb5..0000000 --- a/util/crossgcc/sum/llvm-18.1.8.src.tar.xz.cksum +++ /dev/null @@ -1 +0,0 @@ -f9befa4cbef3f688ab48fca42449e13c5bcb872d tarballs/llvm-18.1.8.src.tar.xz diff --git a/util/crossgcc/sum/llvm-19.1.5.src.tar.xz.cksum b/util/crossgcc/sum/llvm-19.1.5.src.tar.xz.cksum new file mode 100644 index 0000000..2c90383 --- /dev/null +++ b/util/crossgcc/sum/llvm-19.1.5.src.tar.xz.cksum @@ -0,0 +1 @@ +11638313aa790f259ba8f18f83833d9b7a451f33 tarballs/llvm-19.1.5.src.tar.xz -- To view, visit https://review.coreboot.org/c/coreboot/+/85591?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ic325b9af34c113843d664c9b781b60177b6f4b32 Gerrit-Change-Number: 85591 Gerrit-PatchSet: 1 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr>

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[XS] Change in coreboot[main]: util/crossgcc: Update ACPICA from 20230628 to 20241212
by Elyes Haouas (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Felix Singer, Martin L Roth. Hello Felix Singer, Martin L Roth, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84787?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: util/crossgcc: Update ACPICA from 20230628 to 20241212 ...................................................................... util/crossgcc: Update ACPICA from 20230628 to 20241212 This to upgrade iasl from 20230628 to 20241212. Change-Id: I4ae7073e46084024360ac0dd44e0df666cb32269 Signed-off-by: Elyes Haouas <ehaouas(a)noos.fr> --- M util/crossgcc/buildgcc R util/crossgcc/patches/acpica-unix-20241212_iasl.patch D util/crossgcc/sum/acpica-unix-20230628.tar.gz.cksum A util/crossgcc/sum/acpica-unix-20241212.tar.gz.cksum 4 files changed, 3 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/84787/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/84787?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae7073e46084024360ac0dd44e0df666cb32269 Gerrit-Change-Number: 84787 Gerrit-PatchSet: 4 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>

1 0

[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Power management and external Settings
by Paul Menzel (Code Review) 14 Dec '24

14 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Kapil Porwal, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85578?usp=email ) Change subject: mb/trulo/var/uldrenite: Power management and external Settings ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85578/comment/7561b5db_26260da6?us… : PS2, Line 9: 1. Enable dptf : 2. Enable s0ix : 3. Configure external fivr setting Enumerating items is always a good indicator, that the commit should be split up in smaller pieces. -- To view, visit https://review.coreboot.org/c/coreboot/+/85578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id7777b7560b40c1427df9645d991240c027e58e4 Gerrit-Change-Number: 85578 Gerrit-PatchSet: 2 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Sat, 14 Dec 2024 08:48:02 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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