coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: drivers/wifi: Update Drive Strength BRI Rsp Table revision
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Jérémy Compostella. Subrata Banik has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85586?usp=email ) Change subject: drivers/wifi: Update Drive Strength BRI Rsp Table revision ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85586?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284 Gerrit-Change-Number: 85586 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 17:38:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/google/fatcat: Limit Power Limit when battery is missing
by Jérémy Compostella (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Jamie Ryu, Paul Menzel, Subrata Banik. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85146?usp=email ) Change subject: mb/google/fatcat: Limit Power Limit when battery is missing ...................................................................... Patch Set 17: (1 comment) Patchset: PS17: > > > As an alternative, could we filter out on the type of power supply ? […] I would like to of course as I do not enjoy having pending CLs. However, I would like to have a good understanding of the side effects. I am going to consult internally. I will keep you posted. -- To view, visit https://review.coreboot.org/c/coreboot/+/85146?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d71e9edde0ecbd7aaf316cd754a6ebcff9da77e Gerrit-Change-Number: 85146 Gerrit-PatchSet: 17 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Ryu <jamie.m.ryu(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Fri, 13 Dec 2024 17:38:01 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: cpu/x86/topology: Simplify CPU topology initialization
by Jérémy Compostella (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu. Hello Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85576?usp=email to look at the new patch set (#4). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: cpu/x86/topology: Simplify CPU topology initialization ...................................................................... cpu/x86/topology: Simplify CPU topology initialization This commit rewrites the CPU topology initialization code to simplify it and make it more maintainable. The previous code used a complex set of if-else statements to initialize the CPU topology based on the CPUID leaves that were supported. This has been replaced with a simpler and more readable function that follows the Intel Software Developer Manual recommendation by prioritizing CPUID EAX=0x1f over CPUID EAX=0xb if available. The new code removes the need for separate functions to handle the topology initialization for different CPUID leaves. It uses a static array of bitfield descriptors to store the APIC ID descriptor information for each level of the CPU topology. This simplifies the code and makes it easier to add new levels of topology in the future. The code populates the node ID based on the package ID, eliminating the need for an extra function call. Change-Id: Ie9424559f895af69e79c36b919e80af803861148 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/topology.c M src/include/cpu/x86/topology.h M src/soc/intel/xeon_sp/spr/cpu.c 4 files changed, 108 insertions(+), 123 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/85576/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9424559f895af69e79c36b919e80af803861148 Gerrit-Change-Number: 85576 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[XS] Change in coreboot[main]: drivers/wifi: Update Drive Strength BRI Rsp Table revision
by YH Lin (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Jérémy Compostella, Subrata Banik. YH Lin has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85586?usp=email ) Change subject: drivers/wifi: Update Drive Strength BRI Rsp Table revision ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85586?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284 Gerrit-Change-Number: 85586 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 17:29:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: device/pci_rom: add VFCT table for all AMD display devices
by Felix Held (Code Review) 13 Dec '24

13 Dec '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85587?usp=email ) Change subject: device/pci_rom: add VFCT table for all AMD display devices ...................................................................... device/pci_rom: add VFCT table for all AMD display devices Previously pci_rom_write_acpi_tables added a VFCT ACPI table for all AMD GPU PCI devices that have the PCI_CLASS_DISPLAY_VGA subclass. The iGPU PCI device in the AMD Glinda SoC however doesn't support the VGA compatibility mode any more and uses the PCI_CLASS_DISPLAY_OTHER subclass instead. So instead check if the PCI device uses the PCI_BASE_CLASS_DISPLAY class which covers both PCI_CLASS_DISPLAY_VGA and PCI_CLASS_DISPLAY_OTHER subclasses. Since the VFCT is only generated for PCI devices with the PCI_VID_ATI vendor ID, this doesn't affect any non-AMD PCI display output devices aka GPUs. There are additional changes around the ROM loading mechanism required to make the iGPU on AMD Glinda work, which will be done in follow-up commits. Change-Id: I1f3c7b899df772fd5b937f9bfd70f70412c4b8db Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/device/pci_rom.c 1 file changed, 2 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/87/85587/1 diff --git a/src/device/pci_rom.c b/src/device/pci_rom.c index d60720e..7d6e584 100644 --- a/src/device/pci_rom.c +++ b/src/device/pci_rom.c @@ -259,9 +259,8 @@ pci_rom_write_acpi_tables(const struct device *device, unsigned long current, struct acpi_rsdp *rsdp) { - /* Only handle VGA devices */ - if ((device->class >> 8) != PCI_CLASS_DISPLAY_VGA) - return current; + /* Only handle display devices */ + if ((device->class >> 16) != PCI_BASE_CLASS_DISPLAY) /* Only handle enabled devices */ if (!device->enabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/85587?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f3c7b899df772fd5b937f9bfd70f70412c4b8db Gerrit-Change-Number: 85587 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: drivers/wifi: Update Drive Strength BRI Rsp Table revision
by Jérémy Compostella (Code Review) 13 Dec '24

13 Dec '24

Jérémy Compostella has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85586?usp=email ) Change subject: drivers/wifi: Update Drive Strength BRI Rsp Table revision ...................................................................... drivers/wifi: Update Drive Strength BRI Rsp Table revision According to document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.2 and 9.2 specifications, both revision 0 and 1 are supported and share the same structure. BUG=b:346600091 Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h 2 files changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/86/85586/1 diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 4470553..7820987 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -985,7 +985,7 @@ * } } }) */ - if (dsbr->revision != DSBR_REVISION) { + if (dsbr->revision > DSBR_REVISION) { printk(BIOS_ERR, "Unsupported DSBR table revision: %d\n", dsbr->revision); return; diff --git a/src/include/sar.h b/src/include/sar.h index 94763b4..d8c0e05 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -21,7 +21,7 @@ #define BDMM_REVISION 1 #define EBRD_REVISION 1 #define WPFC_REVISION 0 -#define DSBR_REVISION 0 +#define DSBR_REVISION 1 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 #define SAR_REV0_SUBBANDS_COUNT 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85586?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284 Gerrit-Change-Number: 85586 Gerrit-PatchSet: 1 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Dinesh Gehlot, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Tim Crawford. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add function to force disable memory channels ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/743d0712_cdf55970?us… : PS1, Line 252: if (ch_disable_mask == 0) { > > > I think this CL is to provide an additional option to disable memory channels. Originally we could only use half_populated variable to turn off half of channels. > > > However, even with this CL to disable channels, users need still follow Intel PDG for proper usage. > > > We can skip checking these conditions because if config incorrect combinations, the FSP will return a "Memory initialization has failed" error. It's easy to identify. > > > > Partners can't readily understand the reason for the failure by looking at just the coreboot log. The log only says "FSP memoryinit error," and one would need to build FSP in debug mode to get more data. This data is often not readily available as part of CPFE AP FW build. I would still like to keep the minimal configuration, like not disabling MC0CH0. If such a design is seen, we should trigger an error before even calling into FSP.. > > I agree that FSP error codes are pretty much impossible to decipher without looking at its source code, so it would be nice to check that the settings are valid beforehand, in coreboot code. > > Thing is, we would need to know which configurations are valid and which ones aren't. Is there any documentation from Intel that specifies this? Maybe the PDG does (I currently don't have a PDG to check myself), at worst one could look at FSP source codes to see what exactly FSP/MRC considers valid. I guess this is subjected to the hardware design so, Intel platform doc should be helpful. To my understanding valid combinations are 1. MC0CH0 2. MC0CH0 and MC0CH1 I'm not sure if the upper channel can be disable while lower channels are in use. 3. MC0CH2 and MC0CH3 4. MC0CH2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 17:10:45 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels
by Angel Pons (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Dinesh Gehlot, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Tim Crawford. Angel Pons has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add function to force disable memory channels ...................................................................... Patch Set 6: (1 comment) File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/a9fc4673_2fba6fd5?us… : PS1, Line 252: if (ch_disable_mask == 0) { > > I think this CL is to provide an additional option to disable memory channels. Originally we could only use half_populated variable to turn off half of channels. > > However, even with this CL to disable channels, users need still follow Intel PDG for proper usage. > > We can skip checking these conditions because if config incorrect combinations, the FSP will return a "Memory initialization has failed" error. It's easy to identify. > > Partners can't readily understand the reason for the failure by looking at just the coreboot log. The log only says "FSP memoryinit error," and one would need to build FSP in debug mode to get more data. This data is often not readily available as part of CPFE AP FW build. I would still like to keep the minimal configuration, like not disabling MC0CH0. If such a design is seen, we should trigger an error before even calling into FSP.. I agree that FSP error codes are pretty much impossible to decipher without looking at its source code, so it would be nice to check that the settings are valid beforehand, in coreboot code. Thing is, we would need to know which configurations are valid and which ones aren't. Is there any documentation from Intel that specifies this? Maybe the PDG does (I currently don't have a PDG to check myself), at worst one could look at FSP source codes to see what exactly FSP/MRC considers valid. -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 17:00:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[XL] Change in coreboot[main]: drivers/option: Add forms in cbtables
by Angel Pons (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Benjamin Doron, Lean Sheng Tan, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Sean Rhodes. Angel Pons has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/74121?usp=email ) Change subject: drivers/option: Add forms in cbtables ...................................................................... Patch Set 24: (1 comment) File src/drivers/option/cfr.h: https://review.coreboot.org/c/coreboot/+/74121/comment/b56c6c24_526ad144?us… : PS22, Line 10: /* Front-end */ > Which part of this code should be split into another header? Any suggestion on the name? like cdr_fr […] All the `sm_` stuff (setup menu) is the ugly placeholder thing I made to be able to test CFR, i.e. the "frontend" (don't look at a gifted horse's mouth). Though now that I look at it again, the entire thing is now the "frontend". I would suggest renaming this header to `cfr_frontend.h` to make this clearer. -- To view, visit https://review.coreboot.org/c/coreboot/+/74121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 24 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 16:54:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com>

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[M] Change in coreboot[main]: cpu/x86/topology: Simplify CPU topology initialization
by Jérémy Compostella (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Ronak Kanabar, Shuo Liu, Tim Chu. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85576?usp=email ) Change subject: cpu/x86/topology: Simplify CPU topology initialization ...................................................................... Patch Set 2: (3 comments) Patchset: PS1: > LGTM. Will do a test on SPR and GNR to make sure no regression. I will waiting for your test results. File src/cpu/x86/topology.c: https://review.coreboot.org/c/coreboot/+/85576/comment/4a0b4d18_483bcba0?us… : PS1, Line 20: }; > Add a comment to specify to refer to Intel SDM for the level type definitions? I added a general comment to cover the entire file. https://review.coreboot.org/c/coreboot/+/85576/comment/caade511_8733737c?us… : PS1, Line 34: uint8_t nb_bits; > num_bits to be more straightforward? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9424559f895af69e79c36b919e80af803861148 Gerrit-Change-Number: 85576 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 16:48:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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