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Change subject: src/soc/intel/cmn/blk/cse: Log cse sync information
......................................................................
src/soc/intel/cmn/blk/cse: Log cse sync information
This patch adds an event log entry for successful CSE synchronization,
along with the boot stage where the synchronization occurred, either
early or late.
BUG=b:379585294
TEST=elog verified on rex0 and rex64
Rex0:
```
rex-rev3 ~ # /media/usb/elogtool list
3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync
```
Rex64:
```
rex64-rev3 ~ # /media/usb/elogtool list
8 | 2024-01-01 22:51:00-0800 | Firmware CSE sync | CSE Sync at Payload
```
Change-Id: Idece841c2b069d7688afc258470667ed2851a282
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/soc/intel/common/block/cse/cse_lite.c
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85219/2
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Dinesh Gehlot has uploaded a new patch set (#4) to the change originally created by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85111?usp=email )
The following approvals got outdated and were removed:
Code-Review+2 by Subrata Banik, Verified+1 by build bot (Jenkins)
Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place
......................................................................
soc/intel: Log CSE Sync Early Sign of Life event from a better place
CSE Sync Early Sign of Life (ESOL) event is logged as soon as the CSE FW
update is complete. This happens irrespective of whether Early Sign of
Life screen is enabled or not. Move CSE Sync ESOL event right before
displaying the ESOL screen.
BUG=b:378458829, b:379585294
TEST=Build Brox BIOS image and boot to OS. Ensure that the ESOL event
for CSE Sync is logged.
Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/soc/intel/alderlake/romstage/fsp_params.c
M src/soc/intel/alderlake/romstage/romstage.c
M src/soc/intel/common/block/cse/cse_lite.c
M src/soc/intel/meteorlake/romstage/fsp_params.c
4 files changed, 9 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/85111/4
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Change subject: util/cbfstool: Add eventLog support for ELOG_TYPE_FW_CSE_SYNC
......................................................................
util/cbfstool: Add eventLog support for ELOG_TYPE_FW_CSE_SYNC
This patch introduces logging for the ELOG_TYPE_FW_CSE_SYNC event. This
event logs data related to CSE synchronization, along with the relevant
boot stage information.
BUG=b:305898363
TEST=boot verified on google/rex0 and google/rex64
Change-Id: I4d6d3c4e07ab8677feb6a8acf8d4c6604ab704b8
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M util/cbfstool/eventlog.c
1 file changed, 15 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/18/85218/2
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Hello Kapil Porwal, Karthik Ramasubramanian, Subrata Banik, build bot (Jenkins),
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Change subject: commonlib: Add ELOG_TYPE_FW_CSE_SYNC eventLog type
......................................................................
commonlib: Add ELOG_TYPE_FW_CSE_SYNC eventLog type
This patch adds a new event log type, ELOG_TYPE_FW_CSE_SYNC. The
purpose of this event type is to log successful completion of CSE
synchronization.
BUG=b:379585294
TEST=boot verified on google/rex0 and google/rex64
Change-Id: Id73fa3a77e5fbbae5c61dfb30ae26b4ba3dca6ab
Signed-off-by: Dinesh Gehlot <digehlot(a)google.com>
---
M src/commonlib/bsd/include/commonlib/bsd/elog.h
1 file changed, 8 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/17/85217/2
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Change subject: soc/mediatek/mt8196: Add MMinfra driver support
......................................................................
Patch Set 23:
(5 comments)
File src/soc/mediatek/mt8196/bootblock.c:
https://review.coreboot.org/c/coreboot/+/85188/comment/4792f99c_c459adea?us… :
PS5, Line 19: mm_pre_init
> Why is this called `pre_init`? This only registers callbacks for 3 IDs. […]
Done
File src/soc/mediatek/mt8196/include/soc/mminfra.h:
https://review.coreboot.org/c/coreboot/+/85188/comment/67990d20_0d6b510f?us… :
PS5, Line 33: mm
> mminfra
Done
File src/soc/mediatek/mt8196/mminfra_pd.c:
PS5:
> If there's no other `mminfra_*.c` files, can we rename this to `mminfra. […]
Done
https://review.coreboot.org/c/coreboot/+/85188/comment/8d3e4e4a_295d76a2?us… :
PS5, Line 35: while (read32p(MMINFRA_MM0_GALS_PROT_TX_RDY) != 0xff)
: ;
> You can implement a common function and pass register address and expected value to that function. […]
Done
https://review.coreboot.org/c/coreboot/+/85188/comment/4c7e933b_7d20bf30?us… :
PS5, Line 66: static int pd_mm_infra_ao_pre_on(void)
: {
: return 0;
: }
:
: static int pd_mm_infra_ao_post_on(void)
: {
: return 0;
: }
:
: static int pd_mm_infra_ao_pre_off(void)
: {
: return 0;
: }
:
: static int pd_mm_infra_ao_post_off(void)
: {
: return 0;
: }
> Just remove if not used. `mtcmos_callback` will check if the callback is existed.
Done
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Change subject: soc/mediatek/mt8196: Add MMinfra driver support
......................................................................
soc/mediatek/mt8196: Add MMinfra driver support
MMinfra is the Multimedia Infrastructure. All the Multimedia modules
depend on it. This file adds some initial settings for MMinfra.
Test=Build pass
BUG=b:317009620
Signed-off-by: Xueqi Zhang <xueqi.zhang(a)mediatek.corp-partner.google.com>
Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75
---
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/bootblock.c
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/mminfra.h
A src/soc/mediatek/mt8196/mminfra.c
5 files changed, 166 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/85188/23
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Mark Chang has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email )
Change subject: Add support for MiTAC Computing Whitestone-2 mainboard
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h:
https://review.coreboot.org/c/coreboot/+/85532/comment/97529459_b61477ce?us… :
PS4, Line 98: IIO_BIFURCATE_xxxxxx16,
: IIO_BIFURCATE_xxx8xxx8,
: IIO_BIFURCATE_xxxxxx16,
: IIO_BIFURCATE_xxxxxx16,
: IIO_BIFURCATE_xxxxxx16,
> With the `CFG_UPD_PCIE_PORT_DISABLED` macro, it's easy to see how IIO bifurcation correlates to PCIe […]
Yes, it's a good idea to know the PCIe port settings.
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Change subject: mb/google/rauru: Implement regulator interface
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/rauru/regulator.c:
https://review.coreboot.org/c/coreboot/+/85563/comment/6c217a95_05a7b720?us… :
PS4, Line 26: if (id < 0) {
: printk(BIOS_ERR, "Invalid regulator ID: %d\n", regulator);
: return;
: }
> The logic was supposed to support the power rails from multiple PMICs. […]
Ack
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