coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Shuo Liu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Angel Pons, Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Mark Chang, Patrick Rudolph, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Wilson-MiTACComputing <wilson.chien(a)mitaccomputing.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 09:40:35 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Mac Chiang, Pranava Y N, Weimin Wu. Subrata Banik has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... Patch Set 2: (1 comment) File src/drivers/soundwire/alc711/alc711.c: https://review.coreboot.org/c/coreboot/+/85571/comment/64fe00e9_aed55513?us… : PS2, Line 13: static struct soundwire_multilane alc711_multilane = { : }; > Because I don't know how the default value should be configured, and if the chip config does not provide data, then because lane_mapping_count and lane_bus_holder_count are 0, no extra data will be generated, except that one more soundwire_gen_interface_revision(dsd) will be generated. To be honest, I am not sure whether it will cause interference, these need to be confirmed by actual debugging on the board. can Varun (Intel) able to share a response about how to handle the default data ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 08:46:56 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com>

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[S] Change in coreboot[main]: drivers/soundwire: Support Realtek ALC712 codec
by Weimin Wu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Mac Chiang, Pranava Y N. Weimin Wu has posted comments on this change by Weimin Wu. ( https://review.coreboot.org/c/coreboot/+/85571?usp=email ) Change subject: drivers/soundwire: Support Realtek ALC712 codec ...................................................................... Patch Set 2: (1 comment) File src/drivers/soundwire/alc711/alc711.c: https://review.coreboot.org/c/coreboot/+/85571/comment/b56d3c80_2420f8f0?us… : PS2, Line 13: static struct soundwire_multilane alc711_multilane = { : }; > do you wish to keep the default value for case when chip config hasn't been provided `config->multil […] Because I don't know how the default value should be configured, and if the chip config does not provide data, then because lane_mapping_count and lane_bus_holder_count are 0, no extra data will be generated, except that one more soundwire_gen_interface_revision(dsd) will be generated. To be honest, I am not sure whether it will cause interference, these need to be confirmed by actual debugging on the board. -- To view, visit https://review.coreboot.org/c/coreboot/+/85571?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib79896a9fe23f2f66d6ee3a24f5a62bfa0f7a649 Gerrit-Change-Number: 85571 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tongtong Pan <pantongtong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Varun Upadhyay <varun.upadhyay(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mac Chiang <mac.chiang(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 08:26:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: arch/x86: Add breakpoint to stack canary
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Patrick Rudolph. Subrata Banik has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84833?usp=email ) Change subject: arch/x86: Add breakpoint to stack canary ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: > Without further details I cannot fix this. > You didn't mention the platform, but looking at RIP it might be some AMD platform? > Can you figure out what code resides at RIP 0xf983007a or translate it to the romstage offset? That would allow to see which line caused the problem within the code. > > Looking at the AMD code I don't see the stack canary written as it was in https://review.coreboot.org/c/coreboot/+/85568 this issue seen now with all Intel platform that has `CONFIG_IDT_IN_EVERY_STAGE=y` enabled. The one that i have captured in from panther lake. -- To view, visit https://review.coreboot.org/c/coreboot/+/84833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8 Gerrit-Change-Number: 84833 Gerrit-PatchSet: 20 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-CC: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 07:57:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Disable stack overflow debug options
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N. Hello Kapil Porwal, Pranava Y N, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85584?usp=email to look at the new patch set (#3). Change subject: soc/intel/pantherlake: Disable stack overflow debug options ...................................................................... soc/intel/pantherlake: Disable stack overflow debug options This patch disables the `DEBUG_STACK_OVERFLOW_BREAKPOINTS` and `DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES` Kconfig options for the Pantherlake SOC. These options are causing false positive stack overflow detections, leading to unnecessary debugging. w/o this patch: stack corruption before for verstage and romstage early. Failed to create address zero instruction fetch breakpoint Failed to create stack canary breakpoint ... ... Stack corruption detected at rip: 0xf983007a Stack corruption detected at rip: 0xf983007a Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85584/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f Gerrit-Change-Number: 85584 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[M] Change in coreboot[main]: arch/x86: Add breakpoint to stack canary
by Patrick Rudolph (Code Review) 13 Dec '24

13 Dec '24

Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/84833?usp=email ) Change subject: arch/x86: Add breakpoint to stack canary ...................................................................... Patch Set 20: (1 comment) Patchset: PS20: > i'm seeing two errors which i believe false positive […] Without further details I cannot fix this. You didn't mention the platform, but looking at RIP it might be some AMD platform? Can you figure out what code resides at RIP 0xf983007a or translate it to the romstage offset? That would allow to see which line caused the problem within the code. Looking at the AMD code I don't see the stack canary written as it was in https://review.coreboot.org/c/coreboot/+/85568 -- To view, visit https://review.coreboot.org/c/coreboot/+/84833?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8adf07a8425856795a4a71da5c41bec2244b02a8 Gerrit-Change-Number: 84833 Gerrit-PatchSet: 20 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Andrey Petrov <andrey.petrov(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Jeremy Compostella <jeremy.compostella(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Jincheng Li <jincheng.li(a)intel.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-CC: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-CC: yuchi.chen(a)intel.com Gerrit-Comment-Date: Fri, 13 Dec 2024 07:53:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Disable stack overflow debug options
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N. Hello Kapil Porwal, Pranava Y N, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85584?usp=email to look at the new patch set (#2). Change subject: soc/intel/pantherlake: Disable stack overflow debug options ...................................................................... soc/intel/pantherlake: Disable stack overflow debug options This patch disables the `DEBUG_STACK_OVERFLOW_BREAKPOINTS` and `DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES` Kconfig options for the Pantherlake SOC. These options are causing false positive stack overflow detections, leading to unnecessary debugging. Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85584/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f Gerrit-Change-Number: 85584 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Disable stack overflow debug options
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85584?usp=email ) Change subject: soc/intel/pantherlake: Disable stack overflow debug options ...................................................................... soc/intel/pantherlake: Disable stack overflow debug options This patch disables the `DEBUG_STACK_OVERFLOW_BREAKPOINTS` and `DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES` Kconfig options for the Pantherlake SOC. These options are causing false positive stack overflow detections, leading to unnecessary debugging. Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f Signed-off-by: Subrata Banik <subratabanik(a)google.com> --- M src/soc/intel/pantherlake/Kconfig 1 file changed, 9 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/84/85584/1 diff --git a/src/soc/intel/pantherlake/Kconfig b/src/soc/intel/pantherlake/Kconfig index 26a4987..fec30ec 100644 --- a/src/soc/intel/pantherlake/Kconfig +++ b/src/soc/intel/pantherlake/Kconfig @@ -425,4 +425,13 @@ int default 38400000 +# Overrride DEBUG Kconfig to avoid false alarm about stack overflow. +config DEBUG_STACK_OVERFLOW_BREAKPOINTS + bool + default n + +config DEBUG_STACK_OVERFLOW_BREAKPOINTS_IN_ALL_STAGES + bool + default n + endif -- To view, visit https://review.coreboot.org/c/coreboot/+/85584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f Gerrit-Change-Number: 85584 Gerrit-PatchSet: 1 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>

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[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Dinesh Gehlot, Jamie Chen, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Tim Crawford. Subrata Banik has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add function to force disable memory channels ...................................................................... Patch Set 6: Code-Review+1 (2 comments) File src/soc/intel/alderlake/include/soc/meminit.h: https://review.coreboot.org/c/coreboot/+/85529/comment/69437ee3_74ca8609?us… : PS6, Line 120: mb_fill_override_channel_mask you need to write a API expectation in comment section for mb users to follow File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/da187434_e67c7ce8?us… : PS6, Line 269: { you don't need braces for single statement -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 06:57:10 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Configuration Network and Audio
by John Su (Code Review) 13 Dec '24

13 Dec '24

John Su has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85583?usp=email ) Change subject: mb/trulo/var/uldrenite: Configuration Network and Audio ...................................................................... mb/trulo/var/uldrenite: Configuration Network and Audio 1. Configuration WLAN, WWAN and audio 2. Enable WWAN driver 3. Enable HDA driver BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I2fd292550700817f15813dabfbaf9ccab3a907d8 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/uldrenite/Makefile.mk M src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h M src/mainboard/google/brya/variants/uldrenite/overridetree.cb 4 files changed, 63 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/85583/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index d76ec41..8a5bf5f 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -614,6 +614,10 @@ select BOARD_GOOGLE_BASEBOARD_TRULO select SOC_INTEL_TWINLAKE select SOC_INTEL_TCSS_USE_PDC_PMC_USBC_MUX_CONFIGURATION + select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select HAVE_PCIE_WWAN + select HAVE_WWAN_POWER_SEQUENCE + select DRIVERS_WWAN_FM350GL config BOARD_GOOGLE_VELL select BOARD_GOOGLE_BASEBOARD_BRYA diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk index 91f031e..c3c135b 100644 --- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk +++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk @@ -3,3 +3,5 @@ bootblock-y += gpio.c romstage-y += gpio.c ramstage-y += gpio.c + +ramstage-$(CONFIG_SOC_INTEL_COMMON_BLOCK_HDA_VERB) += hda_verb.c diff --git a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h index c4fe342..25edb0c 100644 --- a/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/uldrenite/include/variant/gpio.h @@ -5,4 +5,10 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_H23 +#define WWAN_RST GPP_F12 +#define WWAN_PERST GPP_H13 +#define T1_OFF_MS 20 +#define T2_OFF_MS 10 + #endif diff --git a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb index bc8850d..f71f659 100644 --- a/src/mainboard/google/brya/variants/uldrenite/overridetree.cb +++ b/src/mainboard/google/brya/variants/uldrenite/overridetree.cb @@ -9,6 +9,9 @@ register "tcc_offset" = "5" # TCC of 100 + # Enable CNVi BT + register "cnvi_bt_core" = "true" + # eMMC HS400 register "emmc_enable_hs400_mode" = "true" @@ -75,6 +78,13 @@ # Bit 1,3 - AUX lines are not swapped on the motherboard for either C0 or C1. register "tcss_aux_ori" = "0" + # HD Audio + register "pch_hda_dsp_enable" = "1" + register "pch_hda_audio_link_hda_enable" = "1" + register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" + register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" + register "pch_hda_idisp_codec_enable" = "1" + # Configure external V1P05/Vnn/VnnSx Rails register "ext_fivr_settings" = "{ .configure_ext_fivr = 1, @@ -290,6 +300,14 @@ end end device ref shared_sram on end + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + end device ref i2c0 on chip drivers/i2c/tpm register "hid" = ""GOOG0005"" @@ -395,6 +413,31 @@ device i2c 40 on end end #GTCH7502 end #I2C5 + device ref pcie_rp2 on + # Enable WWAN Card PCIE 2 using clk 2 + register "pch_pcie_rp[PCH_RP(2)]" = "{ + .clk_src = 2, + .clk_req = 2, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + chip soc/intel/common/block/pcie/rtd3 + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F13)" + register "reset_off_delay_ms" = "20" + register "srcclk_pin" = "2" + register "ext_pm_support" = "ACPI_PCIE_RP_EMIT_ALL" + register "skip_on_off_support" = "true" + device generic 0 alias rp2_rtd3 on end + end + chip drivers/wwan/fm + register "fcpo_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_H23)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F12)" + register "perst_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_F13)" + register "wake_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_E16)" + register "add_acpi_dma_property" = "true" + use rp2_rtd3 as rtd3dev + device generic 0 alias rp2_wwan on end + end + end #PCIE2 WWAN card device ref heci1 on end device ref emmc on end device ref uart0 on end @@ -404,5 +447,13 @@ end end device ref pmc hidden end + device ref hda on + chip drivers/sof + register "spkr_tplg" = "max98360a" + register "jack_tplg" = "rt5682" + register "mic_tplg" = "_2ch_pdm0" + device generic 0 on end + end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85583?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2fd292550700817f15813dabfbaf9ccab3a907d8 Gerrit-Change-Number: 85583 Gerrit-PatchSet: 1 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com>

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coreboot-gerrit December 2024