coreboot-gerrit December 2024

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Use \_SB.POSC on all platforms
by Shuo Liu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85559?usp=email ) Change subject: soc/intel/xeon_sp: Use \_SB.POSC on all platforms ...................................................................... Patch Set 5: (1 comment) File src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl: https://review.coreboot.org/c/coreboot/+/85559/comment/6137149f_8a427a4e?us… : PS5, Line 41: Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x15, 1, 1)) Maybe marcos here (e.g., for the 0x15)? -- To view, visit https://review.coreboot.org/c/coreboot/+/85559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c Gerrit-Change-Number: 85559 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 04:50:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Use \_SB.POSC on all platforms
by Shuo Liu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85559?usp=email ) Change subject: soc/intel/xeon_sp: Use \_SB.POSC on all platforms ...................................................................... Patch Set 5: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85559?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f25ffbde9b83d286c568202fcffb75ffb07286c Gerrit-Change-Number: 85559 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 04:49:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/xeon_sp: Allow OS to control LTR and AER
by Shuo Liu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85561?usp=email ) Change subject: soc/intel/xeon_sp: Allow OS to control LTR and AER ...................................................................... Patch Set 5: Code-Review+1 (1 comment) File src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl: https://review.coreboot.org/c/coreboot/+/85561/comment/9cd76985_8961961d?us… : PS5, Line 41: Return (\_SB.POSC(Arg0, Arg1, Arg2, Arg3, 0x3d, 1, 1)) Possible to have some macros to represent the value? -- To view, visit https://review.coreboot.org/c/coreboot/+/85561?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c4176a4df898cee28f6319c6684763e825d9c46 Gerrit-Change-Number: 85561 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 04:48:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/intel/xeon_sp/spr/acpi: Fix regression
by Shuo Liu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85562?usp=email ) Change subject: soc/intel/xeon_sp/spr/acpi: Fix regression ...................................................................... Patch Set 3: Code-Review+2 (1 comment) File src/soc/intel/xeon_sp/spr/acpi/uncore.asl: https://review.coreboot.org/c/coreboot/+/85562/comment/70a9b57b_e258ecd1?us… : PS3, Line 15: #define SOCKET_NAME 0 Maybe mention SOCKET_NAME = SOCKET << 1? -- To view, visit https://review.coreboot.org/c/coreboot/+/85562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658 Gerrit-Change-Number: 85562 Gerrit-PatchSet: 3 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 04:47:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6373 driver
by Yu-Ping Wu (Code Review) 13 Dec '24

13 Dec '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85129?usp=email ) ( 37 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/mediatek/mt8196: Add PMIC MT6373 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6373 driver 1. Add MT6373 driver in soc folder 2 Add regulator API for powering on SD card 3. Add regulator API for VCN33_3 4. Add MT6373 LDO enable API TEST=build pass, check boot log with: [INFO ] mt6373_init_setting done [INFO ] pmic_protect_key_setting done BUG=b:317009620 Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85129 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- A src/soc/mediatek/common/include/soc/mt6373.h A src/soc/mediatek/common/mt6373.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6373.c 4 files changed, 711 insertions(+), 0 deletions(-) Approvals: Yidi Lin: Looks good to me, approved build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/soc/mediatek/common/include/soc/mt6373.h b/src/soc/mediatek/common/include/soc/mt6373.h new file mode 100644 index 0000000..ae25b19 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mt6373.h @@ -0,0 +1,79 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6373_H__ +#define __SOC_MEDIATEK_MT6373_H__ + +#include <soc/spmi.h> +#include <types.h> + +enum { + MT6373_SWCID0 = 0xA, + MT6373_SWCID1 = 0xB, + MT6373_TOP_VRCTL_VOSEL_VBUCK0 = 0x24C, + MT6373_TOP_VRCTL_VOSEL_VBUCK1 = 0x24D, + MT6373_TOP_VRCTL_VOSEL_VBUCK2 = 0x24E, + MT6373_BUCK_TOP_4PHASE_1_ANA_CON42 = 0x1A32, + MT6373_BUCK_TOP_KEY_PROT_LO = 0x142A, + MT6373_BUCK_TOP_KEY_PROT_HI = 0x142B, + MT6373_BUCK_VBUCK0_DBG0 = 0x1496, + MT6373_BUCK_VBUCK1_DBG0 = 0x1516, + MT6373_BUCK_VBUCK2_DBG0 = 0x1596, + MT6373_LDO_VCN33_3_CON0 = 0x1C23, + MT6373_LDO_VCN33_3_CON1 = 0x1C24, + MT6373_LDO_VANT18_CON0 = 0x1C87, + MT6373_LDO_VANT18_CON1 = 0x1C88, + MT6373_LDO_VMCH_CON0 = 0x1CB1, + MT6373_LDO_VMC_CON0 = 0x1CC0, + MT6373_LDO_VSIM1_CON0 = 0x1D31, + MT6373_LDO_VSIM1_CON1 = 0x1D32, + MT6373_LDO_VSIM2_CON0 = 0x1D40, + MT6373_LDO_VSIM2_CON1 = 0x1D41, + MT6373_VCN33_3_ANA_CON0 = 0x1E18, + MT6373_VCN33_3_ANA_CON1 = 0x1E19, + MT6373_VMCH_ANA_CON0 = 0x1E1C, + MT6373_VMCH_ANA_CON1 = 0x1E1D, + MT6373_VMC_ANA_CON0 = 0x1E24, + MT6373_VMC_ANA_CON1 = 0x1E25, +}; + +struct mt6373_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +struct mt6373_efuse { + unsigned short efuse_bit; + unsigned short addr; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6373_VBUCK0 = 0, + MT6373_VBUCK1, + MT6373_VBUCK2, + MT6373_VMC, + MT6373_VMCH, + MT6373_MAX, +}; + +void mt6373_init(void); +void mt6373_set_vmc_voltage(u32 vmc_uv); +u32 mt6373_get_vmc_voltage(void); +void mt6373_set_vmch_voltage(u32 vmch_uv); +u32 mt6373_get_vmch_voltage(void); +void mt6373_set_vcn33_3_voltage(u32 vcn33_3_uv); +void mt6373_enable_vcn33_3(bool enable); +void mt6373_enable_vmc(bool enable); +void mt6373_enable_vmch(bool enable); +void mt6373_enable_vant18(bool enable); +void mt6373_enable_vsim1(bool enable); +void mt6373_enable_vsim2(bool enable); +void mt6373_init_pmif_arb(void); +void mt6373_write_field(u32 reg, u32 val, u32 mask, u32 shift); +void mt6373_init_setting(void); +void mt6373_lp_setting(void); + +#endif /* __SOC_MEDIATEK_MT6373_H__ */ diff --git a/src/soc/mediatek/common/mt6373.c b/src/soc/mediatek/common/mt6373.c new file mode 100644 index 0000000..1d5e1e2 --- /dev/null +++ b/src/soc/mediatek/common/mt6373.c @@ -0,0 +1,264 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6373.h> +#include <soc/pmif.h> +#include <timer.h> + +static const struct mt6373_setting key_protect_setting[] = { + {0x39E, 0x8C, 0xFF, 0}, + {0x39F, 0x9C, 0xFF, 0}, + {0xFAB, 0x73, 0xFF, 0}, + {0xFAC, 0x63, 0xFF, 0}, + {0x142A, 0x43, 0xFF, 0}, + {0x142B, 0x55, 0xFF, 0}, + {0x3A7, 0x8C, 0xFF, 0}, + {0x3A8, 0x9C, 0xFF, 0}, + {0xA1A, 0x29, 0xFF, 0}, + {0xA1B, 0x47, 0xFF, 0}, +}; + +static struct pmif *pmif_arb; +static void mt6373_write8(u32 reg, u8 data) +{ + assert(pmif_arb); + pmif_arb->write(pmif_arb, SPMI_SLAVE_5, reg, data); +} + +static u32 mt6373_read_field(u32 reg, u32 mask, u32 shift) +{ + assert(pmif_arb); + return pmif_arb->read_field(pmif_arb, SPMI_SLAVE_5, reg, mask, shift); +} + +void mt6373_write_field(u32 reg, u32 val, u32 mask, u32 shift) +{ + assert(pmif_arb); + pmif_arb->write_field(pmif_arb, SPMI_SLAVE_5, reg, val, mask, shift); +} + +static void pmic_protect_key_setting(bool lock) +{ + for (int i = 0; i < ARRAY_SIZE(key_protect_setting); i++) + mt6373_write8(key_protect_setting[i].addr, + lock ? 0 : key_protect_setting[i].val); + printk(BIOS_INFO, "%s done\n", __func__); +} + +void mt6373_set_vmc_voltage(u32 vmc_uv) +{ + u32 reg_vol, reg_cali; + + assert(pmif_arb); + + if (vmc_uv >= 1200000 && vmc_uv <= 1300000) + reg_vol = (vmc_uv - 1200000) / 100000; + else if (vmc_uv >= 1500000 && vmc_uv <= 1700000) + reg_vol = (vmc_uv - 1500000) / 200000 + 2; + else if (vmc_uv >= 1800000 && vmc_uv <= 2000000) + reg_vol = (vmc_uv - 1800000) / 200000 + 4; + else if (vmc_uv >= 2100000 && vmc_uv <= 2200000) + reg_vol = (vmc_uv - 2100000) / 100000 + 6; + else if (vmc_uv >= 2700000 && vmc_uv <= 3100000) + reg_vol = (vmc_uv - 2700000) / 100000 + 8; + else if (vmc_uv >= 3300000 && vmc_uv <= 3500000) + reg_vol = (vmc_uv - 3300000) / 100000 + 13; + else + die("ERROR: Unknown vmc voltage %u", vmc_uv); + + reg_cali = ((vmc_uv / 1000) % 100) / 10; + + mt6373_write8(MT6373_VMC_ANA_CON1, reg_vol); + mt6373_write8(MT6373_VMC_ANA_CON0, reg_cali); + + printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vmc_uv); +} + +u32 mt6373_get_vmc_voltage(void) +{ + u32 reg_vol, reg_cali, vol; + + assert(pmif_arb); + + reg_vol = mt6373_read_field(MT6373_VMC_ANA_CON1, 0xF, 0); + reg_cali = mt6373_read_field(MT6373_VMC_ANA_CON0, 0xF, 0); + + if (reg_vol == 0 || reg_vol == 1) + vol = (reg_vol - 0) * 100000 + 1200000; + else if (reg_vol == 2 || reg_vol == 3) + vol = (reg_vol - 2) * 200000 + 1500000; + else if (reg_vol == 4 || reg_vol == 5) + vol = (reg_vol - 4) * 200000 + 1800000; + else if (reg_vol == 6 || reg_vol == 7) + vol = (reg_vol - 6) * 100000 + 2100000; + else if (reg_vol >= 8 && reg_vol <= 12) + vol = (reg_vol - 8) * 100000 + 2700000; + else if (reg_vol >= 13 && reg_vol <= 15) + vol = (reg_vol - 13) * 100000 + 3300000; + else + die("ERROR: Unknown vsim1 reg_vol %x", reg_vol); + + printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, vol %d, %d\n", + __func__, reg_vol, reg_cali, vol, (vol + reg_cali * 1000)); + + return (vol + reg_cali * 1000); +} + +void mt6373_set_vmch_voltage(u32 vmch_uv) +{ + u32 reg_vol, reg_cali; + + assert(pmif_arb); + + if (vmch_uv >= 1200000 && vmch_uv <= 1300000) + reg_vol = (vmch_uv - 1200000) / 100000; + else if (vmch_uv >= 1500000 && vmch_uv <= 1700000) + reg_vol = (vmch_uv - 1500000) / 200000 + 2; + else if (vmch_uv >= 1800000 && vmch_uv <= 2000000) + reg_vol = (vmch_uv - 1800000) / 200000 + 4; + else if (vmch_uv >= 2500000 && vmch_uv <= 3100000) + reg_vol = (vmch_uv - 2500000) / 100000 + 6; + else if (vmch_uv >= 3300000 && vmch_uv <= 3500000) + reg_vol = (vmch_uv - 3300000) / 100000 + 13; + else + die("ERROR: Unknown vmc voltage %u", vmch_uv); + + reg_cali = ((vmch_uv / 1000) % 100) / 10; + + mt6373_write8(MT6373_VMCH_ANA_CON1, reg_vol); + mt6373_write8(MT6373_VMCH_ANA_CON0, reg_cali); + + printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vmch_uv); +} + +u32 mt6373_get_vmch_voltage(void) +{ + u32 reg_vol, reg_cali, vol; + + assert(pmif_arb); + + reg_vol = mt6373_read_field(MT6373_VMCH_ANA_CON1, 0xF, 0); + reg_cali = mt6373_read_field(MT6373_VMCH_ANA_CON0, 0xF, 0); + + if (reg_vol == 0 || reg_vol == 1) + vol = (reg_vol - 0) * 100000 + 1200000; + else if (reg_vol == 2 || reg_vol == 3) + vol = (reg_vol - 2) * 200000 + 1500000; + else if (reg_vol == 4 || reg_vol == 5) + vol = (reg_vol - 4) * 200000 + 1800000; + else if (reg_vol >= 6 && reg_vol <= 12) + vol = (reg_vol - 6) * 100000 + 2500000; + else if (reg_vol >= 13 && reg_vol <= 15) + vol = (reg_vol - 13) * 100000 + 3300000; + else + die("ERROR: Unknown vsim1 reg_vol %x", reg_vol); + + printk(BIOS_INFO, "%s: reg_vol 0x%x, reg_cali 0x%x, vol %d, %d\n", + __func__, reg_vol, reg_cali, vol, (vol + reg_cali * 1000)); + + return (vol + reg_cali * 1000); +} + +void mt6373_set_vcn33_3_voltage(u32 vcn33_3_uv) +{ + udelay(100); + printk(BIOS_INFO, "%s start\n", __func__); + u32 reg_vol, reg_cali; + + assert(pmif_arb); + + if (vcn33_3_uv >= 1200000 && vcn33_3_uv <= 1300000) + reg_vol = (vcn33_3_uv - 1200000) / 100000; + else if (vcn33_3_uv >= 1500000 && vcn33_3_uv <= 1700000) + reg_vol = (vcn33_3_uv - 1500000) / 200000 + 2; + else if (vcn33_3_uv >= 1800000 && vcn33_3_uv <= 2000000) + reg_vol = (vcn33_3_uv - 1800000) / 200000 + 4; + else if (vcn33_3_uv >= 2500000 && vcn33_3_uv <= 3100000) + reg_vol = (vcn33_3_uv - 2500000) / 100000 + 6; + else if (vcn33_3_uv >= 3300000 && vcn33_3_uv <= 3500000) + reg_vol = (vcn33_3_uv - 3300000) / 100000 + 13; + else + die("ERROR: Unknown vcn33_3_uv voltage %u", vcn33_3_uv); + + reg_cali = ((vcn33_3_uv / 1000) % 100) / 10; + + mt6373_write8(MT6373_VCN33_3_ANA_CON1, reg_vol); + udelay(100); + mt6373_write8(MT6373_VCN33_3_ANA_CON0, reg_cali); + udelay(100); + printk(BIOS_INFO, "%s: 0x%x, %d\n", __func__, reg_vol, vcn33_3_uv); +} + +void mt6373_enable_vcn33_3(bool enable) +{ + mt6373_write_field(MT6373_LDO_VCN33_3_CON0, enable, 0x1, 0); +} + +void mt6373_enable_vmc(bool enable) +{ + mt6373_write_field(MT6373_LDO_VMC_CON0, enable, 0x1, 0); +} + +void mt6373_enable_vmch(bool enable) +{ + mt6373_write_field(MT6373_LDO_VMCH_CON0, enable, 0x1, 0); +} + +void mt6373_enable_vant18(bool enable) +{ + mt6373_write_field(MT6373_LDO_VANT18_CON0, enable, 0x1, 0); +} + +void mt6373_enable_vsim1(bool enable) +{ + mt6373_write_field(MT6373_LDO_VSIM1_CON0, enable, 0x1, 0); +} + +void mt6373_enable_vsim2(bool enable) +{ + mt6373_write_field(MT6373_LDO_VSIM2_CON0, enable, 0x1, 0); +} + +static void mt6373_pmic_wdt_set(void) +{ + /* [5]=1, RG_WDTRSTB_DEB */ + mt6373_write_field(0x13a, 0x20, 0xFF, 0); + /* [1]=0, RG_WDTRSTB_MODE */ + mt6373_write_field(0x13b, 0x02, 0xFF, 0); + /* [0]=1, RG_WDTRSTB_EN */ + mt6373_write_field(0x13a, 0x01, 0xFF, 0); + /* Enable BUCK/LDO WDT VOSEL Debug */ + mt6373_write_field(0x231, 0x1, 0x1, 0); + /* Clear WDT status */ + mt6373_write_field(0x13a, 0x1, 0x1, 3); + udelay(50); + mt6373_write_field(0x13b, 0x1, 0x1, 3); + printk(BIOS_INFO, "[%s]WDTRSTB[0x139]=0x%x\n", __func__, + mt6373_read_field(0x139, 0xFF, 0)); +} + +void mt6373_init_pmif_arb(void) +{ + if (!pmif_arb) { + pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_1); + assert(pmif_arb); + } + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("%s: initialization failed", __func__); + + printk(BIOS_INFO, "[%s][MT6373]CHIP ID = 0x%x\n", + __func__, mt6373_read_field(MT6373_SWCID1, 0xFF, 0)); +} + +void mt6373_init(void) +{ + printk(BIOS_INFO, "%s start\n", __func__); + mt6373_init_pmif_arb(); + mt6373_pmic_wdt_set(); + pmic_protect_key_setting(false); + mt6373_init_setting(); + pmic_protect_key_setting(true); +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index f48f380..9652a1e 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -31,6 +31,7 @@ romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c romstage-y += ../common/mt6363.c mt6363.c +romstage-y += ../common/mt6373.c mt6373.c romstage-y += ../common/pmif_clk.c pmif_clk.c romstage-y += ../common/pmif.c pmif_init.c romstage-y += pmif_spmi.c @@ -46,6 +47,7 @@ ramstage-$(CONFIG_PCI) += ../common/pcie.c pcie.c ramstage-y += ../common/mt6363.c mt6363.c ramstage-y += ../common/mt6363_sdmadc.c +ramstage-y += ../common/mt6373.c mt6373.c ramstage-y += soc.c ramstage-y += ../common/sspm.c sspm_sram.c ramstage-y += ../common/pmif_clk.c pmif_clk.c diff --git a/src/soc/mediatek/mt8196/mt6373.c b/src/soc/mediatek/mt8196/mt6373.c new file mode 100644 index 0000000..12c7900 --- /dev/null +++ b/src/soc/mediatek/mt8196/mt6373.c @@ -0,0 +1,366 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * These values are used by MediaTek internally. + * We can find these registers in "MT6373TP_PMIC_Design_Notice_for_MT8196G_V0.2". + * The setting values are provided by MeidaTek designers. + */ + +#include <soc/mt6373.h> +#include <console/console.h> + +static const struct mt6373_setting init_setting[] = { + /* For VIO18 switch to DIG18 feature */ + {0xA95, 0x1, 0x1, 7}, + {0x16, 0xA, 0xA, 0}, + {0x19, 0x1F, 0x1F, 0}, + {0x21, 0x1, 0x1, 0}, + {0x22, 0x61, 0x61, 0}, + {0x4C, 0x0, 0xFF, 0}, + {0x4F, 0x0, 0x80, 0}, + {0x5A, 0x5, 0x5, 0}, + {0x91, 0x93, 0xFF, 0}, + {0x94, 0xFF, 0xFF, 0}, + {0x97, 0xF, 0xFF, 0}, + {0xC4, 0x0, 0x38, 0}, + {0xC7, 0x0, 0x3F, 0}, + {0xCA, 0x0, 0x3F, 0}, + {0xCD, 0x0, 0x3F, 0}, + {0xD0, 0x0, 0x3F, 0}, + {0xD3, 0x0, 0x3F, 0}, + {0xD6, 0x0, 0x3F, 0}, + {0x10F, 0x10, 0x10, 0}, + {0x112, 0x4, 0x4, 0}, + {0x12D, 0x1, 0x1, 0}, + {0x139, 0x21, 0x21, 0}, + {0x230, 0x0, 0x1, 0}, + {0x3A6, 0x3, 0x3, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x90D, 0x10, 0x10, 0}, + {0xA17, 0xFF, 0xFF, 0}, + {0xA18, 0xFF, 0xFF, 0}, + {0xA19, 0xFC, 0xFC, 0}, + {0xA1D, 0xE, 0xFF, 0}, + {0xA1E, 0x7, 0xFF, 0}, + {0xA1F, 0x0, 0xFF, 0}, + {0xA20, 0xFF, 0xFF, 0}, + {0xA21, 0xE, 0xFF, 0}, + {0xA22, 0xFF, 0xFF, 0}, + {0xA23, 0xFF, 0xFF, 0}, + {0xA24, 0xC, 0xFF, 0}, + {0xA25, 0xB, 0xFF, 0}, + {0xA26, 0xA, 0xFF, 0}, + {0xA27, 0x7, 0xFF, 0}, + {0xA28, 0x7, 0xFF, 0}, + {0xA29, 0x7, 0xFF, 0}, + {0xA2A, 0x5, 0xFF, 0}, + {0xA2B, 0xFF, 0xFF, 0}, + {0xA2C, 0xFF, 0xFF, 0}, + {0xA2D, 0xFF, 0xFF, 0}, + {0xA2E, 0xFF, 0xFF, 0}, + {0xA2F, 0xFF, 0xFF, 0}, + {0xA30, 0xFF, 0xFF, 0}, + {0xA31, 0xFF, 0xFF, 0}, + {0xA32, 0xFF, 0xFF, 0}, + {0xA33, 0xFF, 0xFF, 0}, + {0xF8C, 0x15, 0x15, 0}, + {0xF8D, 0x25, 0x25, 0}, + {0x1188, 0x0, 0x80, 0}, + {0x1190, 0x13, 0xFF, 0}, + {0x119B, 0x20, 0xFF, 0}, + {0x119D, 0x60, 0x70, 0}, + {0x11A0, 0x60, 0x70, 0}, + {0x11C6, 0xF, 0xF, 0}, + {0x11C7, 0x0, 0xF, 0}, + {0x140E, 0x0, 0x40, 0}, + {0x144A, 0x0, 0xFF, 0}, + {0x144B, 0x0, 0xFF, 0}, + {0x144C, 0x0, 0xF, 0}, + {0x1487, 0x40, 0xFF, 0}, + {0x1488, 0x0, 0x1, 0}, + {0x148A, 0x5, 0x7F, 0}, + {0x1507, 0x40, 0xFF, 0}, + {0x1508, 0x0, 0x1, 0}, + {0x150A, 0x5, 0x7F, 0}, + {0x1587, 0x40, 0xFF, 0}, + {0x1588, 0x0, 0x1, 0}, + {0x158A, 0x5, 0x7F, 0}, + {0x1607, 0x40, 0xFF, 0}, + {0x1608, 0x0, 0x1, 0}, + {0x160A, 0x5, 0x7F, 0}, + {0x1687, 0x40, 0xFF, 0}, + {0x1688, 0x0, 0x1, 0}, + {0x168B, 0xC, 0x7F, 0}, + {0x1707, 0x40, 0xFF, 0}, + {0x1708, 0x0, 0x1, 0}, + {0x170B, 0xC, 0x7F, 0}, + {0x1787, 0x92, 0xFF, 0}, + {0x1788, 0x0, 0x1, 0}, + {0x1807, 0x40, 0xFF, 0}, + {0x1808, 0x0, 0x1, 0}, + {0x180A, 0x5, 0x7F, 0}, + {0x1887, 0x6C, 0xFF, 0}, + {0x1888, 0x0, 0x1, 0}, + {0x188A, 0x19, 0x7F, 0}, + {0x188B, 0x33, 0x7F, 0}, + {0x1907, 0x98, 0xFF, 0}, + {0x1908, 0x0, 0x1, 0}, + {0x190A, 0x19, 0x7F, 0}, + {0x190B, 0x33, 0x7F, 0}, + {0x198A, 0x2E, 0x2F, 0}, + {0x198C, 0xF8, 0xF8, 0}, + {0x198D, 0x32, 0x3F, 0}, + {0x198F, 0xC, 0xC, 0}, + {0x1990, 0xED, 0xFF, 0}, + {0x1991, 0x10, 0xFF, 0}, + {0x1994, 0x2E, 0x2F, 0}, + {0x1996, 0xF8, 0xF8, 0}, + {0x1997, 0x32, 0x3F, 0}, + {0x1999, 0xC, 0xC, 0}, + {0x199A, 0xED, 0xFF, 0}, + {0x199B, 0x10, 0xFF, 0}, + {0x19A0, 0xF, 0xF, 0}, + {0x19A1, 0x45, 0xFF, 0}, + {0x19A2, 0x45, 0xFF, 0}, + {0x19A3, 0xC, 0xC, 0}, + {0x19B5, 0x5, 0x87, 0}, + {0x19BD, 0x85, 0x87, 0}, + {0x19C0, 0x0, 0x18, 0}, + {0x1A08, 0x10, 0x10, 0}, + {0x1A09, 0x2D, 0x2F, 0}, + {0x1A0A, 0xC1, 0xC1, 0}, + {0x1A0B, 0xFA, 0xFF, 0}, + {0x1A0C, 0x32, 0x3F, 0}, + {0x1A0E, 0xC, 0xC, 0}, + {0x1A0F, 0x77, 0xFF, 0}, + {0x1A10, 0xC0, 0xFF, 0}, + {0x1A11, 0x6B, 0x7F, 0}, + {0x1A12, 0x10, 0x10, 0}, + {0x1A13, 0x2D, 0x2F, 0}, + {0x1A14, 0xC1, 0xC1, 0}, + {0x1A15, 0xFA, 0xFF, 0}, + {0x1A16, 0x32, 0x3F, 0}, + {0x1A18, 0xC, 0xC, 0}, + {0x1A19, 0x77, 0xFF, 0}, + {0x1A1A, 0xC0, 0xFF, 0}, + {0x1A1B, 0x6B, 0x7F, 0}, + {0x1A1C, 0x10, 0x10, 0}, + {0x1A1D, 0x2D, 0x2F, 0}, + {0x1A1E, 0xC1, 0xC1, 0}, + {0x1A1F, 0xFA, 0xFF, 0}, + {0x1A20, 0x32, 0x3F, 0}, + {0x1A22, 0xC, 0xC, 0}, + {0x1A23, 0x77, 0xFF, 0}, + {0x1A24, 0xC0, 0xFF, 0}, + {0x1A25, 0x6B, 0x7F, 0}, + {0x1A26, 0x10, 0x10, 0}, + {0x1A27, 0x2D, 0x2F, 0}, + {0x1A28, 0xC1, 0xC1, 0}, + {0x1A29, 0xFA, 0xFF, 0}, + {0x1A2A, 0x32, 0x3F, 0}, + {0x1A2C, 0xC, 0xC, 0}, + {0x1A2D, 0x77, 0xFF, 0}, + {0x1A2E, 0xC0, 0xFF, 0}, + {0x1A2F, 0x6B, 0x7F, 0}, + {0x1A37, 0xFF, 0xFF, 0}, + {0x1A39, 0x5F, 0xFF, 0}, + {0x1A3A, 0x5F, 0xFF, 0}, + {0x1A3B, 0x5F, 0xFF, 0}, + {0x1A3C, 0x5F, 0xFF, 0}, + {0x1A3D, 0xF0, 0xF0, 0}, + {0x1A46, 0x6, 0x87, 0}, + {0x1A4E, 0x6, 0x87, 0}, + {0x1A56, 0x6, 0x87, 0}, + {0x1A5E, 0x6, 0x87, 0}, + {0x1A61, 0x0, 0x78, 0}, + {0x1A88, 0x10, 0x50, 0}, + {0x1A89, 0x2D, 0x2F, 0}, + {0x1A8B, 0xF8, 0xF8, 0}, + {0x1A8C, 0x32, 0x3F, 0}, + {0x1A8E, 0xC, 0xC, 0}, + {0x1A8F, 0xED, 0xFF, 0}, + {0x1A90, 0x0, 0xFF, 0}, + {0x1A92, 0x10, 0x10, 0}, + {0x1A93, 0x2D, 0x2F, 0}, + {0x1A95, 0xF8, 0xF8, 0}, + {0x1A96, 0x32, 0x3F, 0}, + {0x1A98, 0xC, 0xC, 0}, + {0x1A99, 0xED, 0xFF, 0}, + {0x1A9C, 0x10, 0x16, 0}, + {0x1A9D, 0x2D, 0x2F, 0}, + {0x1A9F, 0xF8, 0xF8, 0}, + {0x1AA0, 0x32, 0x3F, 0}, + {0x1AA2, 0xC, 0xC, 0}, + {0x1AA3, 0xED, 0xFF, 0}, + {0x1AA4, 0x0, 0xFF, 0}, + {0x1AA6, 0x10, 0x56, 0}, + {0x1AA7, 0x2D, 0x2F, 0}, + {0x1AA9, 0xF8, 0xF8, 0}, + {0x1AAA, 0x32, 0x3F, 0}, + {0x1AAC, 0xC, 0xC, 0}, + {0x1AAD, 0xED, 0xFF, 0}, + {0x1AB6, 0x20, 0x30, 0}, + {0x1AB7, 0xF0, 0xF0, 0}, + {0x1AB9, 0xCD, 0xFF, 0}, + {0x1ABA, 0xCD, 0xFF, 0}, + {0x1ABB, 0xE5, 0xFF, 0}, + {0x1ABC, 0xCD, 0xFF, 0}, + {0x1ABD, 0xF0, 0xF0, 0}, + {0x1AC6, 0x6, 0x87, 0}, + {0x1ACE, 0x86, 0x87, 0}, + {0x1AD6, 0x6, 0x87, 0}, + {0x1ADE, 0x6, 0x87, 0}, + {0x1AE1, 0x28, 0x78, 0}, + {0x1B0D, 0xF, 0xF, 0}, + {0x1B0E, 0x1, 0x1, 0}, + {0x1B10, 0xFF, 0xFF, 0}, + {0x1B13, 0xFF, 0xFF, 0}, + {0x1B16, 0xFF, 0xFF, 0}, + {0x1B2A, 0x8, 0x8, 0}, + {0x1B88, 0x10, 0x10, 0}, + {0x1B89, 0x0, 0x80, 0}, + {0x1B96, 0x10, 0x10, 0}, + {0x1B97, 0x0, 0x80, 0}, + {0x1BA4, 0x10, 0x10, 0}, + {0x1BA5, 0x0, 0x80, 0}, + {0x1BAA, 0x40, 0x40, 0}, + {0x1BB2, 0x10, 0x10, 0}, + {0x1BB3, 0x0, 0x80, 0}, + {0x1BC0, 0x10, 0x10, 0}, + {0x1BC1, 0x0, 0x80, 0}, + {0x1BCE, 0x10, 0x10, 0}, + {0x1BCF, 0x0, 0x80, 0}, + {0x1C08, 0x10, 0x10, 0}, + {0x1C09, 0x0, 0x80, 0}, + {0x1C16, 0x10, 0x10, 0}, + {0x1C17, 0x0, 0x80, 0}, + {0x1C24, 0x10, 0x10, 0}, + {0x1C25, 0x0, 0x80, 0}, + {0x1C32, 0x10, 0x10, 0}, + {0x1C33, 0x0, 0x80, 0}, + {0x1C40, 0x10, 0x10, 0}, + {0x1C41, 0x0, 0x80, 0}, + {0x1C4E, 0x10, 0x10, 0}, + {0x1C4F, 0x0, 0x80, 0}, + {0x1C88, 0x10, 0x10, 0}, + {0x1C89, 0x0, 0x80, 0}, + {0x1C96, 0x10, 0x10, 0}, + {0x1C97, 0x0, 0x80, 0}, + {0x1CA4, 0x10, 0x10, 0}, + {0x1CA5, 0x0, 0x80, 0}, + {0x1CB2, 0x10, 0x10, 0}, + {0x1CB3, 0x0, 0x80, 0}, + {0x1CC1, 0x10, 0x10, 0}, + {0x1CC2, 0x0, 0x80, 0}, + {0x1CCF, 0x10, 0x10, 0}, + {0x1CD0, 0x0, 0x80, 0}, + {0x1D08, 0x30, 0x30, 0}, + {0x1D09, 0x0, 0x80, 0}, + {0x1D16, 0x30, 0x30, 0}, + {0x1D17, 0x0, 0x80, 0}, + {0x1D24, 0x30, 0x30, 0}, + {0x1D25, 0x0, 0x80, 0}, + {0x1D32, 0x30, 0x30, 0}, + {0x1D33, 0x0, 0x80, 0}, + {0x1D41, 0x30, 0x30, 0}, + {0x1D42, 0x0, 0x80, 0}, + {0x1D88, 0x10, 0x10, 0}, + {0x1D89, 0x0, 0x80, 0}, + {0x1D91, 0xC, 0x7F, 0}, + {0x1D92, 0xC, 0x7F, 0}, + {0x1E0C, 0x0, 0xF, 0}, + {0x1E22, 0x1, 0x1, 0}, + {0x1E3A, 0x1, 0x1, 0}, + {0x1E3E, 0x1, 0x1, 0}, + {0x1E97, 0x2, 0x3, 0}, + {0x1E9B, 0x2, 0x3, 0}, + {0x1F0B, 0x8, 0xC, 0}, + {0x1F0F, 0x8, 0xC, 0}, + {0x1F8B, 0x8, 0xC, 0}, + {0x1F8F, 0x20, 0x30, 0}, + + /* Add UVLO 2.0 setting. also need to modify dts setting for main pmic */ + {0xA36, 0x2, 0x2, 0}, + {0xA89, 0x5, 0xF, 0}, + {0xA8A, 0x3, 0xF, 0}, + {0xA95, 0x40, 0x40, 0}, +}; + +static const struct mt6373_setting lp_setting[] = { + /* Suspend */ + {0x14a0, 0x1, 0x1, 0x0}, + {0x1494, 0x1, 0x1, 0x0}, + {0x149a, 0x1, 0x1, 0x0}, + {0x15a0, 0x1, 0x1, 0x0}, + {0x1594, 0x1, 0x1, 0x0}, + {0x159a, 0x1, 0x1, 0x0}, + {0x1820, 0x1, 0x1, 0x0}, + {0x1814, 0x1, 0x1, 0x0}, + {0x181a, 0x1, 0x1, 0x0}, + {0x18a0, 0x1, 0x1, 0x0}, + {0x1894, 0x1, 0x1, 0x0}, + {0x189a, 0x1, 0x1, 0x0}, + {0x1cac, 0x1, 0x1, 0xa}, + {0x1cb2, 0x1, 0x1, 0x0}, + {0x1cb8, 0x1, 0x1, 0x0}, + {0x1bbe, 0x1, 0x1, 0xa}, + {0x1bc4, 0x1, 0x1, 0x0}, + {0x1bca, 0x1, 0x1, 0x0}, + {0x1d22, 0x1, 0x1, 0xe}, + {0x1d28, 0x0, 0x1, 0xe}, + {0x1c64, 0x1, 0x1, 0xa}, + {0x1c6a, 0x1, 0x1, 0x0}, + {0x1c70, 0x1, 0x1, 0x0}, + {0x1d34, 0x1, 0x1, 0xe}, + {0x1d3a, 0x0, 0x1, 0xe}, + {0x1c88, 0x1, 0x1, 0xa}, + {0x1c8e, 0x1, 0x1, 0x0}, + {0x1c94, 0x1, 0x1, 0x0}, + {0x1b9a, 0x1, 0x1, 0xa}, + {0x1ba0, 0x1, 0x1, 0x0}, + {0x1ba6, 0x1, 0x1, 0x0}, + {0x1d08, 0x1, 0x1, 0xa}, + {0x1d0e, 0x1, 0x1, 0x0}, + {0x1d14, 0x1, 0x1, 0x0}, + {0x1d0e, 0x1, 0x1, 0x0}, + {0x1d14, 0x1, 0x1, 0x0}, + {0x1d9a, 0x1, 0x1, 0xa}, + {0x1da0, 0x1, 0x1, 0x0}, + {0x1da6, 0x1, 0x1, 0x0}, + + /* Deep idle */ + {0x1bbe, 0x1, 0x1, 0xc}, + {0x1bc4, 0x1, 0x1, 0x2}, + {0x1bca, 0x1, 0x1, 0x2}, + {0x1c64, 0x1, 0x1, 0xc}, + {0x1c6a, 0x1, 0x1, 0x2}, + {0x1c70, 0x1, 0x1, 0x2}, + {0x1c88, 0x1, 0x1, 0xc}, + {0x1c8e, 0x1, 0x1, 0x2}, + {0x1c94, 0x1, 0x1, 0x2}, + {0x1b9a, 0x1, 0x1, 0xc}, + {0x1ba0, 0x1, 0x1, 0x2}, + {0x1ba6, 0x1, 0x1, 0x2}, + {0x1d08, 0x1, 0x1, 0xc}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, + {0x1d0e, 0x1, 0x1, 0x2}, + {0x1d14, 0x1, 0x1, 0x2}, +}; + +void mt6373_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting); i++) + mt6373_write_field(init_setting[i].addr, init_setting[i].val, + init_setting[i].mask, init_setting[i].shift); + printk(BIOS_INFO, "%s done\n", __func__); +} + +void mt6373_lp_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(lp_setting); i++) + mt6373_write_field(lp_setting[i].addr, lp_setting[i].val, + lp_setting[i].mask, lp_setting[i].shift); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85129?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icbcd1f5a22388093781fd92c31889dd55a0ed9a3 Gerrit-Change-Number: 85129 Gerrit-PatchSet: 39 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: mb/google/rauru: Implement regulator interface
by Yu-Ping Wu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Hope Wang, Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85563?usp=email ) Change subject: mb/google/rauru: Implement regulator interface ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85563?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3cad68dbb2c5873c4e00066da18b1593b88ff499 Gerrit-Change-Number: 85563 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 04:01:38 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Mark Chang (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Angel Pons, Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, yuchi.chen(a)intel.com. Hello Angel Pons, Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Patrick Rudolph, Shuo Liu, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85532?usp=email to look at the new patch set (#4). Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Add support for MiTAC Computing Whitestone-2 mainboard The MiTAC Computing Whitestone2 O-RAN CU/DU Edge Server is a compact and highly efficient 1U rackmount solution designed for edge computing in O-RAN (Open Radio Access Network) environments. Featuring support for the 4th Gen Intel® Xeon® Scalable Processor Edge Enhanced Product Family, it delivers robust performance with a single socket (LGA-4677) that supports up to 205W TDP. The server provides excellent memory capabilities with 8 DDR5 RDIMM slots supporting 4400 MHz speeds across 8 channels per CPU. Working: - All eight DIMM slots - Serial port to emit spam - POST code display - Front USB 2.0 port - Front Intel E810 CAM1 (25Gbps x 4) - Front Intel E810 CAM2 (25Gbps x 4 / 10Gbps x 8) - M.2 2280/22110 slot x 2 (Gen3 x4) - Flashing internally with flashrom Untested for now (i.e. should work, will eventually test): - Riser PCIe Gen.4 x16 slots x 2 (FHHL) Others: - The board boots to Ubuntu 22.04.2 (5.15.0-1032-realtime) with all 40 cores (Intel 5433n) available. - FlexRAN 23.11 + DPDK 22.11.1 + ACC200 O-RU + O-DU long-run test pass. Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Signed-off-by: Mark Chang <mark.chang(a)mitaccomputing.com> --- A configs/config.mitaccomputing_ws_2 A src/mainboard/mitaccomputing/Kconfig A src/mainboard/mitaccomputing/Kconfig.name A src/mainboard/mitaccomputing/whitestone-2/Kconfig A src/mainboard/mitaccomputing/whitestone-2/Kconfig.name A src/mainboard/mitaccomputing/whitestone-2/Makefile.mk A src/mainboard/mitaccomputing/whitestone-2/acpi/platform.asl A src/mainboard/mitaccomputing/whitestone-2/board.fmd A src/mainboard/mitaccomputing/whitestone-2/board_info.txt A src/mainboard/mitaccomputing/whitestone-2/bootblock.c A src/mainboard/mitaccomputing/whitestone-2/devicetree.cb A src/mainboard/mitaccomputing/whitestone-2/dsdt.asl A src/mainboard/mitaccomputing/whitestone-2/include/smbios_onboard.h A src/mainboard/mitaccomputing/whitestone-2/include/spr_ws_2_gpio.h A src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h A src/mainboard/mitaccomputing/whitestone-2/mainboard.c A src/mainboard/mitaccomputing/whitestone-2/ramstage.c A src/mainboard/mitaccomputing/whitestone-2/romstage.c 18 files changed, 739 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/85532/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Wilson-MiTACComputing <wilson.chien(a)mitaccomputing.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com>

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[S] Change in coreboot[main]: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
by Rui Zhou (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Rui Zhou has posted comments on this change by Rui Zhou. ( https://review.coreboot.org/c/coreboot/+/85566?usp=email ) Change subject: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > I think it might be better not to revert. […] Of course, I can also revert, and when I cherry-pick this cl, I can manually modify the content to suit the FW branch. -- To view, visit https://review.coreboot.org/c/coreboot/+/85566?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id2415d18c635dece94500f511bccdc9d2b69d1b4 Gerrit-Change-Number: 85566 Gerrit-PatchSet: 3 Gerrit-Owner: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Kun Liu <liukun11(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 13 Dec 2024 03:30:12 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Rui Zhou <zhourui(a)huaqin.corp-partner.google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com>

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[L] Change in coreboot[main]: mb/google/brya/var/uldrenite: update gpio settings
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85522?usp=email ) Change subject: mb/google/brya/var/uldrenite: update gpio settings ...................................................................... mb/google/brya/var/uldrenite: update gpio settings Configure GPIOs according to schematic_20241203. BUG=b:380789023 TEST=emerge-nissa coreboot Change-Id: I3c5cb298fd0a4108af8f65abd9eeddbfe5b7afc4 Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85522 Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/uldrenite/gpio.c 1 file changed, 429 insertions(+), 4 deletions(-) Approvals: Dtrain Hsu: Looks good to me, approved Kapil Porwal: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/uldrenite/gpio.c b/src/mainboard/google/brya/variants/uldrenite/gpio.c index beee6fc..ddb7b08 100644 --- a/src/mainboard/google/brya/variants/uldrenite/gpio.c +++ b/src/mainboard/google/brya/variants/uldrenite/gpio.c @@ -8,17 +8,441 @@ /* Pad configuration in ramstage */ static const struct pad_config gpio_table[] = { - /* TODO */ + /* A0 thru A4, A9 and A10 come configured out of reset, do not touch */ + /* A0 : ESPI_IO0 ==> ESPI_SOC_D0_EC */ + /* A1 : ESPI_IO1 ==> ESPI_SOC_D1_EC */ + /* A2 : ESPI_IO2 ==> ESPI_SOC_D2_EC */ + /* A3 : ESPI_IO3 ==> ESPI_SOC_D3_EC */ + /* A4 : ESPI_CS0# ==> ESPI_SOC_CS_EC_L */ + /* A5 : ESPI_ALERT0# ==> NC */ + PAD_NC(GPP_A5, NONE), + /* A6 : ESPI_ALERT1# ==> NC */ + PAD_NC(GPP_A6, NONE), + /* A7 : NC */ + PAD_NC(GPP_A7, NONE), + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_CFG_GPO(GPP_A8, 1, DEEP), + /* A9 : ESPI_CLK ==> ESPI_SOC_CLK */ + /* A10 : ESPI_RESET# ==> ESPI_SOC_RST_EC_L */ + /* A11 : EN_SPK_PA ==> NC */ + PAD_NC(GPP_A11, NONE), + /* A12 : NC */ + PAD_NC(GPP_A12, NONE), + /* A13 : GPP_A13 ==> SOC_BT_ON */ + PAD_CFG_GPO_LOCK(GPP_A13, 1, LOCK_CONFIG), + /* A14 : USB_OC1# ==> NC */ + PAD_NC(GPP_A14, NONE), + /* A15 : USB_OC2# ==> NC */ + PAD_NC(GPP_A15, NONE), + /* A16 : USB_OC3# ==> NC */ + PAD_NC_LOCK(GPP_A16, NONE, LOCK_CONFIG), + /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT), + /* A18 : DDSP_HPDB ==> NC */ + PAD_NC(GPP_A18, NONE), + /* A19 : NC */ + PAD_NC(GPP_A19, NONE), + /* A20 : NC */ + PAD_NC(GPP_A20, NONE), + /* A21 : DDPC_CTRLCLK ==> TCHSCR_REPORT_EN */ + PAD_CFG_GPO(GPP_A21, 0, DEEP), + /* A22 : GPP_A22 ==> NC */ + PAD_NC(GPP_A22, NONE), + /* A23 : GPP_A23 ==> NC */ + PAD_NC(GPP_A23, NONE), + + /* B0 : CORE_VID0 ==> VCCIN_AUX_VID0 */ + PAD_CFG_NF(GPP_B0, NONE, DEEP, NF1), + /* B1 : CORE_VID1 ==> VCCIN_AUX_VID1 */ + PAD_CFG_NF(GPP_B1, NONE, DEEP, NF1), + /* B2 : NC */ + PAD_NC(GPP_B2, NONE), + /* B3 : CPU_GP2 ==> EC_TP_INT */ + PAD_CFG_GPI_IRQ_WAKE(GPP_B3, NONE, PWROK, LEVEL, INVERT), + /* B4 : PROC_GP3 ==> EN_PP3300_UCAM_X */ + PAD_CFG_GPO_LOCK(GPP_B4, 1, LOCK_CONFIG), + /* B5 : GPP_B5 ==> NC */ + PAD_NC(GPP_B5, NONE), + /* B6 : GPP_B6 ==> NC */ + PAD_NC(GPP_B6, NONE), + /* B7 : GPP_B7 ==> NC */ + PAD_NC_LOCK(GPP_B7, NONE, LOCK_CONFIG), + /* B8 : GPP_B8 ==> NC */ + PAD_NC_LOCK(GPP_B8, NONE, LOCK_CONFIG), + /* B9 : Not available */ + PAD_NC(GPP_B9, NONE), + /* B10 : Not available */ + PAD_NC(GPP_B10, NONE), + /* B11 : SOC_PD_INT# */ + PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1), + /* B12 : SLP_S0# ==> PM_SLP_S0# */ + PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1), + /* B13 : PLTRST# ==> PLT_RST_L */ + PAD_CFG_NF_LOCK(GPP_B13, NONE, NF1, LOCK_CONFIG), + /* B14 : SPKR ==> GPP_B14_STRAP */ + PAD_NC_LOCK(GPP_B14, NONE, LOCK_CONFIG), + /* B15 : NC */ + PAD_NC_LOCK(GPP_B15, NONE, LOCK_CONFIG), + /* B16 : GPP_B16 ==> I2C_5_SDA */ + PAD_CFG_NF_LOCK(GPP_B16, NONE, NF2, LOCK_CONFIG), + /* B17 : GPP_B17 ==> I2C_5_SCL */ + PAD_CFG_NF_LOCK(GPP_B17, NONE, NF2, LOCK_CONFIG), + /* B18 : GPP_B18 ==> GPP_B18_STRAP */ + PAD_NC(GPP_B18, NONE), + /* B19 : Not available */ + PAD_NC(GPP_B19, NONE), + /* B20 : Not available */ + PAD_NC(GPP_B20, NONE), + /* B21 : Not available */ + PAD_NC(GPP_B21, NONE), + /* B22 : Not available */ + PAD_NC(GPP_B22, NONE), + /* B23 : SML1ALERT# ==> PCHHOT_ODL_STRAP */ + PAD_NC(GPP_B23, NONE), + + /* C0 : NC */ + PAD_NC(GPP_C0, NONE), + /* C1 : NC */ + PAD_NC(GPP_C1, NONE), + /* C2 : SMBALERT# ==> GPP_C2_STRAP */ + PAD_NC(GPP_C2, NONE), + /* C3 : NC */ + PAD_NC(GPP_C3, NONE), + /* C4 : NC */ + PAD_NC(GPP_C4, NONE), + /* C5 : SML0ALERT# ==> GPP_C5_STRAP */ + PAD_NC(GPP_C5, NONE), + /* C6 : SML1_SMBCLK */ + PAD_CFG_NF(GPP_C6, NONE, DEEP, NF1), + /* C7 : SML1_SMBDATA */ + PAD_CFG_NF(GPP_C7, NONE, DEEP, NF1), + + /* D0 : ISH_GP0 ==> UCAM_FW_PROTECT */ + PAD_CFG_GPO(GPP_D0, 1, DEEP), + /* D1 : ISH_GP1 ==> NC */ + PAD_NC(GPP_D1, NONE), + /* D2 : ISH_GP2 ==> TOUCH_SCREEN_DET# */ + PAD_CFG_GPO_LOCK(GPP_D2, 1, LOCK_CONFIG), + /* D3 : NC ==> PHY_SHUTTER_DET */ + PAD_CFG_GPO_LOCK(GPP_D3, 1, LOCK_CONFIG), + /* D4 : NC ==> WCAM_FW_PROTECT */ + PAD_CFG_GPO(GPP_D4, 1, DEEP), + /* D5 : NC */ + PAD_NC(GPP_D5, NONE), + /* D6 : NC */ + PAD_NC(GPP_D6, NONE), + /* D7 : GPP_D7 ==> CLKREQ_PCIE#2 */ + PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1), + /* D8 : SRCCLKREQ3# ==> NC */ + PAD_NC(GPP_D8, NONE), + /* D9 : NC */ + PAD_NC_LOCK(GPP_D9, NONE, LOCK_CONFIG), + /* D10 : ISH_SPI_CLK ==> GPP_D10_STRAP */ + PAD_NC_LOCK(GPP_D10, NONE, LOCK_CONFIG), + /* D11 : NC */ + PAD_NC_LOCK(GPP_D11, NONE, LOCK_CONFIG), + /* D12 : ISH_SPI_MOSI ==> GPP_D12_STRAP */ + PAD_NC_LOCK(GPP_D12, NONE, LOCK_CONFIG), + /* D13 : UART0_ISH_RXD ==> NC */ + PAD_NC(GPP_D13, NONE), + /* D14 : UART0_ISH_TXD ==> LCD_CBL_DET# */ + PAD_CFG_GPO(GPP_D14, 1, DEEP), + /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */ + PAD_CFG_GPO_LOCK(GPP_D15, 1, LOCK_CONFIG), + /* D16 : ISH_UART0_CTS# ==> SOC_TS_I2C_INT# */ + PAD_CFG_GPI_APIC(GPP_D16, NONE, PLTRST, LEVEL, INVERT), + /* D17 : NC ==> UART1_ISH_RX_DBG_TX */ + PAD_CFG_NF(GPP_D17, NONE, DEEP, NF2), + /* D18 : NC ==> UART1_ISH_TX_DBG_RX */ + PAD_CFG_NF(GPP_D18, NONE, DEEP, NF2), + /* D19 : I2S_MCLK1_OUT ==> NC */ + PAD_NC(GPP_D19, NONE), + + /* E0 : NC */ + PAD_NC(GPP_E0, NONE), + /* E1 : THC0_SPI1_IO2 ==> RAM_ID1 */ + PAD_CFG_GPI_LOCK(GPP_E1, NONE, LOCK_CONFIG), + /* E2 : THC0_SPI1_IO3 ==> RAM_ID0 */ + PAD_CFG_GPI_LOCK(GPP_E2, NONE, LOCK_CONFIG), + /* E3 : PROC_GP0 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER_LOCK(GPP_E3, NONE, LOCK_CONFIG), + /* E4 : NC */ + PAD_NC(GPP_E4, NONE), + /* E5 : NC */ + PAD_NC(GPP_E5, NONE), + /* E6 : THC0_SPI1_RST# ==> GPP_E6_STRAP */ + PAD_NC_LOCK(GPP_E6, NONE, LOCK_CONFIG), + /* E7 : NC */ + PAD_NC(GPP_E7, NONE), + /* E8 : GPP_E8 ==> WLAN_DISABLE_L */ + PAD_CFG_GPO(GPP_E8, 1, DEEP), + /* E9 : NC */ + PAD_NC_LOCK(GPP_E9, NONE, LOCK_CONFIG), + /* E10 : NC */ + PAD_NC_LOCK(GPP_E10, NONE, LOCK_CONFIG), + /* E11 : NC */ + PAD_NC_LOCK(GPP_E11, NONE, LOCK_CONFIG), + /* E12 : THC0_SPI1_IO1 ==> RAM_ID2 */ + PAD_CFG_GPI_LOCK(GPP_E12, NONE, LOCK_CONFIG), + /* E13 : NC ==> RAM_ID3 */ + PAD_CFG_GPI_LOCK(GPP_E13, NONE, LOCK_CONFIG), + /* E14 : DDSP_HPDA ==> EDP_HPD */ + PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1), + /* E15 : NC */ + PAD_NC(GPP_E15, NONE), + /* E16 : NC ==> WWAN_PCIE_WAKE_ODL */ + PAD_CFG_GPI_SCI_LOW(GPP_E16, NONE, DEEP, LEVEL), + /* E17 : GPP_E17 ==> SOC_TS_PWR_EN */ + PAD_CFG_GPO_LOCK(GPP_E17, 1, LOCK_CONFIG), + /* E18 : NC */ + PAD_NC(GPP_E18, NONE), + /* E19 : DDP1_CTRLDATA ==> GPP_E19_STRAP */ + PAD_NC(GPP_E19, NONE), + /* E20 : NC */ + PAD_NC(GPP_E20, NONE), + /* E21 : NC */ + PAD_NC(GPP_E21, NONE), + /* E22 : DDPA_CTRLCLK ==> NC */ + PAD_NC(GPP_E22, NONE), + /* E23 : DDPA_CTRLDATA ==> NC */ + PAD_NC(GPP_E23, NONE), + + /* F0 : CNV_BRI_DT ==> CNV_BRI_CTX_DRX */ + PAD_CFG_NF(GPP_F0, NONE, DEEP, NF1), + /* F1 : CNV_BRI_RSP ==> CNV_BRI_CRX_DTX */ + PAD_CFG_NF(GPP_F1, UP_20K, DEEP, NF1), + /* F2 : CNV_RGI_DT ==> CNV_RGI_CTX_DRX */ + PAD_CFG_NF(GPP_F2, NONE, DEEP, NF1), + /* F3 : CNV_RGI_RSP ==> CNV_RGI_CRX_DTX */ + PAD_CFG_NF(GPP_F3, UP_20K, DEEP, NF1), + /* F4 : CNV_RF_RESET# ==> CNV_RF_RESET# */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), + /* F5 : MODEM_CLKREQ ==> CLKREQ_CNV# */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF2), + /* F6 : CNV_PA_BLANKING ==> NC */ + PAD_NC(GPP_F6, NONE), + /* F7 : GPP_F7 ==> GPP_F7_STRAP */ + PAD_NC(GPP_F7, NONE), + /* F8 : Not available */ + PAD_NC(GPP_F8, NONE), + /* F9 : Not available */ + PAD_NC(GPP_F9, NONE), + /* F10 : GPP_F10 ==> GPP_F10_STRAP */ + PAD_NC(GPP_F10, NONE), + /* F11 : NC */ + PAD_NC_LOCK(GPP_F11, NONE, LOCK_CONFIG), + /* F12 : NC ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* F13 : NC ==> PLTRST_WWAN# */ + PAD_CFG_GPO(GPP_F13, 0, DEEP), + /* F14 : NC */ + PAD_NC(GPP_F14, NONE), + /* F15 : NC */ + PAD_NC_LOCK(GPP_F15, NONE, LOCK_CONFIG), + /* F16 : NC */ + PAD_NC_LOCK(GPP_F16, NONE, LOCK_CONFIG), + /* F17 : THC1_SPI2_RST# ==> EC_SOC_WAKE_ODL */ + PAD_CFG_GPI_IRQ_WAKE(GPP_F17, NONE, PWROK, EDGE_SINGLE, INVERT), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI_LOCK(GPP_F18, NONE, LOCK_CONFIG), + /* F19 : Not available */ + PAD_NC(GPP_F19, NONE), + /* F20 : Not available */ + PAD_NC(GPP_F20, NONE), + /* F21 : Not available */ + PAD_NC(GPP_F21, NONE), + /* F22 : NC */ + PAD_NC(GPP_F22, NONE), + /* F23 : V1P05_CTRL ==> V1P05EXT_CTRL */ + PAD_CFG_NF(GPP_F23, NONE, DEEP, NF1), + + /* H0 : GPP_H0_STRAP */ + PAD_NC(GPP_H0, NONE), + /* H1 : GPP_H1_STRAP */ + PAD_NC(GPP_H1, NONE), + /* H2 : GPP_H2_STRAP */ + PAD_NC(GPP_H2, NONE), + /* H3 : NC */ + PAD_NC_LOCK(GPP_H3, NONE, LOCK_CONFIG), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF_LOCK(GPP_H4, NONE, NF1, LOCK_CONFIG), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF_LOCK(GPP_H5, NONE, NF1, LOCK_CONFIG), + /* H6 : I2C1_SDA ==> I2C_1_SDA */ + PAD_CFG_NF(GPP_H6, NONE, DEEP, NF1), + /* H7 : I2C1_SCL ==> I2C_1_SCL */ + PAD_CFG_NF(GPP_H7, NONE, DEEP, NF1), + /* H8 : NC */ + PAD_NC(GPP_H8, NONE), + /* H9 : NC */ + PAD_NC(GPP_H9, NONE), + /* H10 : UART0_RXD ==> UART_2_CRXD_DTXD */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_2_CTXD_DRXD */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H12 : NC */ + PAD_NC(GPP_H12, NONE), + /* H13 : NC */ + PAD_NC(GPP_H13, NONE), + /* H14 : Not available */ + PAD_NC(GPP_H14, NONE), + /* H15 : NC */ + PAD_NC(GPP_H15, NONE), + /* H16 : Not available */ + PAD_NC(GPP_H16, NONE), + /* H17 : PD_SOC_DBG_L */ + PAD_CFG_GPI(GPP_H17, NONE, PLTRST), + /* H18 : PROC_C10_GATE# ==> CPU_C10_GATE# */ + PAD_CFG_NF(GPP_H18, NONE, DEEP, NF1), + /* H19 : NC */ + PAD_NC(GPP_H19, NONE), + /* H20 : IMGCLKOUT1 ==> NC */ + PAD_NC(GPP_H20, NONE), + /* H21 : NC */ + PAD_NC(GPP_H21, NONE), + /* H22 : NC */ + PAD_NC(GPP_H22, NONE), + /* H23 : LTE_PWR_OFF_EN */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), + + /* R0 : HDA_BCLK ==> HDA_BIT_CLK */ + PAD_CFG_NF(GPP_R0, NONE, DEEP, NF1), + /* R1 : HDA_SYNC ==> HEN_PP3300_TCHSCR_XDA_SYNC */ + PAD_CFG_NF(GPP_R1, NONE, DEEP, NF1), + /* R2 : HDA_SDO ==> HDA_SDOUT */ + PAD_CFG_NF(GPP_R2, NONE, DEEP, NF1), + /* R3 : HDA_SDI0 ==> HDA_SDIN0 */ + PAD_CFG_NF(GPP_R3, NONE, DEEP, NF1), + /* R4 : HDA_RST# ==> HDA_RST# */ + PAD_CFG_NF(GPP_R4, NONE, DEEP, NF1), + /* R5 : HDA_SDI1 ==> HDA_SDIN1 */ + PAD_CFG_NF(GPP_R5, NONE, DEEP, NF1), + /* R6 : DMIC_CLK1_R */ + PAD_CFG_NF(GPP_R6, NONE, DEEP, NF3), + /* R7 : DMIC_DATA1_R */ + PAD_CFG_NF(GPP_R7, NONE, DEEP, NF3), + + /* S0 : I2S_SPK_BCLK_R ==> NC */ + PAD_NC(GPP_S0, NONE), + /* S1 : I2S_SPK_LRCK_R ==> NC */ + PAD_NC(GPP_S1, NONE), + /* S2 : DMIC_CKL_A0 ==> PCH_DMIC_CLK */ + PAD_CFG_NF(GPP_S2, NONE, DEEP, NF2), + /* S3 : DMIC_DATA0 ==> PCH_DMIC_DATA */ + PAD_CFG_NF(GPP_S3, NONE, DEEP, NF2), + /* S4 : NC */ + PAD_NC(GPP_S4, NONE), + /* S5 : NC */ + PAD_NC(GPP_S5, NONE), + /* S6 : NC */ + PAD_NC(GPP_S6, NONE), + /* S7 : NC */ + PAD_NC(GPP_S7, NONE), + + /* I5 : NC */ + PAD_NC(GPP_I5, NONE), + /* I7 : EMMC_CMD ==> EMMC_CMD */ + PAD_CFG_NF(GPP_I7, NONE, DEEP, NF1), + /* I8 : EMMC_DATA0 ==> EMMC_D0 */ + PAD_CFG_NF(GPP_I8, NONE, DEEP, NF1), + /* I9 : EMMC_DATA1 ==> EMMC_D1 */ + PAD_CFG_NF(GPP_I9, NONE, DEEP, NF1), + /* I10 : EMMC_DATA2 ==> EMMC_D2 */ + PAD_CFG_NF(GPP_I10, NONE, DEEP, NF1), + /* I11 : EMMC_DATA3 ==> EMMC_D3 */ + PAD_CFG_NF(GPP_I11, NONE, DEEP, NF1), + /* I12 : EMMC_DATA4 ==> EMMC_D4 */ + PAD_CFG_NF(GPP_I12, NONE, DEEP, NF1), + /* I13 : EMMC_DATA5 ==> EMMC_D5 */ + PAD_CFG_NF(GPP_I13, NONE, DEEP, NF1), + /* I14 : EMMC_DATA6 ==> EMMC_D6 */ + PAD_CFG_NF(GPP_I14, NONE, DEEP, NF1), + /* I15 : EMMC_DATA7 ==> EMMC_D7 */ + PAD_CFG_NF(GPP_I15, NONE, DEEP, NF1), + /* I16 : EMMC_RCLK ==> EMMC_RCLK */ + PAD_CFG_NF(GPP_I16, NONE, DEEP, NF1), + /* I17 : EMMC_CLK ==> EMMC_CLK */ + PAD_CFG_NF(GPP_I17, NONE, DEEP, NF1), + /* I18 : EMMC_RESET# ==> EMMC_RST_L */ + PAD_CFG_NF(GPP_I18, NONE, DEEP, NF1), + + /* GPD0 : BATLOW# ==> SOC_BATLOW_L */ + PAD_CFG_NF(GPD0, NONE, DEEP, NF1), + /* GPD1 : ACPRESENT ==> SOC_ACPRESENT */ + PAD_CFG_NF(GPD1, NONE, DEEP, NF1), + /* GPD2 : EC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPD2, NONE, PLTRST, LEVEL, INVERT), + /* GPD3 : PWRBTN# ==> EC_SOC_PWR_BTN_ODL */ + PAD_CFG_NF(GPD3, NONE, DEEP, NF1), + /* GPD4 : SLP_S3# ==> SLP_S3_L */ + PAD_CFG_NF(GPD4, NONE, DEEP, NF1), + /* GPD5 : SLP_S4# ==> SLP_S4_L */ + PAD_CFG_NF(GPD5, NONE, DEEP, NF1), + /* GPD6 : SLP_A# ==> NC */ + PAD_NC(GPD6, NONE), + /* GPD7 : GPD7_STRAP */ + PAD_NC(GPD7, NONE), + /* GPD8 : SUSCLK ==> PCH_SUSCLK */ + PAD_CFG_NF(GPD8, NONE, DEEP, NF1), + /* GPD9 : NC */ + PAD_NC(GPD9, NONE), + /* GPD10 : SLP_S5# ==> NC */ + PAD_NC(GPD10, NONE), + /* GPD11 : NC */ + PAD_NC(GPD11, NONE), + + /* Configure the unused virtual CNVi Bluetooth UART pads to NC mode. */ + /* vCNV_BT_UART_TXD */ + PAD_NC(GPP_VGPIO_6, NONE), + /* vCNV_BT_UART_RXD */ + PAD_NC(GPP_VGPIO_7, NONE), + /* vCNV_BT_UART_CTS_B */ + PAD_NC(GPP_VGPIO_8, NONE), + /* vCNV_BT_UART_RTS_B */ + PAD_NC(GPP_VGPIO_9, NONE), + + /* Configure the unused vUART for Bluetooth pads to NC mode. */ + /* vUART0_TXD */ + PAD_NC(GPP_VGPIO_18, NONE), + /* vUART0_RXD */ + PAD_NC(GPP_VGPIO_19, NONE), + /* vUART0_CTS_B */ + PAD_NC(GPP_VGPIO_20, NONE), + /* vUART0_RTS_B */ + PAD_NC(GPP_VGPIO_21, NONE), }; /* Early pad configuration in bootblock */ static const struct pad_config early_gpio_table[] = { - /* TODO */ + /* A17 : GPP_A17 ==> GSC_SOC_INT_ODL */ + PAD_CFG_GPI_APIC(GPP_A17, NONE, PLTRST, LEVEL, INVERT), + /* E3 : PROC_GP0 ==> SOC_WP_OD */ + PAD_CFG_GPI_GPIO_DRIVER(GPP_E3, NONE, DEEP), + /* F12 : NC ==> WWAN_RST_L */ + PAD_CFG_GPO(GPP_F12, 0, DEEP), + /* F13 : NC ==> PLTRST_WWAN# */ + PAD_CFG_GPO(GPP_F13, 0, DEEP), + /* F18 : THC1_SPI2_INT# ==> EC_IN_RW_OD */ + PAD_CFG_GPI(GPP_F18, NONE, DEEP), + /* H4 : I2C0_SDA ==> SOC_I2C_GSC_SDA */ + PAD_CFG_NF(GPP_H4, NONE, DEEP, NF1), + /* H5 : I2C0_SCL ==> SOC_I2C_GSC_SCL */ + PAD_CFG_NF(GPP_H5, NONE, DEEP, NF1), + /* H10 : UART0_RXD ==> UART_SOC_RX_DBG_TX */ + PAD_CFG_NF(GPP_H10, NONE, DEEP, NF2), + /* H11 : UART0_TXD ==> UART_SOC_TX_DBG_RX */ + PAD_CFG_NF(GPP_H11, NONE, DEEP, NF2), + /* H23 : LTE_PWR_OFF_EN */ + PAD_CFG_GPO(GPP_H23, 0, DEEP), }; /* Fill romstage gpio configuration */ static const struct pad_config romstage_gpio_table[] = { - /* TODO */ + /* Enable touchscreen, hold in reset */ + /* E17 : GPP_E17 ==> SOC_TS_PWR_EN */ + PAD_CFG_GPO(GPP_E17, 1, DEEP), + /* D15 : GPP_D15 ==> SOC_TS_I2C_RST# */ + PAD_CFG_GPO(GPP_D15, 0, DEEP), }; const struct pad_config *variant_gpio_table(size_t *num) @@ -40,7 +464,8 @@ } static const struct cros_gpio cros_gpios[] = { - /* TODO */ + CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME), + CROS_GPIO_WP_AH(GPIO_PCH_WP, CROS_GPIO_DEVICE_NAME), }; DECLARE_CROS_GPIOS(cros_gpios); -- To view, visit https://review.coreboot.org/c/coreboot/+/85522?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c5cb298fd0a4108af8f65abd9eeddbfe5b7afc4 Gerrit-Change-Number: 85522 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: mb/google/trulo/var/uldrenite: Add memory config
by Subrata Banik (Code Review) 13 Dec '24

13 Dec '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85542?usp=email ) Change subject: mb/google/trulo/var/uldrenite: Add memory config ...................................................................... mb/google/trulo/var/uldrenite: Add memory config Fill in memory config based on the schematic_20241203. BUG=b:380476928, b:380789023 TEST=emerge-nissa coreboot Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85542 Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> Reviewed-by: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/uldrenite/Makefile.mk A src/mainboard/google/brya/variants/uldrenite/memory.c 2 files changed, 114 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Kapil Porwal: Looks good to me, approved Dtrain Hsu: Looks good to me, approved Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk index 91f031e..4c33dad 100644 --- a/src/mainboard/google/brya/variants/uldrenite/Makefile.mk +++ b/src/mainboard/google/brya/variants/uldrenite/Makefile.mk @@ -2,4 +2,5 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-y += memory.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brya/variants/uldrenite/memory.c b/src/mainboard/google/brya/variants/uldrenite/memory.c new file mode 100644 index 0000000..03e97a1 --- /dev/null +++ b/src/mainboard/google/brya/variants/uldrenite/memory.c @@ -0,0 +1,113 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ + +#include <baseboard/variants.h> +#include <gpio.h> +#include <soc/romstage.h> + +static const struct mb_cfg variant_memcfg = { + .type = MEM_TYPE_LP5X, + + .rcomp = { + /* Baseboard uses only 100ohm Rcomp resistors */ + .resistor = 100, + }, + + /* DQ byte map */ + .lpx_dq_map = { + .ddr0 = { + .dq0 = { 11, 15, 13, 12, 9, 10, 14, 8 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr1 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr2 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr3 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + .ddr4 = { + .dq0 = { 11, 15, 13, 12, 9, 10, 14, 8 }, + .dq1 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + }, + .ddr5 = { + .dq0 = { 3, 1, 2, 0, 4, 7, 5, 6 }, + .dq1 = { 13, 9, 8, 11, 10, 14, 15, 12 }, + }, + .ddr6 = { + .dq0 = { 2, 1, 3, 0, 4, 6, 5, 7 }, + .dq1 = { 8, 9, 10, 11, 13, 14, 12, 15 }, + }, + .ddr7 = { + .dq0 = { 3, 0, 1, 2, 5, 6, 4, 7 }, + .dq1 = { 13, 9, 11, 8, 14, 15, 10, 12 }, + }, + }, + + /* DQS CPU<>DRAM map */ + .lpx_dqs_map = { + .ddr0 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr1 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr2 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr3 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr4 = { .dqs0 = 1, .dqs1 = 0 }, + .ddr5 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr6 = { .dqs0 = 0, .dqs1 = 1 }, + .ddr7 = { .dqs0 = 0, .dqs1 = 1 }, + }, + + .lp5x_config = { + .ccc_config = 0xff, + }, + + .ect = 1, /* Early Command Training */ + + .UserBd = BOARD_TYPE_MOBILE, +}; + +const struct mb_cfg *variant_memory_params(void) +{ + return &variant_memcfg; +} + +int variant_memory_sku(void) +{ + /* + * Memory configuration board straps + * GPIO_MEM_CONFIG_0 GPP_E2 + * GPIO_MEM_CONFIG_1 GPP_E1 + * GPIO_MEM_CONFIG_2 GPP_E12 + * GPIO_MEM_CONFIG_3 GPP_E13 + */ + gpio_t spd_gpios[] = { + GPP_E2, + GPP_E1, + GPP_E12, + GPP_E13 + }; + + return gpio_base2_value(spd_gpios, ARRAY_SIZE(spd_gpios)); +} + +bool variant_is_half_populated(void) +{ + /* + * Ideally half_populated is used in platforms with multiple channels to + * enable only one half of the channel. Alder Lake-N has single channel, + * and it would require for new structures to be defined in meminit block + * driver for LPx memory configurations. In order to avoid adding new + * structures, set half_populated to true. This has the same effect as + * having single channel with 64-bit width. + */ + return true; +} + +void variant_get_spd_info(struct mem_spd *spd_info) +{ + spd_info->topo = MEM_TOPO_MEMORY_DOWN; + spd_info->cbfs_index = variant_memory_sku(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85542?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I28865fb3787b8195504fb890e05447fbc4d55ddf Gerrit-Change-Number: 85542 Gerrit-PatchSet: 5 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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coreboot-gerrit December 2024