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Change subject: mb/google/brya/var/uldrenite: update gpio settings
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/brya/variants/uldrenite/gpio.c:
https://review.coreboot.org/c/coreboot/+/85522/comment/d9bdd7dc_cd432219?us… :
PS4, Line 453:
: const struct pad_config *variant_gpio_override_table(size_t *num)
: {
: *num = 0;
: return NULL;
: }
> It cannot be removed because it is required for mainboard initialization. […]
oh no weak function for it.
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Change subject: soc/intel/alderlake: Add function to force disable memory channels
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/alderlake/meminit.c:
https://review.coreboot.org/c/coreboot/+/85529/comment/12c3edc0_9112e795?us… :
PS1, Line 252: if (ch_disable_mask == 0) {
> Is this rule applicable to memory down topology only?
the same rule also apply on MC1 channels?
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Change subject: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
> I think you still need fw_config_is_provisioned for SMT? or your factory will always pre-flash FW co […]
The FW branch(15217) of nissa is relatively old,, and the method of not updating fw_config (probe unprovisioned) is not supported, so fw_config will still be updated first, but the Bluetooth of WIFI6E will not be usable. It is currently used in the fw branch (skipping upstream).https://chromium-review.googlesource.com/c/chromiumos/third_party…
Due to the existence of ```assert```, we can't directly use ```fw_config_probe(FW_CONFIG(WIFI, WIFI_UNKNOWN))```, otherwise it will fail to boot. However, since the BT function is ignored, it is better to continue using the ```WIFI_UNKNOWN``` method from the source.
https://chromium-review.googlesource.com/c/chromiumos/third_party/coreboot/…
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Change subject: soc/intel/xeon_sp: Enable IDT_IN_EVERY_STAGE
......................................................................
Patch Set 1:
(1 comment)
Patchset:
PS1:
Will do some tests around. Back later.
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Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
File src/cpu/intel/car/romstage.c:
https://review.coreboot.org/c/coreboot/+/85568/comment/1435ea5b_2a1ddb8e?us… :
PS1, Line 40: stack_canary_breakpoint_remove();
The stack canary is enabled in bootblock ahead of time, right? Not sure if it is a good pattern to do stack_canary_breakpoint_remove at end of each phase/block and stack_canary_breakpoint_init at the head of the each phase/block?
https://review.coreboot.org/c/coreboot/+/85568/comment/c7a52678_d19fb004?us… :
PS1, Line 44:
Maybe add comments to specify stack canary and stack guard servers different purposes? e.g., the former is for coreboot stack usage and warns at real time, while the latter also covers FSP-M stack usage and provides an afterwards check.
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Change subject: mb/google/nissa/var/rull: For probe, change unprovisioned to unknown
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
I think you still need fw_config_is_provisioned for SMT? or your factory will always pre-flash FW config?
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Change subject: soc/intel/xeon_sp: Merge SKX and CPX
......................................................................
Patch Set 5:
(5 comments)
Patchset:
PS5:
May
Commit Message:
https://review.coreboot.org/c/coreboot/+/85557/comment/2aad8f8b_fe1700f7?us… :
PS5, Line 10: - Create a new 14nm folder
There are '(xx)nm - old' and 'intel(x) - new' for process namings which is confusing. Maybe still using gen(x) as what is currently using to be consistent?
File src/soc/intel/xeon_sp/14nm/acpi/gpio.asl:
PS5:
Should we still place the 'acpi' ahead of '14nm (or gen1)' to be consistent?
File src/soc/intel/xeon_sp/cpx/Kconfig:
https://review.coreboot.org/c/coreboot/+/85557/comment/a176eb9a_83fb016b?us… :
PS5, Line 5: select SOC_INTEL_XEON_SP_14NM
Maybe we can have a SOC_INTEL_XEON_SP_GEN3 but select the same kconfigs as SOC_INTEL_XEON_SP_GEN1
File src/soc/intel/xeon_sp/skx/Kconfig:
https://review.coreboot.org/c/coreboot/+/85557/comment/0f65b4f1_87a8708a?us… :
PS5, Line 5: select SOC_INTEL_XEON_SP_14NM
SOC_INTEL_XEON_SP_GEN1?
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Change subject: cpu/x86/topology: Simplify CPU topology initialization
......................................................................
Patch Set 1: Code-Review+1
(3 comments)
Patchset:
PS1:
LGTM. Will do a test on SPR and GNR to make sure no regression.
File src/cpu/x86/topology.c:
https://review.coreboot.org/c/coreboot/+/85576/comment/ebc224fb_3edc3cf6?us… :
PS1, Line 20: };
Add a comment to specify to refer to Intel SDM for the level type definitions?
https://review.coreboot.org/c/coreboot/+/85576/comment/e2081360_6124d846?us… :
PS1, Line 34: uint8_t nb_bits;
num_bits to be more straightforward?
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