coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Disable stack overflow debug options
by Kapil Porwal (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Pranava Y N, Subrata Banik. Kapil Porwal has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85584?usp=email ) Change subject: soc/intel/pantherlake: Disable stack overflow debug options ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f Gerrit-Change-Number: 85584 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 10:52:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Disable stack overflow debug options
by Dinesh Gehlot (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Kapil Porwal, Pranava Y N, Subrata Banik. Dinesh Gehlot has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/85584?usp=email ) Change subject: soc/intel/pantherlake: Disable stack overflow debug options ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85584?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I31b99a7b6de221d3ec23f6538c078d0797a6084f Gerrit-Change-Number: 85584 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 10:48:46 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
by Angel Pons (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85153?usp=email ) Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 ...................................................................... Patch Set 13: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 13 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 10:21:37 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: Add support for MiTAC Computing Whitestone-2 mainboard
by Angel Pons (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Jincheng Li, Lean Sheng Tan, Mark Chang, Patrick Rudolph, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Mark Chang. ( https://review.coreboot.org/c/coreboot/+/85532?usp=email ) Change subject: Add support for MiTAC Computing Whitestone-2 mainboard ...................................................................... Patch Set 4: Code-Review+2 (1 comment) File src/mainboard/mitaccomputing/whitestone-2/include/sprsp_ws_2_iio.h: https://review.coreboot.org/c/coreboot/+/85532/comment/6e4428df_187628b8?us… : PS4, Line 98: IIO_BIFURCATE_xxxxxx16, : IIO_BIFURCATE_xxx8xxx8, : IIO_BIFURCATE_xxxxxx16, : IIO_BIFURCATE_xxxxxx16, : IIO_BIFURCATE_xxxxxx16, With the `CFG_UPD_PCIE_PORT_DISABLED` macro, it's easy to see how IIO bifurcation correlates to PCIe port settings :D -- To view, visit https://review.coreboot.org/c/coreboot/+/85532?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icf625cf8e9c76ef08411614c15ee43d0c459b905 Gerrit-Change-Number: 85532 Gerrit-PatchSet: 4 Gerrit-Owner: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Reviewer: Angel Pons <angel.pons(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Wilson-MiTACComputing <wilson.chien(a)mitaccomputing.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Mark Chang <mark.chang(a)mitaccomputing.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Angel Pons <angel.pons(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 10:21:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels
by Angel Pons (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Dinesh Gehlot, Jamie Chen, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Tim Crawford. Angel Pons has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add function to force disable memory channels ...................................................................... Patch Set 6: Code-Review+1 (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85529/comment/aa44d63d_90c519b8?us… : PS3, Line 8: > DMI is only a way to ensure that the intended channels were disabled. […] Looking at DMI info is a simple way to show what happens when using the channel disable mask. File src/soc/intel/alderlake/include/soc/meminit.h: https://review.coreboot.org/c/coreboot/+/85529/comment/6d13e061_43c75074?us… : PS6, Line 120: mb_fill_override_channel_mask > you need to write a API expectation in comment section for mb users to follow +1 nit: could we also rename the function? ```suggestion uint8_t mb_get_channel_disable_mask(void); ``` File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/9ec2248f_e342aff6?us… : PS1, Line 264: void memcfg_init(FSPM_UPD *memupd, const struct mb_cfg *mb_cfg, : const struct mem_spd *spd_info, bool half_populated, : uint32_t ch_disable_mask) > Uploaded a new patch. Looks good to me. https://review.coreboot.org/c/coreboot/+/85529/comment/ee027c1a_33575f7a?us… : PS1, Line 315: mem_init_override_channel_mask(mem_cfg, ch_disable_mask); > > Could this be called at the very end of the function? If so, you could export this function (make […] Ack File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/124b029e_4cb5706c?us… : PS6, Line 260: if ((ch_disable_mask & BIT(0)) && : !((ch_disable_mask & 0xf) == (BIT(0) | BIT(1))) : ) { I'm confused about this check. If Mc0Ch0 is disabled, but Mc0Ch0 + Mc0Ch1 are *not* the only disabled channels on Mc0, the configuration is invalid. For the following `ch_disable_mask ---> valid` (considering Mc0 only): - Ch0, Ch1 ---> valid - Ch0, Ch1, Ch3 ---> invalid - Ch2, Ch3 ---> valid - Ch0, Ch2 ---> invalid - Ch1, Ch3 ---> valid - Ch2 ---> valid https://review.coreboot.org/c/coreboot/+/85529/comment/79682a1d_f8bfd998?us… : PS6, Line 269: { > you don't need braces for single statement Sharing some thoughts on this, but I don't have a strong opinion. IIRC the coding style doesn't enforce a preference. I prefer using braces myself but I don't mind either approach during reviews unless it's error-prone, e.g.: ``` while (true) if (true) for (int i = 0; i < 10; i++) foo(); bar(); // some compilers might warn about this likely being a bug ``` There have been bugs in the past caused by missing braces, which is why I prefer using them. https://review.coreboot.org/c/coreboot/+/85529/comment/884f32c4_ef4221d8?us… : PS6, Line 325: mem_init_override_channel_mask(mem_cfg, mb_fill_override_channel_mask()); nit: You can call `mb_fill_override_channel_mask()` inside `mem_init_override_channel_mask()` -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 6 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 10:16:38 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
by Shuo Liu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Tim Chu, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85153?usp=email ) Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 ...................................................................... Patch Set 13: (1 comment) File src/soc/intel/xeon_sp/lpc_gen6.c: https://review.coreboot.org/c/coreboot/+/85153/comment/469e74d5_ee91f04a?us… : PS12, Line 52: BIOS_ERR > Is this an error? Fixed :) -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 13 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 09:57:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
by Shuo Liu (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Hello Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Tim Chu, build bot (Jenkins), yuchi.chen(a)intel.com, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85153?usp=email to look at the new patch set (#13). The following approvals got outdated and were removed: Code-Review+1 by Angel Pons, Code-Review+2 by Lean Sheng Tan, Verified+1 by build bot (Jenkins) Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 ...................................................................... soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 1. Route IRQ for on-chip end-points only (e.g. 00:1f.4 i801_smbus) IRQ routing for devices under root ports needs additional swizzle per decided by root port configurations, which will postponed to later till there is actual usage. 2. Route IRQ based on FSP programmed end-point device ID <-> PIRQ mapping. TESTED=Build and boot on intel/avenuecity CRB Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/soc/intel/xeon_sp/include/soc/irq.h M src/soc/intel/xeon_sp/lpc_gen6.c 2 files changed, 52 insertions(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/85153/13 -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 13 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
by Angel Pons (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85153?usp=email ) Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 ...................................................................... Patch Set 12: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 12 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 09:49:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
by Angel Pons (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Patrick Rudolph, Paul Menzel, Shuo Liu, Tim Chu, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Shuo Liu. ( https://review.coreboot.org/c/coreboot/+/85153?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 ...................................................................... Patch Set 12: (1 comment) File src/soc/intel/xeon_sp/lpc_gen6.c: https://review.coreboot.org/c/coreboot/+/85153/comment/52832ce4_e4a113f6?us… : PS12, Line 52: BIOS_ERR Is this an error? -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 12 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 09:49:22 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Wait for BMC
by Angel Pons (Code Review) 13 Dec '24

13 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Morgan Jang, Patrick Rudolph, Paul Menzel, Shuo Liu, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85492?usp=email ) Change subject: mb/ocp/tiogapass: Wait for BMC ...................................................................... Patch Set 6: Code-Review+2 (2 comments) File src/mainboard/ocp/tiogapass/romstage.c: https://review.coreboot.org/c/coreboot/+/85492/comment/1e5366b2_0744b14b?us… : PS2, Line 60: static const long timeout = 180 * 1000; > Thanks, I have no opens. I guess this would work for now File src/mainboard/ocp/tiogapass/romstage.c: https://review.coreboot.org/c/coreboot/+/85492/comment/d7d96daa_b1a1d4f2?us… : PS3, Line 72: mdelay(100); > Do we need this delay? We're polling a GPIO, it shouldn't matter if we poll it as fast as possible, […] Gone -- To view, visit https://review.coreboot.org/c/coreboot/+/85492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Gerrit-Change-Number: 85492 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Fri, 13 Dec 2024 09:48:53 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Christian Walter <christian.walter(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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