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Change subject: mb/trulo/var/uldrenite: Configure serial_io and I2C
......................................................................
mb/trulo/var/uldrenite: Configure serial_io and I2C
1. Configure serial_io and I2C
2. Add I2C devices
BUG=b:380789023
TEST=emerge-nissa coreboot
Change-Id: I3c1b6028c7e4392a2142851d5fd0199954e2272d
Signed-off-by: John Su <john_su(a)compal.corp-partner.google.com>
---
M src/mainboard/google/brya/Kconfig
M src/mainboard/google/brya/variants/uldrenite/overridetree.cb
2 files changed, 189 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/85581/8
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Change subject: soc/intel/xeon_sp: Merge SKX and CPX
......................................................................
Patch Set 5:
(1 comment)
File src/soc/intel/xeon_sp/cpx/Kconfig:
https://review.coreboot.org/c/coreboot/+/85557/comment/68489919_27256fee?us… :
PS5, Line 5: select SOC_INTEL_XEON_SP_14NM
> GEN1 is SKX, but GEN3 isn't usable. It's CPX and ICX.
@shuo.liu@intel.com isnt CPX gen 2?
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Change subject: soc/intel/xeon_sp: Merge SKX and CPX
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85557/comment/348c4e52_d29be8cf?us… :
PS5, Line 18: TEST: Still boots on ocp/tiogapass.
> Yes, but not sure if we have such a test system.
Delta Lake should be CPX, no idea if we have one though
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Change subject: soc/intel/xeon_sp: Merge SKX and CPX
......................................................................
Patch Set 5:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85557/comment/3f1c43db_2284d577?us… :
PS5, Line 10: - Create a new 14nm folder
> I'm not aware of a name for the group. […]
Agree that 14nm covers SKX and CPX more accurately. But sometimes a gen might use previous gen's code, e.g. SPR uses src/soc/intel/xeon_sp/chip_gen1.c. Maybe we will have both at the moment or any good ideas?
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Change subject: libpayload: Add st_buffer pointer to lib_sysinfo
......................................................................
Set Ready For Review
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Change subject: drivers/self_test/intel_cpu: Add self test submodule for Intel CPU
......................................................................
Patch Set 16:
This change is ready for review.
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Change subject: soc/mediatek/mt8196: Add MMinfra driver support
......................................................................
Patch Set 27:
(3 comments)
File src/soc/mediatek/mt8196/include/soc/addressmap.h:
https://review.coreboot.org/c/coreboot/+/85188/comment/0c1aa1e1_ca15e28d?us… :
PS23, Line 146: VLPCFG_BASE
> Upload a separate patch to rename this to `VLP_CFG_BASE`.
please review on 84929.
https://review.coreboot.org/c/coreboot/+/85188/comment/a48722c5_9b6379b3?us… :
PS23, Line 175:
> tabs
Done
File src/soc/mediatek/mt8196/mminfra.c:
https://review.coreboot.org/c/coreboot/+/85188/comment/f2eaf80a_8c6dae89?us… :
PS26, Line 110: int ret;
:
: /* mminfra0 */
: ret = mtcmos_cb_register(MTCMOS_ID_MM_INFRA0, &mm_infra0_pb_cb);
: if (ret)
: return;
:
: /* mminfra1 */
: ret = mtcmos_cb_register(MTCMOS_ID_MM_INFRA1, &mm_infra1_pb_cb);
: if (ret)
: return;
: }
> ``` […]
Done
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Change subject: soc/mediatek/mt8196: Add MMinfra driver support
......................................................................
soc/mediatek/mt8196: Add MMinfra driver support
MMinfra is the Multimedia Infrastructure. All the Multimedia modules
depend on it. This file adds some initial settings for MMinfra.
Test=Build pass
BUG=b:317009620
Signed-off-by: Xueqi Zhang <xueqi.zhang(a)mediatek.corp-partner.google.com>
Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75
---
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/bootblock.c
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/mminfra.h
A src/soc/mediatek/mt8196/mminfra.c
5 files changed, 160 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/88/85188/27
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Change subject: soc/mediatek/mt8196: Add tracker driver
......................................................................
soc/mediatek/mt8196: Add tracker driver
Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus
timeout occurs, the system reboots and latches some values which could
be used for debug.
Rename VLPCFG_BASE to VLP_CFG_BASE.
TEST=Build pass, When we encounter a bus hang and HW watchdog triggers
a reset to the platform, the tracker will print the
latched information:
[INFO ] **Dump %s aw debug register start**
[INFO ] xxxxxx, 0x1c600000, 0x0, 63
This means that the 63rd entry latch accessing 0x1c600000 has a bus
timeout.
BUG=b:317009620
Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com>
Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298
---
M src/soc/mediatek/mt8196/Makefile.mk
M src/soc/mediatek/mt8196/bootblock.c
M src/soc/mediatek/mt8196/include/soc/addressmap.h
A src/soc/mediatek/mt8196/include/soc/tracker.h
A src/soc/mediatek/mt8196/tracker.c
5 files changed, 175 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/30
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Change subject: soc/intel/xeon_sp: Merge SKX and CPX
......................................................................
Patch Set 5:
(5 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/85557/comment/e94ea908_da7af6ab?us… :
PS5, Line 10: - Create a new 14nm folder
> Is there an Intel name for the "Xeon-SP SPR and CPX" group?
I'm not aware of a name for the group.
Intel naming is broken for CPX and intentionally not used.Intel marketing team named both the 14nm CPX and 10nm ICX the *3rd gen Xeon-SP*. Datasheets contain those names only and no code-names, thus it's hard to tell which is which.
CPX and ICX are very different from silicon POV, while SKX and CPX are very similar.
To prevent confusion we should stay with the 14nm model. It perfectly describes which silicon it refers to.
https://review.coreboot.org/c/coreboot/+/85557/comment/62d2b068_cf760b45?us… :
PS5, Line 18: TEST: Still boots on ocp/tiogapass.
> Should this be boot-tested on CPX too?
Yes, but not sure if we have such a test system.
File src/soc/intel/xeon_sp/14nm/acpi/gpio.asl:
PS5:
> Should we still place the 'acpi' ahead of '14nm (or gen1)' to be consistent?
That's not done for spr either. With this change only common code resides in `src/soc/intel/xeon_sp/acpi`, which makes more sense.
File src/soc/intel/xeon_sp/cpx/Kconfig:
https://review.coreboot.org/c/coreboot/+/85557/comment/9f027e18_f778ee83?us… :
PS5, Line 5: select SOC_INTEL_XEON_SP_14NM
> I don't know what GEN1 and GEN3 correspond to, SKX and CPX respectively?
GEN1 is SKX, but GEN3 isn't usable. It's CPX and ICX.
File src/soc/intel/xeon_sp/skx/Kconfig:
https://review.coreboot.org/c/coreboot/+/85557/comment/32e1bdb2_71ee294b?us… :
PS5, Line 5: select SOC_INTEL_XEON_SP_14NM
> SOC_INTEL_XEON_SP_GEN1?
Doesn't apply to CPX.
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