coreboot-gerrit December 2024

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[M] Change in coreboot[main]: mb/trulo/var/uldrenite: Configure serial_io and I2C
by Kapil Porwal (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Dinesh Gehlot, Dtrain Hsu, Eric Lai, Jayvik Desai, John Su, Nick Vaccaro, Paul Menzel, Subrata Banik. Kapil Porwal has posted comments on this change by John Su. ( https://review.coreboot.org/c/coreboot/+/85581?usp=email ) Change subject: mb/trulo/var/uldrenite: Configure serial_io and I2C ...................................................................... Patch Set 11: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85581?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3c1b6028c7e4392a2142851d5fd0199954e2272d Gerrit-Change-Number: 85581 Gerrit-PatchSet: 11 Gerrit-Owner: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: Jamie Chen <jamie_chen(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Mon, 16 Dec 2024 15:59:08 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: util/crossgcc: Add libstdcxx target
by Raul Rangel (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Felix Singer, Jon Murphy, Karthik Ramasubramanian, Martin L Roth. Raul Rangel has posted comments on this change by Jon Murphy. ( https://review.coreboot.org/c/coreboot/+/85275?usp=email ) Change subject: util/crossgcc: Add libstdcxx target ...................................................................... Patch Set 11: (3 comments) File util/crossgcc/buildgcc: https://review.coreboot.org/c/coreboot/+/85275/comment/dc16fca8_c0f11831?us… : PS11, Line 841: ${EXTRA_ARGS} Can we drop the EXTRA_ARGS and just pass `$@` here? https://review.coreboot.org/c/coreboot/+/85275/comment/f69b6ada_6cf510df?us… : PS11, Line 845: set -- "" : EXTRA_ARGS="$@" Doesn't this set `EXTRA_ARGS=""`? https://review.coreboot.org/c/coreboot/+/85275/comment/86ba139c_7b2c6d16?us… : PS11, Line 867: set -- "--with-gxx-include-dir=\"${LIBSTDCXX_INCLUDE_PATH}/coreboot-${TARGETARCH}/include/\" : --with-sysroot=\"${LIBSTDCXX_INCLUDE_PATH}/\"" : EXTRA_ARGS="$@" : configure_GCC "${EXTRA_ARGS}" ```suggestion configure_GCC --with-gxx-include dir="${LIBSTDCXX_INCLUDE_PATH}/coreboot-${TARGETARCH}/include/" \ --with-sysroot="${LIBSTDCXX_INCLUDE_PATH}/" ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85275?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie0c06ffaeab632c27a992dee8abcc403cceabeed Gerrit-Change-Number: 85275 Gerrit-PatchSet: 11 Gerrit-Owner: Jon Murphy <jpmurphy(a)google.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Jon Murphy <jpmurphy(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 15:52:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Johannes Hahn (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Mario Scheithauer, Uwe Poeche, Werner Zeh. Johannes Hahn has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... Patch Set 3: (2 comments) Patchset: PS3: Done. Commit Message: https://review.coreboot.org/c/coreboot/+/85606/comment/3255ebfa_306b4d94?us… : PS1, Line 14: This is not the case for Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still > `Possible unwrapped commit description (prefer a maximum 72 chars per line)` Please fix. -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 3 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 15:10:59 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Johannes Hahn (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Mario Scheithauer, Uwe Poeche, Werner Zeh. Hello Mario Scheithauer, Uwe Poeche, Werner Zeh, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85606?usp=email to look at the new patch set (#3). Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... soc/intel/common/block/power_limit: Disable RAPL via MSR completely Disabling RAPL via Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS does not turn off RAPL completely (i.d. MMIO & MSR). In the past it was assumed disabling RAPL via MCHBAR is sufficient and the corresponding changes are also reflected in the related MSR (0x610-PACKAGE_POWER_LIMIT). This is not the case for Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still set although PL1 and PL2 were disabled through MCHBAR. Thus Bit[10]-POWER_LIMITATION_STATUS flag can be set in MSR 0x19C (THERM_STATUS) when the power limit of the SKU exceeds. This may lead to a throttling of the domain level frequency. Moreover related parameters within the same MSR (0x610-PACKAGE_POWER_LIMIT) like PKG_PWR_LIM_TIME, PKG_CLMP_LIM, PKG_PWR_LIM have to be cleared as well for both Power Limits (PL1 & PL2). This is due to the fact that these parameters stray in to the system and may effect different system settings. With this commit the PACKAGE_POWER_LIMIT MSR is cleared additionally to the MCHBAR setting when build for ElkhartLake. TEST=Verify MSR(0x610-PACKAGE_POWER_LIMIT) is set to zero during OS runtime except Bit[15]-PKG_PWR_LIM_1_EN (it is known as a bug that this bit will be set to 1 anyway). Moreover using a system stress test tool (e.g. Passmark's BurnInTest) and stressing the system hard should not lead to Bit[10]-POWER_LIMITATION_STATUS flag being set. This is the case when MSR (0x610-PACKAGE_POWER_LIMIT) is not cleared completely and the system is stressed intensively. Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/soc/intel/common/block/power_limit/power_limit.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85606/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 3 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com>

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[XS] Change in coreboot[main]: testcommit for gerrit trigger
by Uwe Poeche (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Uwe Poeche. Uwe Poeche has removed Martin L Roth from this change. ( https://review.coreboot.org/c/coreboot/+/85177?usp=email ) Change subject: testcommit for gerrit trigger ...................................................................... Removed reviewer Martin L Roth <gaumless(a)gmail.com>. -- To view, visit https://review.coreboot.org/c/coreboot/+/85177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: deleteReviewer Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee42fc1e5882972b812fbc1b33bf867c76f767e Gerrit-Change-Number: 85177 Gerrit-PatchSet: 3 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com>

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6
by Lean Sheng Tan (Code Review) 16 Dec '24

16 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85153?usp=email ) Change subject: soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 ...................................................................... soc/intel/xeon_sp: Improve PCI INTx IRQ routing for Gen6 1. Route IRQ for on-chip end-points only (e.g. 00:1f.4 i801_smbus) IRQ routing for devices under root ports needs additional swizzle per decided by root port configurations, which will postponed to later till there is actual usage. 2. Route IRQ based on FSP programmed end-point device ID <-> PIRQ mapping. TESTED=Build and boot on intel/avenuecity CRB Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Signed-off-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85153 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/soc/intel/xeon_sp/include/soc/irq.h M src/soc/intel/xeon_sp/lpc_gen6.c 2 files changed, 52 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/include/soc/irq.h b/src/soc/intel/xeon_sp/include/soc/irq.h index 4d3ad7a..209f699 100644 --- a/src/soc/intel/xeon_sp/include/soc/irq.h +++ b/src/soc/intel/xeon_sp/include/soc/irq.h @@ -6,5 +6,6 @@ #define PCH_IRQ10 10 #define PCH_IRQ11 11 #define PCH_IRQ14 14 +#define PCH_IRQ16 16 #endif /* _SOC_IRQ_H_ */ diff --git a/src/soc/intel/xeon_sp/lpc_gen6.c b/src/soc/intel/xeon_sp/lpc_gen6.c index d4045a8..9455510 100644 --- a/src/soc/intel/xeon_sp/lpc_gen6.c +++ b/src/soc/intel/xeon_sp/lpc_gen6.c @@ -1,9 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <console/console.h> +#include <device/pci.h> +#include <device/pci_ops.h> #include <intelblocks/itss.h> #include <intelblocks/lpc_lib.h> #include <intelblocks/pcr.h> +#include <soc/irq.h> #include <soc/pcr_ids.h> #include <acpi/acpigen.h> @@ -30,15 +33,56 @@ acpigen_write_scope_end(); /* Scope */ } +uint32_t itss_soc_get_on_chip_dev_pir(const struct device *dev) +{ + assert(is_pci(dev)); + return PCI_ITSS_PIR(PCI_SLOT(dev->path.pci.devfn)); +} + +static void soc_itss_route_irq(const struct device *irq_dev, uint8_t int_pin) +{ + uint8_t pirq = itss_get_on_chip_dev_pirq(irq_dev, int_pin); + if (pirq == PIRQ_INVALID) + return; + + uint8_t pirq_rout = pcr_read8(PID_ITSS, + PCR_ITSS_PIRQA_ROUT + pirq_idx(pirq)); + uint8_t int_line = (pirq_rout & 0x80) ? pirq_idx(pirq) + PCH_IRQ16 : pirq_rout & 0xf; + + printk(BIOS_SPEW, "routing irq: dev %s, pin %d, pirq %d, intline %d\n", + dev_path(irq_dev), int_pin, pirq, int_line); + pci_write_config8(irq_dev, PCI_INTERRUPT_LINE, int_line); +} + +static void soc_pch_pirq_init(void) +{ + /* Program irq pin/line for PCI devices using 8259 compatible mode */ + size_t pirq_routes; + const uint8_t *pirq_routing_legacy = lpc_get_pic_pirq_routing(&pirq_routes); + + itss_irq_init(pirq_routing_legacy); + for (int i = 0; i < PIRQ_COUNT; i++) + itss_set_irq_polarity(pirq_routing_legacy[i], 1); + + /* Route irq for end-points */ + struct device *domain = NULL; + while ((domain = dev_find_path(domain, DEVICE_PATH_DOMAIN))) { + struct device *irq_dev = NULL; + while ((irq_dev = dev_bus_each_child(domain->downstream, irq_dev))) { + if (!is_enabled_pci(irq_dev)) + continue; + uint8_t int_pin = pci_read_config8(irq_dev, PCI_INTERRUPT_PIN); + if (int_pin < PCI_INT_A || int_pin > PCI_INT_D) + continue; + + soc_itss_route_irq(irq_dev, int_pin); + } + } +} + void lpc_soc_init(struct device *dev) { printk(BIOS_SPEW, "pch: lpc_init\n"); - /* Program irq pin/line for PCI devices by PCH convention */ - pch_pirq_init(); - - /* Explicitly set polarity low for PIRQA to PIRQH */ - for (int i = 0; i < PIRQ_COUNT; i++) { - itss_set_irq_polarity(pcr_read8(PID_ITSS, PCR_ITSS_PIRQA_ROUT + i), 1); - } + soc_pch_pirq_init(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/85153?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibeb7c8fb3432e5cb240ac3b09c19d2c361e4b45a Gerrit-Change-Number: 85153 Gerrit-PatchSet: 14 Gerrit-Owner: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: testcommit for gerrit trigger
by Uwe Poeche (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Uwe Poeche. Hello build bot (Jenkins), siemens-bot, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85177?usp=email to look at the new patch set (#3). Change subject: testcommit for gerrit trigger ...................................................................... testcommit for gerrit trigger ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa aaaaaaaa Change-Id: Iaee42fc1e5882972b812fbc1b33bf867c76f767e Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/85177/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee42fc1e5882972b812fbc1b33bf867c76f767e Gerrit-Change-Number: 85177 Gerrit-PatchSet: 3 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com>

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[XS] Change in coreboot[main]: testcommit for gerrit trigger
by Uwe Poeche (Code Review) 16 Dec '24

16 Dec '24

Uwe Poeche has removed Martin L Roth from this change. ( https://review.coreboot.org/c/coreboot/+/85177?usp=email ) Change subject: testcommit for gerrit trigger ...................................................................... Removed reviewer Martin L Roth <gaumless(a)gmail.com>. -- To view, visit https://review.coreboot.org/c/coreboot/+/85177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: deleteReviewer Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee42fc1e5882972b812fbc1b33bf867c76f767e Gerrit-Change-Number: 85177 Gerrit-PatchSet: 2 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot

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[XS] Change in coreboot[main]: testcommit for gerrit trigger
by Uwe Poeche (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Uwe Poeche. Hello build bot (Jenkins), siemens-bot, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85177?usp=email to look at the new patch set (#2). Change subject: testcommit for gerrit trigger ...................................................................... testcommit for gerrit trigger ddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddddd aaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaaa Change-Id: Iaee42fc1e5882972b812fbc1b33bf867c76f767e Signed-off-by: Uwe Poeche <uwe.poeche(a)siemens.com> --- M Makefile 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/85177/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85177?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaee42fc1e5882972b812fbc1b33bf867c76f767e Gerrit-Change-Number: 85177 Gerrit-PatchSet: 2 Gerrit-Owner: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Johannes Hahn (Code Review) 16 Dec '24

16 Dec '24

Johannes Hahn has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... soc/intel/common/block/power_limit: Disable RAPL via MSR completely Disabling RAPL via Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS does not turn off RAPL completely (i.d. MMIO & MSR). In the past it was assumed disabling RAPL via MCHBAR is sufficient and the corresponding changes are also reflected in the related MSR (0x610 - PACKAGE_POWER_LIMIT). This is not the case for Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still set although PL1 and PL2 were disabled through MCHBAR. Thus Bit[10]-POWER_LIMITATION_STATUS flag can be set in MSR 0x19C (THERM_STATUS) when the power limit of the SKU exceeds. This may lead to a throttling of the domain level frequency. Moreover related parameters within the same MSR (0x610-PACKAGE_POWER_LIMIT) like PKG_PWR_LIM_TIME, PKG_CLMP_LIM, PKG_PWR_LIM have to be cleared as well for both Power Limits (PL1 & PL2). This is due to the fact that these parameters stray in to the system and may effect different system settings. With this commit the PACKAGE_POWER_LIMIT MSR is cleared additionally to the MCHBAR setting when build for ElkhartLake. TEST=Verify MSR(0x610-PACKAGE_POWER_LIMIT) is set to zero during OS runtime except Bit[15]-PKG_PWR_LIM_1_EN (it is known as a bug that this bit will be set to 1 anyway). Moreover using a system stress test tool (e.g. Passmark's BurnInTest) and stressing the system hard should not lead to Bit[10]-POWER_LIMITATION_STATUS flag being set. This is the case when MSR (0x610-PACKAGE_POWER_LIMIT) is not cleared completely and the system is stressed intensively. Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/soc/intel/common/block/power_limit/power_limit.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85606/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 2 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org>

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coreboot-gerrit December 2024