coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

1 participants
3018 discussions

[L] Change in coreboot[main]: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake)
by Name of user not set (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Alicja Michalska. Name of user not set #1004406 has posted comments on this change by Name of user not set #1004406. ( https://review.coreboot.org/c/coreboot/+/65225?usp=email ) Change subject: mb/asrock: Add ASRock H370m-ITX support (Coffee Lake) ...................................................................... Patch Set 20: (3 comments) File src/mainboard/asrock/h370m/devicetree.cb: https://review.coreboot.org/c/coreboot/+/65225/comment/eb7f2b35_50e2f5b2?us… : PS20, Line 6: register "s0ix_enable" = "1" > Try disabling it, platform might suspend correctly if you use S3 state instead you are right. removing s0ix_enable and setting PchPmSlpS3* result in a correct sleep down. but the system doesnt wake up correctly. keyboard doesnt trigger wakeup and power button will result in a broken state. https://review.coreboot.org/c/coreboot/+/65225/comment/c7370f34_22f3d1f3?us… : PS20, Line 14: device ref igpu on end > Did you forget to include DDI configuration? […] i have no igpu. is this still possible? https://review.coreboot.org/c/coreboot/+/65225/comment/ff600920_b47edeb4?us… : PS20, Line 115: device ref lpc_espi on > You can obtain a copy of datasheet for SuperIO from Nuvoton if you send them an email. […] thanks for that information. i will contact nuvoton. a NCT5567D-B is used here but it seems that the ID is identical to the NCT5539D. -- To view, visit https://review.coreboot.org/c/coreboot/+/65225?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79302247311471153ebbba991081365d9265791b Gerrit-Change-Number: 65225 Gerrit-PatchSet: 20 Gerrit-Owner: Name of user not set #1004406 Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 14:23:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Alicja Michalska <ahplka19(a)gmail.com>

1 0

[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Johannes Hahn (Code Review) 16 Dec '24

16 Dec '24

Johannes Hahn has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... soc/intel/common/block/power_limit: Disable RAPL via MSR completely Disabling RAPL via Kconfig switch SOC_INTEL_DISABLE_POWER_LIMITS does not turn off RAPL completely (i.d. MMIO & MSR). In the past it was assumed disabling RAPL via MCHBAR is sufficient and the corresponding changes are also reflected in the related MSR (0x610 - PACKAGE_POWER_LIMIT). This is not the case for Power Limit 2 (PL2) because Bit[47]-PKG_PWR_LIM_2_EN is still set although PL1 and PL2 were disabled through MCHBAR. Thus Bit[10]-POWER_LIMITATION_STATUS flag can be set in MSR 0x19C (THERM_STATUS) when the power limit of the SKU exceeds. This may lead to a throttling of the domain level frequency. Moreover related parameters within the same MSR (0x610-PACKAGE_POWER_LIMIT) like PKG_PWR_LIM_TIME, PKG_CLMP_LIM, PKG_PWR_LIM have to be cleared as well for both Power Limits (PL1 & PL2). This is due to the fact that these parameters stray in to the system and may effect different system settings. With this commit the PACKAGE_POWER_LIMIT MSR is cleared additionally to the MCHBAR setting when build for ElkhartLake. TEST=Verify MSR(0x610-PACKAGE_POWER_LIMIT) is set to zero during OS runtime except Bit[15]-PKG_PWR_LIM_1_EN (it is known as a bug that this bit will be set to 1 anyway). Moreover using a system stress test tool (e.g. Passmark's BurnInTest) and stressing the system hard should not lead to Bit[10]-POWER_LIMITATION_STATUS flag being set. This is the case when MSR (0x610-PACKAGE_POWER_LIMIT) is not cleared completely and the system is stressed intensively. Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Signed-off-by: Johannes Hahn <johannes-hahn(a)siemens.com> --- M src/soc/intel/common/block/power_limit/power_limit.c 1 file changed, 8 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/06/85606/1 diff --git a/src/soc/intel/common/block/power_limit/power_limit.c b/src/soc/intel/common/block/power_limit/power_limit.c index b5fbe89..c81ddbb 100644 --- a/src/soc/intel/common/block/power_limit/power_limit.c +++ b/src/soc/intel/common/block/power_limit/power_limit.c @@ -91,6 +91,14 @@ MCHBAR32(MCH_PKG_POWER_LIMIT_LO) = value & ~(PKG_POWER_LIMIT_EN); value = MCHBAR32(MCH_PKG_POWER_LIMIT_HI); MCHBAR32(MCH_PKG_POWER_LIMIT_HI) = value & ~(PKG_POWER_LIMIT_EN); + /* Elkhartlake SoC does not shadow PKG_POWER_LIMIT MCHBAR settings + * to MSR correctly */ + if (CONFIG(SOC_INTEL_ELKHARTLAKE)) { + msr = rdmsr(MSR_PKG_POWER_LIMIT); + msr.hi = 0; + msr.lo = 0; + wrmsr(MSR_PKG_POWER_LIMIT, msr); + } } else { msr = rdmsr(MSR_PKG_POWER_LIMIT); msr.lo &= ~PKG_POWER_LIMIT_EN; -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 1 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com>

1 0

[S] Change in coreboot[main]: soc/intel/xeon_sp/spr/acpi: Fix regression
by Patrick Rudolph (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Angel Pons, Christian Walter, Johnny Lin, Jonathan Zhang, Shuo Liu, Tim Chu. Patrick Rudolph has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85562?usp=email ) Change subject: soc/intel/xeon_sp/spr/acpi: Fix regression ...................................................................... Patch Set 4: (1 comment) File src/soc/intel/xeon_sp/spr/acpi/uncore.asl: https://review.coreboot.org/c/coreboot/+/85562/comment/7ccb716f_74b20861?us… : PS3, Line 15: #define SOCKET_NAME 0 > +1, or use `SOCKET * 2`? Arithmetic expression are not evaluated by the preprocessor, nor iasl. -- To view, visit https://review.coreboot.org/c/coreboot/+/85562?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ice168bdebc46dc0cfb9c63c78c46a5d9ff2b7658 Gerrit-Change-Number: 85562 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 14:06:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

1 0

[S] Change in coreboot[main]: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1]
by Ana Carolina Cabral (Code Review) 16 Dec '24

16 Dec '24

Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/85498?usp=email ) Change subject: mb/amb/birman*/gpio: remove configuration for VDD_MEM_VID[0,1] ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85498/comment/b3f2a480_fd81b2d5?us… : PS4, Line 9: Fix VDD_MEM_VID[0,1] pin assignments that was causing boot issues. > It’d be great if you explained the issue with ABL, mentioned in the comments. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85498?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie5634575aff6dad210928c9c9af808e245322b99 Gerrit-Change-Number: 85498 Gerrit-PatchSet: 4 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Comment-Date: Mon, 16 Dec 2024 13:28:49 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[M] Change in coreboot[main]: drivers/amd/nova: Add Nova Card common driver
by Ana Carolina Cabral (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Anand Vaikar, Paul Menzel. Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84776?usp=email ) Change subject: drivers/amd/nova: Add Nova Card common driver ...................................................................... Patch Set 7: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84776/comment/861e87c5_1d208539?us… : PS5, Line 7: directory > As you add more than the directory, maybe just write “common driver”? Done https://review.coreboot.org/c/coreboot/+/84776/comment/00014807_f2dbd1a4?us… : PS5, Line 9: As multiple boards use the NOVA daughter card, the function that detects : the connector type has been moved to the drivers folder and : will be refactored in the soc path in the following patches. > This looks a little strange. Maybe also re-flow the second and third line. Done File src/drivers/amd/nova/Kconfig: https://review.coreboot.org/c/coreboot/+/84776/comment/6495ef10_4c60e0cd?us… : PS5, Line 4: def_bool n > will this be enabled via defconfig? It can be, I wasn`t sure if all mainboards have a nova card File src/drivers/amd/nova/nova_card.c: https://review.coreboot.org/c/coreboot/+/84776/comment/d815d4fc_6fdfd515?us… : PS5, Line 24: uint16_t connector_type = data[1] | data[0] << 8; > > `please, no spaces at the start of a line` […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e9ded2090d6a5865e3330408f490e59fbf480f4 Gerrit-Change-Number: 84776 Gerrit-PatchSet: 7 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 13:26:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Anand Vaikar <a.vaikar2021(a)gmail.com>

1 0

[M] Change in coreboot[main]: drivers/amd/nova: Add Nova Card common driver
by Ana Carolina Cabral (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Ana Carolina Cabral. Hello Felix Held, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84776?usp=email to look at the new patch set (#7). Change subject: drivers/amd/nova: Add Nova Card common driver ...................................................................... drivers/amd/nova: Add Nova Card common driver As multiple boards use the NOVA daughter card, a common driver is created with the function that detects the connector type. The following patches remove the duplicate code for this function used on each amd/mb path. Change-Id: I5e9ded2090d6a5865e3330408f490e59fbf480f4 Signed-off-by: Ana Carolina Cabral <ana.cpmelo95(a)gmail.com> --- M Makefile.mk A src/drivers/amd/nova/Kconfig A src/drivers/amd/nova/Makefile.mk A src/drivers/amd/nova/chip.h A src/drivers/amd/nova/nova_card.c 5 files changed, 68 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/84776/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/84776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e9ded2090d6a5865e3330408f490e59fbf480f4 Gerrit-Change-Number: 84776 Gerrit-PatchSet: 7 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-CC: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Ana Carolina Cabral

1 0

[XL] Change in coreboot[main]: drivers/option: Add forms in cbtables
by Lean Sheng Tan (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Angel Pons, Benjamin Doron, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Sean Rhodes. Lean Sheng Tan has uploaded a new patch set (#27) to the change originally created by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/74121?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: drivers/option: Add forms in cbtables ...................................................................... drivers/option: Add forms in cbtables Introduce a mechanism so that coreboot can provide a list of options to post-coreboot code. The options are grouped together into forms and have a meaning name and optional help text. This can be used to let payloads know which options should be displayed in a setup menu, for instance. Although this system was written to be used with edk2, it has been designed with flexibility in mind so that other payloads can also make use of this mechanism. The system currently lacks a way to describe where to find option values. This information is stored in a set of data structures specifically created for this purpose. This format is known as CFR, which means "coreboot forms representation" or "cursed forms representation". Although the "forms representation" is borrowed from UEFI, CFR can be used in non-UEFI scenarios as well. The data structures are implemented as an extension of cbtables records to support nesting. It should not break backwards compatibility because the CFR root record (LB_TAG_CFR_ROOT) size includes all of its children records. The concept of record nesting is borrowed from the records for CMOS options. It is not possible to reuse the CMOS records because they are too closely coupled with CMOS options; using these structures would needlessly restrict more capable backends to what can be done with CMOS options, which is undesired. Because CFR supports variable-length components, directly transforming options into CFR structures is not a trivial process. Furthermore, CFR structures need to be written in one go. Because of this, abstractions exist to generate CFR structures from a set of "setup menu" structures that are coreboot-specific and could be integrated with the devicetree at some point. Note that `struct sm_object` is a tagged union. This is used to have lists of options in an array, as building linked lists of options at runtime is extremely impractical because options would have to be added at the end of the linked list to maintain option order. To avoid mistakes defining `struct sm_object` values, helper macros exist for supported option types. The macros also provide some type checking as they initialise specific union members. It should be possible to extend CFR support for more sophisticated options like fan curve points. Feedback about this is highly appreciated. Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Signed-off-by: Angel Pons <th3fanbus(a)gmail.com> --- A Documentation/drivers/cfr.md A Documentation/drivers/cfr_internal.md M Documentation/drivers/index.md A src/commonlib/include/commonlib/cfr.h M src/commonlib/include/commonlib/coreboot_tables.h A src/drivers/option/Kconfig A src/drivers/option/Makefile.mk A src/drivers/option/cfr.c A src/drivers/option/cfr_frontend.h M src/include/boot/coreboot_tables.h M src/lib/coreboot_table.c M src/lib/program.ld 12 files changed, 1,105 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/74121/27 -- To view, visit https://review.coreboot.org/c/coreboot/+/74121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 27 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Christian Walter <christian.walter(a)9elements.com> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com>

1 0

[M] Change in coreboot[main]: soc/intel/alderlake: Add function to force disable memory channels
by Angel Pons (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Christian Walter, Dinesh Gehlot, Eric Lai, Jayvik Desai, Jeremy Soller, Kapil Porwal, Lean Sheng Tan, Michał Kopeć, Michał Żygowski, Nick Vaccaro, Paul Menzel, Piotr Król, Sean Rhodes, Subrata Banik, Tim Crawford. Angel Pons has posted comments on this change by Kapil Porwal. ( https://review.coreboot.org/c/coreboot/+/85529?usp=email ) Change subject: soc/intel/alderlake: Add function to force disable memory channels ...................................................................... Patch Set 7: (1 comment) File src/soc/intel/alderlake/meminit.c: https://review.coreboot.org/c/coreboot/+/85529/comment/faabea48_89821291?us… : PS1, Line 252: if (ch_disable_mask == 0) { > Per my test, the four combinations are valid. […] Are these combinations valid? - Mc0Ch1 - Mc0Ch3 I wonder if the channels are grouped in pairs (0+1 and 2+3), and the first channel of a group must be enabled if the group is in use. -- To view, visit https://review.coreboot.org/c/coreboot/+/85529?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibfeca4509cb3d88bc1bac2ac2d480e665d895bc5 Gerrit-Change-Number: 85529 Gerrit-PatchSet: 7 Gerrit-Owner: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Frank Wu <frank_wu(a)compal.corp-partner.google.com> Gerrit-CC: John Su <john_su(a)compal.corp-partner.google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 12:12:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Jamie Chen <jamie.chen(a)intel.corp-partner.google.com> Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Kapil Porwal <kapilporwal(a)google.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

1 0

[L] Change in coreboot[main]: soc/intel/xeon_sp: Merge SKX and CPX
by Shuo Liu (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85557?usp=email ) Change subject: soc/intel/xeon_sp: Merge SKX and CPX ...................................................................... Patch Set 5: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85557/comment/e47993da_6c4932bf?us… : PS5, Line 10: - Create a new 14nm folder > Agree that 14nm covers SKX and CPX more accurately. […] At a second thought, maybe we could accept both - SKX/CPX common codes in 14nm folder, while other gen's common codes laid flatly in xeon_sp top directory. It would be helpful to have a README.md in 14nm folder to specify the background of the naming. File src/soc/intel/xeon_sp/cpx/Kconfig: https://review.coreboot.org/c/coreboot/+/85557/comment/8ba9e574_cfa97310?us… : PS5, Line 5: select SOC_INTEL_XEON_SP_14NM > @shuo.liu@intel. […] CPX is gen3. -- To view, visit https://review.coreboot.org/c/coreboot/+/85557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I915d502efc36b299e089158c60e81822dfa2b333 Gerrit-Change-Number: 85557 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 12:05:27 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com>

1 0

[M] Change in coreboot[main]: soc/mediatek/mt8196: Add MMinfra driver support
by Yidi Lin (Code Review) 16 Dec '24

16 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85188?usp=email ) Change subject: soc/mediatek/mt8196: Add MMinfra driver support ...................................................................... Patch Set 27: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85188?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie86f141a0957fc60d4973875c0dbcbdb57be1f75 Gerrit-Change-Number: 85188 Gerrit-PatchSet: 27 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Mon, 16 Dec 2024 12:00:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

Jump to page:

2025

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit December 2024