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Change subject: util/crossgcc: Add libstdcxx target
......................................................................
Patch Set 12:
(4 comments)
File util/crossgcc/buildgcc:
https://review.coreboot.org/c/coreboot/+/85275/comment/e03cad19_3da219ba?us… :
PS12, Line 840: $@
```suggestion
"$@"
```
https://review.coreboot.org/c/coreboot/+/85275/comment/e47231c5_55557708?us… :
PS12, Line 844: configure_GCC
The script isn't running with `-e`, so we need to chain the commands.
```suggestion
configure_GCC && \
```
https://review.coreboot.org/c/coreboot/+/85275/comment/19f4ec2d_b8c942ad?us… :
PS12, Line 864: configure_GCC "--with-gxx-include-dir=\"${LIBSTDCXX_INCLUDE_PATH}/coreboot-${TARGETARCH}/include/\"
: --with-sysroot=\"${LIBSTDCXX_INCLUDE_PATH}/\""
```suggestion
configure_GCC \
--with-gxx-include-dir="${LIBSTDCXX_INCLUDE_PATH}/coreboot-${TARGETARCH}/include/" \
--with-sysroot="${LIBSTDCXX_INCLUDE_PATH}/" && \
```
https://review.coreboot.org/c/coreboot/+/85275/comment/af2ec73e_2cf529e5?us… :
PS12, Line 870: || touch .failed
You don't want to build libstdc++ if libgcc failed.
```suggestion
$MAKE install-target-libgcc DESTDIR=$DESTDIR && \
```
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Alicja Michalska has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/85609?usp=email )
Change subject: mb/topton/adl: Disable mapped SATA port
......................................................................
mb/topton/adl: Disable mapped SATA port
According to Intel mFIT tool, SATA Port 0 is mapped as RP11 (PCI-E).
Disable SATA mapping on that port.
Change-Id: I9556383952d163a145ac73cb846740a4ce67a1e1
Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com>
---
M src/mainboard/topton/adl/devicetree.cb
M src/mainboard/topton/adl/gpio.h
2 files changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/85609/2
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Hello Felix Singer, Karthik Ramasubramanian, Martin L Roth, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/85275?usp=email
to look at the new patch set (#12).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: util/crossgcc: Add libstdcxx target
......................................................................
util/crossgcc: Add libstdcxx target
Add target for building libstdcxx for a cross compile target using the
GCC source downloaded for a cross compiler build and linking against a
specified libc implementation.
BUG=NONE
TEST=Build libstdc++ for cross compilers, link against generated library
./util/crossgcc/buildgcc -t -p arm-eabi -P libstdcxx -l c,c++ -j128 \
--libstdcxx_include /tmp/picolibc
Change-Id: Ie0c06ffaeab632c27a992dee8abcc403cceabeed
Signed-off-by: Jon Murphy <jpmurphy(a)google.com>
---
M util/crossgcc/.gitignore
M util/crossgcc/buildgcc
2 files changed, 40 insertions(+), 6 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/85275/12
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Change subject: util/crossgcc: Add libstdcxx target
......................................................................
Patch Set 11:
(3 comments)
File util/crossgcc/buildgcc:
https://review.coreboot.org/c/coreboot/+/85275/comment/6298449f_d4adf191?us… :
PS11, Line 841: ${EXTRA_ARGS}
> Can we drop the EXTRA_ARGS and just pass `$@` here?
Done
https://review.coreboot.org/c/coreboot/+/85275/comment/361261d7_c91f4660?us… :
PS11, Line 845: set -- ""
: EXTRA_ARGS="$@"
> Doesn't this set `EXTRA_ARGS=""`?
Yes, was trying to keep the style aligned between functions
https://review.coreboot.org/c/coreboot/+/85275/comment/ff7b0c5a_95a579b1?us… :
PS11, Line 867: set -- "--with-gxx-include-dir=\"${LIBSTDCXX_INCLUDE_PATH}/coreboot-${TARGETARCH}/include/\"
: --with-sysroot=\"${LIBSTDCXX_INCLUDE_PATH}/\""
: EXTRA_ARGS="$@"
: configure_GCC "${EXTRA_ARGS}"
> ```suggestion […]
Done
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Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85609?usp=email )
Change subject: mb/topton/adl: Disable mapped SATA port
......................................................................
mb/topton/adl: Disable mapped SATA port
According to Intel mFIT tool, SATA Port 0 is mapped as RP11 (PCI-E).
Disable SATA mapping on that port.
Change-Id: I9556383952d163a145ac73cb846740a4ce67a1e1
Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com>
---
M src/mainboard/topton/adl/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/09/85609/1
diff --git a/src/mainboard/topton/adl/devicetree.cb b/src/mainboard/topton/adl/devicetree.cb
index f21687a..216589d 100644
--- a/src/mainboard/topton/adl/devicetree.cb
+++ b/src/mainboard/topton/adl/devicetree.cb
@@ -44,9 +44,9 @@
device ref shared_sram on end
# Not working, resource conflict(?)
+ # Port 0 is configured as PCI-E in FIT (RP11)
device ref sata on
register "sata_ports_enable" = "{
- [0] = 1,
[1] = 1,
}"
end
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Change subject: util/intelp2m: Drop non-DWx register analysis support
......................................................................
Patch Set 19: Code-Review+2
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