coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/topton/adl: Disable mapped SATA port
by Alicja Michalska (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Felix Singer. Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/85609?usp=email ) Change subject: mb/topton/adl: Disable mapped SATA port ...................................................................... Patch Set 3: (1 comment) Patchset: PS2: > We use the hashtag field for marking patches supposed to be included in the release. […] Thanks, been looking for it :) -- To view, visit https://review.coreboot.org/c/coreboot/+/85609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9556383952d163a145ac73cb846740a4ce67a1e1 Gerrit-Change-Number: 85609 Gerrit-PatchSet: 3 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Comment-Date: Tue, 17 Dec 2024 03:09:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: mb/topton/adl: Enable TPM
by Alicja Michalska (Code Review) 17 Dec '24

17 Dec '24

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85611?usp=email ) Change subject: mb/topton/adl: Enable TPM ...................................................................... mb/topton/adl: Enable TPM Enable TPM2 (Intel fTPM/PTT). Change-Id: If1a52cacf2eeef68efdd98c48d5802712305f354 Signed-off-by: Alicja Michalska <alicja.michalska(a)9elements.com> --- M src/mainboard/topton/adl/Kconfig M src/mainboard/topton/adl/devicetree.cb 2 files changed, 5 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/85611/1 diff --git a/src/mainboard/topton/adl/Kconfig b/src/mainboard/topton/adl/Kconfig index 94cd222..df8a513 100644 --- a/src/mainboard/topton/adl/Kconfig +++ b/src/mainboard/topton/adl/Kconfig @@ -13,6 +13,8 @@ select SOC_INTEL_ALDERLAKE_PCH_N select INTEL_GMA_HAVE_VBT select SOC_INTEL_COMMON_BLOCK_HDA_VERB + select HAVE_INTEL_PTT + select CRB_TPM config MAINBOARD_DIR default "topton/adl" diff --git a/src/mainboard/topton/adl/devicetree.cb b/src/mainboard/topton/adl/devicetree.cb index 216589d..da53c73 100644 --- a/src/mainboard/topton/adl/devicetree.cb +++ b/src/mainboard/topton/adl/devicetree.cb @@ -121,5 +121,8 @@ register "pch_hda_idisp_link_frequency" = "HDA_LINKFREQ_96MHZ" register "pch_hda_idisp_link_tmode" = "HDA_TMODE_8T" end + chip drivers/crb + device mmio 0xfed40000 on end + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/85611?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If1a52cacf2eeef68efdd98c48d5802712305f354 Gerrit-Change-Number: 85611 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com>

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[M] Change in coreboot[main]: cpu/x86/topology: Simplify CPU topology initialization
by Jincheng Li (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Ronak Kanabar, Tim Chu. Jincheng Li has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85576?usp=email ) Change subject: cpu/x86/topology: Simplify CPU topology initialization ...................................................................... Patch Set 4: Code-Review+1 (1 comment) File src/cpu/x86/topology.c: https://review.coreboot.org/c/coreboot/+/85576/comment/bb85c67a_d30330a4?us… : PS4, Line 89: level = CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs); There got double MACRO CPUID_CPU_TOPOLOGY_LEVEL call nearly, not sure if it is good to combine them ?(e.g. if (level != LEVEL_TYPE_SMT return;)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9424559f895af69e79c36b919e80af803861148 Gerrit-Change-Number: 85576 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 03:08:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: cpu/x86/topology: Simplify CPU topology initialization
by Shuo Liu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Jérémy Compostella, Lean Sheng Tan, Patrick Rudolph, Ronak Kanabar, Tim Chu. Shuo Liu has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85576?usp=email ) Change subject: cpu/x86/topology: Simplify CPU topology initialization ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Double check on GNR, no issue either. -- To view, visit https://review.coreboot.org/c/coreboot/+/85576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9424559f895af69e79c36b919e80af803861148 Gerrit-Change-Number: 85576 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 03:04:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Yidi Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Yu-Ping Wu. Yidi Lin has posted comments on this change by Ccong Chen. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... Patch Set 2: (5 comments) File src/soc/mediatek/common/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/d5d89e0e_4c93ea4c?us… : PS1, Line 59: #ifndef CONFIG_MEDIATEK_SPM_V2 > In 8196 SOC design, this part has been simplified, no need the part of setting No done https://review.coreboot.org/c/coreboot/+/85599/comment/8a38da6b_d3470a82?us… : PS1, Line 101: CONFIG_MEDIATEK_SPM_V2 > 8196 have not the register setting not done File src/soc/mediatek/mt8196/include/soc/spm.h: https://review.coreboot.org/c/coreboot/+/85599/comment/2fdbf6e7_cb866c99?us… : PS2, Line 87: #define AP_WDT_TIMEOUT_SUSPEND_S Are you saying that the time unit is second ? File src/soc/mediatek/mt8196/include/soc/spm.h: https://review.coreboot.org/c/coreboot/+/85599/comment/bf5b9719_634496e2?us… : PS1, Line 85: PCM_WDT_TIMEOUT > Done Not done. You don't even mention anything. File src/soc/mediatek/mt8196/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/ed3eb7ed_71c427d5?us… : PS1, Line 861: SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | > align line742 ? align with first param. -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 2 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 02:58:08 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com> Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Ccong Chen (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Ccong Chen has posted comments on this change by Ccong Chen. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... Patch Set 2: (42 comments) File src/soc/mediatek/common/Kconfig: https://review.coreboot.org/c/coreboot/+/85599/comment/8fa0a2ab_cb969395?us… : PS1, Line 122: spm version2 > SPM version 2 Done File src/soc/mediatek/common/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/ec1bc60a_6d18de24?us… : PS1, Line 59: #ifndef CONFIG_MEDIATEK_SPM_V2 > if (!CONFIG(MEDIATEK_SPM_V2)) […] In 8196 SOC design, this part has been simplified, no need the part of setting https://review.coreboot.org/c/coreboot/+/85599/comment/2e83276c_5c201551?us… : PS1, Line 71: /* In the new SOC design, this part has been simplified */ > Remove this comment (same below). […] Done https://review.coreboot.org/c/coreboot/+/85599/comment/87a8e788_e5da0653?us… : PS1, Line 101: CONFIG_MEDIATEK_SPM_V2 > if (!CONFIG(MEDIATEK_SPM_V2)) 8196 have not the register setting File src/soc/mediatek/mt8196/include/soc/addressmap.h: https://review.coreboot.org/c/coreboot/+/85599/comment/8ff3e614_2f25cd57?us… : PS1, Line 146: SCP_BASE > Just use `SPM_BASE`. Also see CB:85521. Done File src/soc/mediatek/mt8196/include/soc/pll.h: https://review.coreboot.org/c/coreboot/+/85599/comment/b9efee56_fbbfdbda?us… : PS1, Line 140: _0 > Why `_0`? How many config registers do we have? If we have 8, please write `clk_scp_cfg[8]` here and […] Done File src/soc/mediatek/mt8196/include/soc/spm.h: https://review.coreboot.org/c/coreboot/+/85599/comment/5234fbb1_b1a64f02?us… : PS1, Line 508: u32 spm_power_on_val[4]; > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/52ea792e_9151df29?us… : PS1, Line 535: u32 md32pcm_scu_ctrl[4]; > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/c1978c0a_a279970a?us… : PS1, Line 562: u32 sw2spm_mailbox[4]; : u32 spm2sw_mailbox[4]; : > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/217ced40_ec0b3bea?us… : PS1, Line 575: u32 pcm_apwdt_latch[20]; > Keep it unmodified. apwdt register address have been changed https://review.coreboot.org/c/coreboot/+/85599/comment/c2ad26e5_5ed6606a?us… : PS1, Line 591: u32 spm_dpsw_con; > Keep it unmodified. spm_dpsw_con register address have been changed https://review.coreboot.org/c/coreboot/+/85599/comment/f718cffb_fa313d79?us… : PS1, Line 645: struct { : u32 latch_l; : u32 latch_h; : } sys_timer_latch[16]; > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/7777a265_89495105?us… : PS1, Line 654: u32 pcm_apwdt_latch_20[19]; : u8 reserved18[4]; > Keep it unmodified. The register address have been changed https://review.coreboot.org/c/coreboot/+/85599/comment/2bc4c3d4_9c372456?us… : PS1, Line 660: u32 spm_sw_rsv[9]; > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/06fbde08_68529c83?us… : PS1, Line 684: u32 spm_sema_m[8]; > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/193e8568_2d2614eb?us… : PS1, Line 687: u32 spm2pmcu_mailbox[4]; : u32 pmcu2spm_mailbox[4]; > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/4320a50f_9aebf46b?us… : PS1, Line 704: u32 spm_src_mask[12]; : u32 spm_req_sta[12]; > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/b3fae9a8_141dbf2f?us… : PS1, Line 710: u32 spm_resource_ack_con[2]; : u32 spm_resource_ack_mask[9]; > Keep it unmodified. Done https://review.coreboot.org/c/coreboot/+/85599/comment/34773737_525b264b?us… : PS1, Line 12: 0x10001060 > `(INFRACFG_AO_BASE + ... […] Done https://review.coreboot.org/c/coreboot/+/85599/comment/4f9ddc21_c0353fee?us… : PS1, Line 13: 0x1c001108 > Should we define a structure for `VLPCFG_BASE`? Done https://review.coreboot.org/c/coreboot/+/85599/comment/dde1e689_d7752042?us… : PS1, Line 69: 0x003FFE20 > Keep it lower case in this patch. We should change all of these to upper case in a separate patch. Done https://review.coreboot.org/c/coreboot/+/85599/comment/24e3c5cc_5b711fa6?us… : PS1, Line 85: PCM_WDT_TIMEOUT > What's the unit? Done https://review.coreboot.org/c/coreboot/+/85599/comment/dbd8a44e_81308a84?us… : PS1, Line 87: AP_WDT_TIMEOUT_SUSPEND > Append unit such as `_MS`. Done https://review.coreboot.org/c/coreboot/+/85599/comment/11cbc625_198f1484?us… : PS1, Line 635: u32 reserved0[5]; > Revert these unrelated changes. Done https://review.coreboot.org/c/coreboot/+/85599/comment/c5f4e386_cb655e66?us… : PS1, Line 717: [1] > remove `[1]` Done https://review.coreboot.org/c/coreboot/+/85599/comment/43dcd639_48ee9ec0?us… : PS1, Line 968: u32 spm_src_mask_17; : u32 spm_src_mask_18; : u32 spm_resource_ack_mask_13; : u32 spm_resource_ack_mask_14; > The offsets are varied previous version. Please make sure the offsets are correct. Yes, it's correct File src/soc/mediatek/mt8196/spm.c: https://review.coreboot.org/c/coreboot/+/85599/comment/1606eba1_4182ff59?us… : PS1, Line 10: > one space only Done https://review.coreboot.org/c/coreboot/+/85599/comment/b573960b_a080a024?us… : PS1, Line 17: > remove extra blank lnie. Done https://review.coreboot.org/c/coreboot/+/85599/comment/e993c015_41857bc7?us… : PS1, Line 26: /* TODO: replace with common regs structure if they have been defined */ > Remove this comment if common structures are not defined already. Done https://review.coreboot.org/c/coreboot/+/85599/comment/4f8aa46a_e255b7a9?us… : PS1, Line 731: ( > remove Done https://review.coreboot.org/c/coreboot/+/85599/comment/6c0373bc_e0d5d66a?us… : PS1, Line 735: ( > remove Done https://review.coreboot.org/c/coreboot/+/85599/comment/1f0eca4d_a8f00b53?us… : PS1, Line 738: en > Do you mean `enable`? Done https://review.coreboot.org/c/coreboot/+/85599/comment/36a28fd2_b3973d91?us… : PS1, Line 738: status > Remove if not used. Done https://review.coreboot.org/c/coreboot/+/85599/comment/e9669879_7fca4d96?us… : PS1, Line 738: int > bool Done https://review.coreboot.org/c/coreboot/+/85599/comment/89b2f24f_529516b7?us… : PS1, Line 740: unsigned int > u32 Done https://review.coreboot.org/c/coreboot/+/85599/comment/353b16fb_93328b5f?us… : PS1, Line 743: clrbits32(&mtk_spm->spm_ack_chk_con_3, SPM_ACK_CHK_3_CON_CLR_ALL); : setbits32(&mtk_spm->spm_ack_chk_con_3, SPM_ACK_CHK_3_CON_EN); > Can this be done in one `clrsetbits32` call? Done https://review.coreboot.org/c/coreboot/+/85599/comment/480f63a2_775255b2?us… : PS1, Line 755: SPM_ACK_CHK_3_CON_HW_MODE_TRIG > Align Done https://review.coreboot.org/c/coreboot/+/85599/comment/3a700f46_c66b054f?us… : PS1, Line 782: ( > Space before `(` Done https://review.coreboot.org/c/coreboot/+/85599/comment/a374e55d_06269083?us… : PS1, Line 791: i > I Done https://review.coreboot.org/c/coreboot/+/85599/comment/53270e4c_a9356088?us… : PS1, Line 794: ( > remove Done https://review.coreboot.org/c/coreboot/+/85599/comment/c298f4bc_6bb16c1e?us… : PS1, Line 797: ( > remove Done https://review.coreboot.org/c/coreboot/+/85599/comment/da523204_3d2db25e?us… : PS1, Line 861: SPM_REGWR_CFG_KEY | REG_SPM_APB_INTERNAL_EN_LSB | > Align align line742 ? -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 2 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 02:50:52 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Ccong Chen (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin. Hello Hung-Te Lin, Wenzhen Yu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85599?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... soc/meidatek/mt8196: Add SPM loader This patch adds support for loading SPM firmware from CBFS to SPM SRAM. SPM needs its own firmware to enable SPM suspend/resume function which turns off several resources such as DRAM/mainpll/26M clk when linux system suspend. coreboot log: CBFS: Found 'spm_firmware.pm' @0xadf00 size 0x5a60 in mcache @0xfffdd3c mtk_init_mcu: Loaded (and reset) spm_firmware.pm in 3 msecs (30080 byt) TEST=build pass BUG=348147674 Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Signed-off-by: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/common/Kconfig M src/soc/mediatek/common/spm.c M src/soc/mediatek/mt8196/Kconfig M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h M src/soc/mediatek/mt8196/include/soc/pll.h M src/soc/mediatek/mt8196/include/soc/spm.h A src/soc/mediatek/mt8196/spm.c 8 files changed, 1,369 insertions(+), 175 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/85599/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 2 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com>

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[S] Change in coreboot[main]: util/crossgcc: Update LLVM from 18.1.8 to 19.1.5
by Felix Singer (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Elyes Haouas, Martin L Roth. Felix Singer has posted comments on this change by Felix Singer. ( https://review.coreboot.org/c/coreboot/+/85169?usp=email ) Change subject: util/crossgcc: Update LLVM from 18.1.8 to 19.1.5 ...................................................................... Patch Set 8: (1 comment) Patchset: PS6: > For some reason the toolchain for PPC64 can't be found and also some x86 mainboards can't be built. […] The issue still persists with 19.1.5. I will do a local build and try digging into it. -- To view, visit https://review.coreboot.org/c/coreboot/+/85169?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4a392b472b7450685343e1343c7b84c78b0cad3d Gerrit-Change-Number: 85169 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 17 Dec 2024 02:43:19 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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[XS] Change in coreboot[main]: mb/topton/adl: Disable mapped SATA port
by Felix Singer (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Alicja Michalska. Felix Singer has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/85609?usp=email ) Change subject: mb/topton/adl: Disable mapped SATA port ...................................................................... Patch Set 2: (1 comment) Patchset: PS2: We use the hashtag field for marking patches supposed to be included in the release. It's a bit hidden, unfortunately. It appears after expanding the menu in the top-left corner with "Show all". -- To view, visit https://review.coreboot.org/c/coreboot/+/85609?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9556383952d163a145ac73cb846740a4ce67a1e1 Gerrit-Change-Number: 85609 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 02:17:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: util/crossgcc: Update ACPICA from 20230628 to 20241212
by Felix Singer (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Elyes Haouas, Martin L Roth. Felix Singer has posted comments on this change by Elyes Haouas. ( https://review.coreboot.org/c/coreboot/+/84787?usp=email ) Change subject: util/crossgcc: Update ACPICA from 20230628 to 20241212 ...................................................................... Patch Set 5: (1 comment) Patchset: PS4: > I've verified that the link used by the CI works. So the issue relies somewhere else. I think I've fixed the issue. Let's see.. -- To view, visit https://review.coreboot.org/c/coreboot/+/84787?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ae7073e46084024360ac0dd44e0df666cb32269 Gerrit-Change-Number: 84787 Gerrit-PatchSet: 5 Gerrit-Owner: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-Comment-Date: Tue, 17 Dec 2024 01:57:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Singer <service+coreboot-gerrit(a)felixsinger.de>

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