coreboot-gerrit December 2024

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[M] Change in coreboot[main]: mb/google/skywalker: Add MediaTek MT8189 reference board
by Yidi Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Vince Liu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85617?usp=email ) Change subject: mb/google/skywalker: Add MediaTek MT8189 reference board ...................................................................... Patch Set 2: Code-Review+2 (1 comment) Patchset: PS2: You probably need to rebase to the latest main branch. ``` Traceback (most recent call last): File "/home/coreboot/node-root/workspace/coreboot-gerrit/./util/mtkheader/gen-bl-img.py", line 89, in <module> main(sys.argv) File "/home/coreboot/node-root/workspace/coreboot-gerrit/./util/mtkheader/gen-bl-img.py", line 86, in main write(argv[4], gen_preloader(argv[1], argv[2], read(argv[3]))) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/home/coreboot/node-root/workspace/coreboot-gerrit/./util/mtkheader/gen-bl-img.py", line 72, in gen_preloader gfh_info = gen_gfh_info(chip_ver, data) ^^^^^^^^^^^^^^^^^^^^^^^^^^^^ File "/home/coreboot/node-root/workspace/coreboot-gerrit/./util/mtkheader/gen-bl-img.py", line 32, in gen_gfh_info load_addr = entries[chip] - gfh_size ~~~~~~~^^^^^^ KeyError: 'mt8189' make[2]: *** [src/soc/mediatek/mt8189/Makefile.mk:22: /cb-build/coreboot-gerrit.0/gcc/GOOGLE_SKYWALKER/cbfs/fallback/bootblock.bin] Error 1 make[2]: Leaving directory '/home/coreboot/node-root/workspace/coreboot-gerrit' ``` -- To view, visit https://review.coreboot.org/c/coreboot/+/85617?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I690508fea91c790f202f234f89be8f3cf4d09546 Gerrit-Change-Number: 85617 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 11:46:43 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders
by Yidi Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Xi Chen, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85625?usp=email ) Change subject: soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders ...................................................................... soc/mediatek/common: Move SPM_SYSTEM_BASE_OFFSET to soc folders MT8196's SPM_SYSTEM_BASE_OFFSET has a different offset due to the hardware design. To avoiding a new config to differentiate MT8196 and other MediaTek SoCs, move the definition to the SoCs folder. BUG=none TEST=emerge-geralt coreboot && emerge-corsola coreboot Change-Id: I5df510d5d05a0594d87e7e96e1e03e20a018785f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/spm_common.h M src/soc/mediatek/mt8186/include/soc/spm.h M src/soc/mediatek/mt8188/include/soc/spm.h M src/soc/mediatek/mt8192/include/soc/spm.h M src/soc/mediatek/mt8195/include/soc/spm.h 5 files changed, 7 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/85625/1 diff --git a/src/soc/mediatek/common/include/soc/spm_common.h b/src/soc/mediatek/common/include/soc/spm_common.h index 6a65b2c..f45b59e 100644 --- a/src/soc/mediatek/common/include/soc/spm_common.h +++ b/src/soc/mediatek/common/include/soc/spm_common.h @@ -5,8 +5,6 @@ #include <soc/mcu_common.h> -#define SPM_SYSTEM_BASE_OFFSET 0x40000000 - struct pcm_desc { u32 pmem_words; u32 total_words; diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h index cffc523..9368916 100644 --- a/src/soc/mediatek/mt8186/include/soc/spm.h +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -14,6 +14,7 @@ #include <soc/spm_common.h> #include <types.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 #define SPM_INIT_DONE_US 20 #define CLK_SCP_CFG_0 (IO_PHYS + 0x200) diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h index 043a102..529ad18 100644 --- a/src/soc/mediatek/mt8188/include/soc/spm.h +++ b/src/soc/mediatek/mt8188/include/soc/spm.h @@ -9,6 +9,8 @@ #include <soc/spm_common.h> #include <types.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index cc5052b..065053a 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -9,6 +9,8 @@ #include <soc/spm_common.h> #include <types.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h index c118f06..67873ec 100644 --- a/src/soc/mediatek/mt8195/include/soc/spm.h +++ b/src/soc/mediatek/mt8195/include/soc/spm.h @@ -9,6 +9,8 @@ #include <soc/spm_common.h> #include <types.h> +#define SPM_SYSTEM_BASE_OFFSET 0x40000000 + /* SPM READ/WRITE CFG */ #define SPM_PROJECT_CODE 0xb16 #define SPM_REGWR_CFG_KEY (SPM_PROJECT_CODE << 16) -- To view, visit https://review.coreboot.org/c/coreboot/+/85625?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5df510d5d05a0594d87e7e96e1e03e20a018785f Gerrit-Change-Number: 85625 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Use array to represent spm_sw_rsv registers
by Yidi Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Xi Chen, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85624?usp=email ) Change subject: soc/mediatek/common: Use array to represent spm_sw_rsv registers ...................................................................... soc/mediatek/common: Use array to represent spm_sw_rsv registers This patch only revises the registers used by common/spm.c. BUG=none TEST=emerge-geralt coreboot && emerge-rauru corsola Change-Id: I7f49e18e7907d59944e6eb3554df667d12b07399 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/spm.c M src/soc/mediatek/mt8186/include/soc/spm.h M src/soc/mediatek/mt8188/include/soc/spm.h M src/soc/mediatek/mt8192/include/soc/spm.h M src/soc/mediatek/mt8195/include/soc/spm.h 5 files changed, 9 insertions(+), 34 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/85624/1 diff --git a/src/soc/mediatek/common/spm.c b/src/soc/mediatek/common/spm.c index 8a57af7..65372f9 100644 --- a/src/soc/mediatek/common/spm.c +++ b/src/soc/mediatek/common/spm.c @@ -67,8 +67,8 @@ write32(&mtk_spm->spm_sw_flag_0, pcm_flags); write32(&mtk_spm->spm_sw_flag_1, pcm_flags1); - write32(&mtk_spm->spm_sw_rsv_7, pcm_flags); - write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1); + write32(&mtk_spm->spm_sw_rsv[7], pcm_flags); + write32(&mtk_spm->spm_sw_rsv[8], pcm_flags1); } static void spm_parse_firmware(struct mtk_mcu *mcu) diff --git a/src/soc/mediatek/mt8186/include/soc/spm.h b/src/soc/mediatek/mt8186/include/soc/spm.h index b402b2c..cffc523 100644 --- a/src/soc/mediatek/mt8186/include/soc/spm.h +++ b/src/soc/mediatek/mt8186/include/soc/spm.h @@ -415,15 +415,7 @@ uint32_t spm_sw_debug_0; uint32_t spm_sw_flag_1; uint32_t spm_sw_debug_1; - uint32_t spm_sw_rsv_0; - uint32_t spm_sw_rsv_1; - uint32_t spm_sw_rsv_2; - uint32_t spm_sw_rsv_3; - uint32_t spm_sw_rsv_4; - uint32_t spm_sw_rsv_5; - uint32_t spm_sw_rsv_6; - uint32_t spm_sw_rsv_7; - uint32_t spm_sw_rsv_8; + uint32_t spm_sw_rsv[9]; uint32_t spm_bk_wake_event; uint32_t spm_bk_vtcxo_dur; uint32_t spm_bk_wake_misc; diff --git a/src/soc/mediatek/mt8188/include/soc/spm.h b/src/soc/mediatek/mt8188/include/soc/spm.h index 240805c6..043a102 100644 --- a/src/soc/mediatek/mt8188/include/soc/spm.h +++ b/src/soc/mediatek/mt8188/include/soc/spm.h @@ -733,15 +733,7 @@ u32 spm_sw_debug_0; u32 spm_sw_flag_1; u32 spm_sw_debug_1; - u32 spm_sw_rsv_0; - u32 spm_sw_rsv_1; - u32 spm_sw_rsv_2; - u32 spm_sw_rsv_3; - u32 spm_sw_rsv_4; - u32 spm_sw_rsv_5; - u32 spm_sw_rsv_6; - u32 spm_sw_rsv_7; - u32 spm_sw_rsv_8; + u32 spm_sw_rsv[9]; u32 spm_bk_wake_event; u32 spm_bk_vtcxo_dur; u32 spm_bk_wake_misc; diff --git a/src/soc/mediatek/mt8192/include/soc/spm.h b/src/soc/mediatek/mt8192/include/soc/spm.h index 4c24a48..cc5052b 100644 --- a/src/soc/mediatek/mt8192/include/soc/spm.h +++ b/src/soc/mediatek/mt8192/include/soc/spm.h @@ -603,9 +603,8 @@ u32 spm_sw_flag_0; u32 spm_sw_debug_0; u32 spm_sw_flag_1; - u32 reserved11[8]; - u32 spm_sw_rsv_7; - u32 spm_sw_rsv_8; + u32 spm_sw_debug_1; + u32 spm_sw_rsv[9]; u32 reserved12[203]; u32 spm_ack_chk_con_3; u32 spm_ack_chk_pc_3; @@ -645,8 +644,8 @@ check_member(mtk_spm_regs, spm_force_dvfs, 0x4fc); check_member(mtk_spm_regs, spm_sw_flag_0, 0x600); check_member(mtk_spm_regs, spm_sw_flag_1, 0x608); -check_member(mtk_spm_regs, spm_sw_rsv_7, 0x62c); -check_member(mtk_spm_regs, spm_sw_rsv_8, 0x630); +check_member(mtk_spm_regs, spm_sw_rsv[7], 0x62c); +check_member(mtk_spm_regs, spm_sw_rsv[8], 0x630); check_member(mtk_spm_regs, spm_ack_chk_con_3, 0x960); check_member(mtk_spm_regs, spm_ack_chk_timer_3, 0x96c); check_member(mtk_spm_regs, sys_timer_con, 0x98c); diff --git a/src/soc/mediatek/mt8195/include/soc/spm.h b/src/soc/mediatek/mt8195/include/soc/spm.h index 0974ee1..c118f06 100644 --- a/src/soc/mediatek/mt8195/include/soc/spm.h +++ b/src/soc/mediatek/mt8195/include/soc/spm.h @@ -705,15 +705,7 @@ u32 spm_sw_debug_0; u32 spm_sw_flag_1; u32 spm_sw_debug_1; - u32 spm_sw_rsv_0; - u32 spm_sw_rsv_1; - u32 spm_sw_rsv_2; - u32 spm_sw_rsv_3; - u32 spm_sw_rsv_4; - u32 spm_sw_rsv_5; - u32 spm_sw_rsv_6; - u32 spm_sw_rsv_7; - u32 spm_sw_rsv_8; + u32 spm_sw_rsv[9]; u32 spm_bk_wake_event; u32 spm_bk_vtcxo_dur; u32 spm_bk_wake_misc; -- To view, visit https://review.coreboot.org/c/coreboot/+/85624?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7f49e18e7907d59944e6eb3554df667d12b07399 Gerrit-Change-Number: 85624 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Xi Chen <xixi.chen(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/common: Move some functions to spm_v1.c
by Yidi Lin (Code Review) 17 Dec '24

17 Dec '24

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85623?usp=email ) Change subject: soc/mediatek/common: Move some functions to spm_v1.c ...................................................................... soc/mediatek/common: Move some functions to spm_v1.c The init flow in `spm_init_pcm_register` and `spm_kick_pcm_to_run` is simplified on MT8196. And MT8196 does not have corresponded registers used by these two functions. Therefore, move these two function to a separated file and simply named it as spm_v1.c. BUG=none TEST=emerge-geralt coreboot && emerge-corsola coreboot Change-Id: I028d8f8ca8c9988d26d400f25ca09a2615541364 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/spm_common.h M src/soc/mediatek/common/spm.c A src/soc/mediatek/common/spm_v1.c M src/soc/mediatek/mt8186/Makefile.mk M src/soc/mediatek/mt8188/Makefile.mk M src/soc/mediatek/mt8192/Makefile.mk M src/soc/mediatek/mt8195/Makefile.mk 7 files changed, 53 insertions(+), 45 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/23/85623/1 diff --git a/src/soc/mediatek/common/include/soc/spm_common.h b/src/soc/mediatek/common/include/soc/spm_common.h index 820fbca..6a65b2c 100644 --- a/src/soc/mediatek/common/include/soc/spm_common.h +++ b/src/soc/mediatek/common/include/soc/spm_common.h @@ -27,5 +27,8 @@ void spm_set_wakeup_event(const struct pwr_ctrl *pwrctrl); void spm_extern_initialize(void); int spm_init(void); +void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl); +void spm_init_pcm_register(void); +void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl); #endif /* SOC_MEDIATEK_SPM_COMMON_H */ diff --git a/src/soc/mediatek/common/spm.c b/src/soc/mediatek/common/spm.c index e39f3da..8a57af7 100644 --- a/src/soc/mediatek/common/spm.c +++ b/src/soc/mediatek/common/spm.c @@ -51,22 +51,7 @@ setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); } -static void spm_init_pcm_register(void) -{ - /* Init r0 with POWER_ON_VAL0 */ - write32(&mtk_spm->pcm_reg_data_ini, - read32(&mtk_spm->spm_power_on_val0)); - write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); - write32(&mtk_spm->pcm_pwr_io_en, 0); - - /* Init r7 with POWER_ON_VAL1 */ - write32(&mtk_spm->pcm_reg_data_ini, - read32(&mtk_spm->spm_power_on_val1)); - write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); - write32(&mtk_spm->pcm_pwr_io_en, 0); -} - -static void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) +void spm_set_pcm_flags(const struct pwr_ctrl *pwrctrl) { u32 pcm_flags = pwrctrl->pcm_flags, pcm_flags1 = pwrctrl->pcm_flags1; @@ -86,31 +71,6 @@ write32(&mtk_spm->spm_sw_rsv_8, pcm_flags1); } -static void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) -{ - /* Waiting for loading SPMFW done*/ - while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) - ; - - /* Init register to match PCM expectation */ - write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); - write32(&mtk_spm->spm_bus_protect2_mask_b, - SPM_BUS_PROTECT2_MASK_B_DEF); - write32(&mtk_spm->pcm_reg_data_ini, 0); - - spm_set_pcm_flags(pwrctrl); - - /* Kick PCM to run (only toggle PCM_KICK) */ - setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); - - /* Reset md32pcm */ - SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn, - MD32PCM_CFGREG_SW_RSTN_RESET, 1); - - /* Waiting for SPM init done */ - udelay(SPM_INIT_DONE_US); -} - static void spm_parse_firmware(struct mtk_mcu *mcu) { size_t file_size, copy_size; diff --git a/src/soc/mediatek/common/spm_v1.c b/src/soc/mediatek/common/spm_v1.c new file mode 100644 index 0000000..cbae66e --- /dev/null +++ b/src/soc/mediatek/common/spm_v1.c @@ -0,0 +1,45 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <device/mmio.h> +#include <soc/spm.h> +#include <delay.h> + +void spm_init_pcm_register(void) +{ + /* Init r0 with POWER_ON_VAL0 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val0)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R0); + write32(&mtk_spm->pcm_pwr_io_en, 0); + + /* Init r7 with POWER_ON_VAL1 */ + write32(&mtk_spm->pcm_reg_data_ini, + read32(&mtk_spm->spm_power_on_val1)); + write32(&mtk_spm->pcm_pwr_io_en, PCM_RF_SYNC_R7); + write32(&mtk_spm->pcm_pwr_io_en, 0); +} + +void spm_kick_pcm_to_run(const struct pwr_ctrl *pwrctrl) +{ + /* Waiting for loading SPMFW done*/ + while (read32(&mtk_spm->md32pcm_dma0_rlct) != 0x0) + ; + + /* Init register to match PCM expectation */ + write32(&mtk_spm->spm_bus_protect_mask_b, SPM_BUS_PROTECT_MASK_B_DEF); + write32(&mtk_spm->spm_bus_protect2_mask_b, + SPM_BUS_PROTECT2_MASK_B_DEF); + write32(&mtk_spm->pcm_reg_data_ini, 0); + + spm_set_pcm_flags(pwrctrl); + + /* Kick PCM to run (only toggle PCM_KICK) */ + setbits32(&mtk_spm->pcm_con0, SPM_REGWR_CFG_KEY | PCM_CK_EN_LSB); + + /* Reset md32pcm */ + SET32_BITFIELDS(&mtk_spm->md32pcm_cfgreg_sw_rstn, + MD32PCM_CFGREG_SW_RSTN_RESET, 1); + + /* Waiting for SPM init done */ + udelay(SPM_INIT_DONE_US); +} diff --git a/src/soc/mediatek/mt8186/Makefile.mk b/src/soc/mediatek/mt8186/Makefile.mk index fda4180..0d44c2e 100644 --- a/src/soc/mediatek/mt8186/Makefile.mk +++ b/src/soc/mediatek/mt8186/Makefile.mk @@ -50,7 +50,7 @@ ramstage-y += ../common/pmic_wrap.c pmic_wrap.c pmif.c mt6366.c ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c rtc.c ramstage-y += soc.c -ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/tps65132s.c ramstage-y += ../common/usb.c ../common/usb_secondary.c usb.c diff --git a/src/soc/mediatek/mt8188/Makefile.mk b/src/soc/mediatek/mt8188/Makefile.mk index e9e7088..3c5965b 100644 --- a/src/soc/mediatek/mt8188/Makefile.mk +++ b/src/soc/mediatek/mt8188/Makefile.mk @@ -56,7 +56,7 @@ ramstage-y += ../common/pmif_spmi.c pmif_spmi.c ramstage-y += ../common/rtc.c ../common/rtc_osc_init.c ../common/rtc_mt6359p.c ramstage-y += soc.c -ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/tps65132s.c ramstage-y += ../common/usb.c usb.c diff --git a/src/soc/mediatek/mt8192/Makefile.mk b/src/soc/mediatek/mt8192/Makefile.mk index 8b409ba..1c4baa8 100644 --- a/src/soc/mediatek/mt8192/Makefile.mk +++ b/src/soc/mediatek/mt8192/Makefile.mk @@ -49,7 +49,7 @@ ramstage-y += ../common/pmif.c ../common/pmif_init.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c -ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/ufs.c ramstage-y += ../common/usb.c usb.c diff --git a/src/soc/mediatek/mt8195/Makefile.mk b/src/soc/mediatek/mt8195/Makefile.mk index 3ece4ad..f011f95 100644 --- a/src/soc/mediatek/mt8195/Makefile.mk +++ b/src/soc/mediatek/mt8195/Makefile.mk @@ -65,7 +65,7 @@ ramstage-y += ../common/pmif.c ../common/pmif_init.c ramstage-y += ../common/rtc.c ../common/rtc_mt6359p.c ramstage-y += soc.c -ramstage-y += ../common/spm.c spm.c +ramstage-y += ../common/spm.c ../common/spm_v1.c spm.c ramstage-y += ../common/sspm.c ramstage-y += ../common/ufs.c ramstage-y += ../common/usb.c usb.c -- To view, visit https://review.coreboot.org/c/coreboot/+/85623?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I028d8f8ca8c9988d26d400f25ca09a2615541364 Gerrit-Change-Number: 85623 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
by Yu-Ping Wu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Vince Liu, Yidi Lin. Yu-Ping Wu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85616?usp=email ) Change subject: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197 Gerrit-Change-Number: 85616 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 11:40:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: commonlib: Refactor CSE sync eventLog
by Dinesh Gehlot (Code Review) 17 Dec '24

17 Dec '24

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85622?usp=email ) Change subject: commonlib: Refactor CSE sync eventLog ...................................................................... commonlib: Refactor CSE sync eventLog This patch enhances the readability of the CSE sync event ELOG_TYPE_FW_CSE_SYNC by updating the event naming from "early and late bootstage" to "pre and post memory." BUG=b:379585294 TEST=boot verified on google/rex0 and google/rex64 without change: ``` rex-rev3 ~ # elogtool list rex64-rev3 ~ # /media/usb/elogtool list 3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync ``` with change: ``` rex64-rev3 ~ # elogtool list 3 | 2024-12-17 02:22:36-0800 | Firmware CSE sync | Post RAM CSE Sync ``` Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/elog.h M src/soc/intel/common/block/cse/cse_lite.c M util/cbfstool/eventlog.c 3 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/22/85622/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index e1c8f5d..2206062 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -385,8 +385,8 @@ * Events related to CSE sync */ #define ELOG_TYPE_FW_CSE_SYNC 0xbd -#define ELOG_FW_EARLY_CSE_SYNC 0x0 -#define ELOG_FW_LATE_CSE_SYNC 0x1 +#define ELOG_FW_PRERAM_CSE_SYNC 0x0 +#define ELOG_FW_POSTRAM_CSE_SYNC 0x1 #define ELOG_FW_CSE_SYNC_AT_PAYLOAD 0x2 /* Only the 7-LSB are used for size */ diff --git a/src/soc/intel/common/block/cse/cse_lite.c b/src/soc/intel/common/block/cse/cse_lite.c index 00b5de6..f2ca720 100644 --- a/src/soc/intel/common/block/cse/cse_lite.c +++ b/src/soc/intel/common/block/cse/cse_lite.c @@ -806,8 +806,8 @@ return CB_ERR; printk(BIOS_INFO, "cse_lite: CSE RW Update Successful\n"); - elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, ENV_RAMSTAGE ? ELOG_FW_LATE_CSE_SYNC : - ELOG_FW_EARLY_CSE_SYNC); + elog_add_event_byte(ELOG_TYPE_FW_CSE_SYNC, ENV_RAMSTAGE ? ELOG_FW_POSTRAM_CSE_SYNC : + ELOG_FW_PRERAM_CSE_SYNC); return CB_SUCCESS; } diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index 0227683..989cc6c 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -485,8 +485,8 @@ }; static const struct valstr cse_sync_path_types[] = { - {ELOG_FW_EARLY_CSE_SYNC, "Early CSE Sync"}, - {ELOG_FW_LATE_CSE_SYNC, "Late CSE Sync"}, + {ELOG_FW_PRERAM_CSE_SYNC, "Pre RAM CSE Sync"}, + {ELOG_FW_POSTRAM_CSE_SYNC, "Post RAM CSE Sync"}, {ELOG_FW_CSE_SYNC_AT_PAYLOAD, "CSE Sync at Payload"}, {0, NULL}, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/85622?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia5db3ffb43b2ceac821de72ef9e88ed62e617d41 Gerrit-Change-Number: 85622 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>

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[S] Change in coreboot[main]: util/cbfstool: eliminate late sign of life event
by Dinesh Gehlot (Code Review) 17 Dec '24

17 Dec '24

Dinesh Gehlot has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85621?usp=email ) Change subject: util/cbfstool: eliminate late sign of life event ...................................................................... util/cbfstool: eliminate late sign of life event The purpose of the late sign-of-life (SOL) event was to add logs for the CSE sync at the payload. However, recent changes have decoupled CSE sync and SOL events, resulting in redundant event logging. This update eliminates the superfluous late SOL event logs. BUG=b:379585294 TEST=boot verified on google/rex0 and google/rex64 without change: ``` rex-rev3 ~ # elogtool list rex64-rev3 ~ # /media/usb/elogtool list 0 | 2024-01-01 22:50:19-0800 | Log area cleared | 250 1 | 2024-01-01 22:50:59-0800 | System boot | 30 2 | 2024-01-01 22:50:59-0800 | Firmware Splash Screen | Enabled 3 | 2024-01-01 22:51:00-0800 | Power Fail 4 | 2024-01-01 22:51:00-0800 | SUS Power Fail 5 | 2024-01-01 22:51:00-0800 | ACPI Wake | S5 6 | 2024-01-01 22:51:00-0800 | Wake Source | Power Button | 0 7 | 2024-01-01 22:51:00-0800 | Late Sign of Life | CSE Sync Late SOL Screen Shown 8 | 2024-01-01 22:51:00-0800 | Firmware CSE sync | CSE Sync at Payload ``` with change: ``` rex64-rev3 ~ # elogtool list 0 | 2024-12-17 02:42:23-0800 | Log area cleared | 141 1 | 2024-12-17 02:43:14-0800 | System boot | 81 2 | 2024-12-17 02:43:14-0800 | Firmware Splash Screen | Enabled 3 | 2024-12-17 02:43:16-0800 | Power Fail 4 | 2024-12-17 02:43:16-0800 | SUS Power Fail 5 | 2024-12-17 02:43:16-0800 | ACPI Wake | S5 6 | 2024-12-17 02:43:16-0800 | Wake Source | Power Button | 0 7 | 2024-12-17 02:43:16-0800 | Firmware CSE sync | CSE Sync at Payload ``` Change-Id: I53baecb3ca0cef5e0e18732e02832e8331e000d0 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/commonlib/bsd/include/commonlib/bsd/elog.h M util/cbfstool/eventlog.c 2 files changed, 0 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/21/85621/1 diff --git a/src/commonlib/bsd/include/commonlib/bsd/elog.h b/src/commonlib/bsd/include/commonlib/bsd/elog.h index 9032abc..e1c8f5d 100644 --- a/src/commonlib/bsd/include/commonlib/bsd/elog.h +++ b/src/commonlib/bsd/include/commonlib/bsd/elog.h @@ -382,12 +382,6 @@ #define ELOG_TYPE_FW_SPLASH_SCREEN 0xbb /* - * Events related to CSE sync from payload - */ -#define ELOG_TYPE_FW_LATE_SOL 0xbc -#define ELOG_FW_LATE_SOL_CSE_SYNC 0x0 - -/* * Events related to CSE sync */ #define ELOG_TYPE_FW_CSE_SYNC 0xbd diff --git a/util/cbfstool/eventlog.c b/util/cbfstool/eventlog.c index e3fccde..0227683 100644 --- a/util/cbfstool/eventlog.c +++ b/util/cbfstool/eventlog.c @@ -169,7 +169,6 @@ {ELOG_TYPE_PSR_DATA_BACKUP, "PSR data backup"}, {ELOG_TYPE_PSR_DATA_LOST, "PSR data lost"}, {ELOG_TYPE_FW_SPLASH_SCREEN, "Firmware Splash Screen"}, - {ELOG_TYPE_FW_LATE_SOL, "Late Sign of Life "}, {ELOG_TYPE_FW_CSE_SYNC, "Firmware CSE sync"}, {ELOG_TYPE_EOL, "End of log"}, }; @@ -485,11 +484,6 @@ {0, NULL}, }; - static const struct valstr late_sol_path_types[] = { - {ELOG_FW_LATE_SOL_CSE_SYNC, "CSE Sync Late SOL Screen Shown"}, - {0, NULL}, - }; - static const struct valstr cse_sync_path_types[] = { {ELOG_FW_EARLY_CSE_SYNC, "Early CSE Sync"}, {ELOG_FW_LATE_CSE_SYNC, "Late CSE Sync"}, @@ -518,7 +512,6 @@ [ELOG_TYPE_FW_EARLY_SOL] = sizeof(uint8_t), [ELOG_TYPE_PSR_DATA_BACKUP] = sizeof(uint8_t), [ELOG_TYPE_FW_SPLASH_SCREEN] = sizeof(uint8_t), - [ELOG_TYPE_FW_LATE_SOL] = sizeof(uint8_t), [ELOG_TYPE_FW_CSE_SYNC] = sizeof(uint8_t), [0xff] = 0, }; @@ -686,11 +679,6 @@ eventlog_printf("%s", *fw_splash_screen_event ? "Enabled" : "Disabled"); break; } - case ELOG_TYPE_FW_LATE_SOL: { - const uint8_t *sol_event = event_get_data(event); - eventlog_printf("%s", val2str(*sol_event, late_sol_path_types)); - break; - } case ELOG_TYPE_FW_CSE_SYNC: { const uint8_t *cse_event = event_get_data(event); eventlog_printf("%s", val2str(*cse_event, cse_sync_path_types)); -- To view, visit https://review.coreboot.org/c/coreboot/+/85621?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I53baecb3ca0cef5e0e18732e02832e8331e000d0 Gerrit-Change-Number: 85621 Gerrit-PatchSet: 1 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com>

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[S] Change in coreboot[main]: soc/intel: Log CSE Sync Early Sign of Life event from a better place
by Dinesh Gehlot (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro, Subrata Banik, Tarun. Dinesh Gehlot has uploaded a new patch set (#5) to the change originally created by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/85111?usp=email ) The following approvals got outdated and were removed: Code-Review+1 by Karthik Ramasubramanian, Verified+1 by build bot (Jenkins) Change subject: soc/intel: Log CSE Sync Early Sign of Life event from a better place ...................................................................... soc/intel: Log CSE Sync Early Sign of Life event from a better place CSE Sync Early Sign of Life (ESOL) event is logged as soon as the CSE FW update is complete. This happens irrespective of whether Early Sign of Life screen is enabled or not. Move CSE Sync ESOL event right before displaying the ESOL screen. BUG=b:378458829, b:379585294 TEST=Build Brox BIOS image and boot to OS. Ensure that the ESOL event for CSE Sync is logged. Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/alderlake/romstage/fsp_params.c M src/soc/intel/alderlake/romstage/romstage.c M src/soc/intel/common/block/cse/cse_lite.c M src/soc/intel/meteorlake/romstage/fsp_params.c 4 files changed, 10 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/11/85111/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85111?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa0dbb87ddde69dc3f4a9e058fc6bed8711b29e7 Gerrit-Change-Number: 85111 Gerrit-PatchSet: 5 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com>

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[XS] Change in coreboot[main]: src/soc/intel/cmn/blk/cse: Log cse sync information
by Dinesh Gehlot (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Dinesh Gehlot, Kapil Porwal, Paul Menzel, Subrata Banik. Hello Kapil Porwal, Karthik Ramasubramanian, Paul Menzel, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85219?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: src/soc/intel/cmn/blk/cse: Log cse sync information ...................................................................... src/soc/intel/cmn/blk/cse: Log cse sync information This patch adds an event log entry for successful CSE synchronization, along with the boot stage where the synchronization occurred, either early or late. BUG=b:379585294 TEST=elog verified on rex0 and rex64 Rex0: ``` rex-rev3 ~ # /media/usb/elogtool list 3 | 2024-01-01 22:25:59-0800 | Firmware CSE sync | Late CSE Sync ``` Rex64: ``` rex64-rev3 ~ # /media/usb/elogtool list 8 | 2024-01-01 22:51:00-0800 | Firmware CSE sync | CSE Sync at Payload ``` Change-Id: Idece841c2b069d7688afc258470667ed2851a282 Signed-off-by: Dinesh Gehlot <digehlot(a)google.com> --- M src/soc/intel/common/block/cse/cse_lite.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85219/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/85219?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Idece841c2b069d7688afc258470667ed2851a282 Gerrit-Change-Number: 85219 Gerrit-PatchSet: 3 Gerrit-Owner: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Yidi Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yu-Ping Wu. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 31: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 31 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 11:20:12 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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