coreboot-gerrit December 2024

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Merge SKX and CPX
by Shuo Liu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85557?usp=email ) Change subject: soc/intel/xeon_sp: Merge SKX and CPX ...................................................................... Patch Set 5: (1 comment) Patchset: PS5: > May Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I915d502efc36b299e089158c60e81822dfa2b333 Gerrit-Change-Number: 85557 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 13:35:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com>

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[L] Change in coreboot[main]: soc/intel/xeon_sp: Merge SKX and CPX
by Shuo Liu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Angel Pons, Arthur Heymans, Christian Walter, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Morgan Jang, Patrick Rudolph, Tim Chu. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85557?usp=email ) Change subject: soc/intel/xeon_sp: Merge SKX and CPX ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/85557/comment/813b4097_8e4dcfa5?us… : PS5, Line 10: - Create a new 14nm folder > Agree. `chip_gen1. […] Good point. The only open is that before a ICX port is upstreamed, maybe we need to use chip_gen4.c as the name? -- To view, visit https://review.coreboot.org/c/coreboot/+/85557?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I915d502efc36b299e089158c60e81822dfa2b333 Gerrit-Change-Number: 85557 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 13:33:51 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Shuo Liu <shuo.liu(a)intel.com> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com>

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[XS] Change in coreboot[main]: src/soc/amd/glinda: Update PSP MBOX offset in Kconfig
by Naresh Solanki (Code Review) 17 Dec '24

17 Dec '24

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85627?usp=email ) Change subject: src/soc/amd/glinda: Update PSP MBOX offset in Kconfig ...................................................................... src/soc/amd/glinda: Update PSP MBOX offset in Kconfig Glinda SoC PSP MBOX offset is 0x10970 & hence update the same in Kconfig Change-Id: I328959513228fe0f9e78070eb6b302ef89857b42 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/glinda/Kconfig 1 file changed, 3 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/85627/1 diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index 68a1b6f..5f1c57e 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -380,6 +380,9 @@ help Add psp_verstage signature token to the build & PSP Directory Table +config PSPV2_MBOX_CMD_OFFSET + hex + default 0x10970 endmenu config VBOOT -- To view, visit https://review.coreboot.org/c/coreboot/+/85627?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I328959513228fe0f9e78070eb6b302ef89857b42 Gerrit-Change-Number: 85627 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com>

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[XS] Change in coreboot[main]: soc/amd/common/psp_gen2: Add config for PSP MBOX offset
by Naresh Solanki (Code Review) 17 Dec '24

17 Dec '24

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85626?usp=email ) Change subject: soc/amd/common/psp_gen2: Add config for PSP MBOX offset ...................................................................... soc/amd/common/psp_gen2: Add config for PSP MBOX offset Some SoC like Glinda use different PSP MBOX offset. Add config to allow SoC Kconfig to override PSP MBOX offset. Change-Id: Iefcc7d3b75689b43399a7a7b612417c155619211 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/common/block/psp/Kconfig M src/soc/amd/common/block/psp/psp_gen2.c 2 files changed, 6 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/85626/1 diff --git a/src/soc/amd/common/block/psp/Kconfig b/src/soc/amd/common/block/psp/Kconfig index 07ee0fa..17853fa 100644 --- a/src/soc/amd/common/block/psp/Kconfig +++ b/src/soc/amd/common/block/psp/Kconfig @@ -202,3 +202,7 @@ default y if SOC_AMD_COMMON_BLOCK_PSP help Select this if AMDFWTOOL needs to be built + +config PSPV2_MBOX_CMD_OFFSET + hex + default 0x10570 diff --git a/src/soc/amd/common/block/psp/psp_gen2.c b/src/soc/amd/common/block/psp/psp_gen2.c index 21c1f2a..026d32f 100644 --- a/src/soc/amd/common/block/psp/psp_gen2.c +++ b/src/soc/amd/common/block/psp/psp_gen2.c @@ -8,8 +8,8 @@ #include <device/mmio.h> #include "psp_def.h" -#define PSP_MAILBOX_COMMAND_OFFSET 0x10570 /* 4 bytes */ -#define PSP_MAILBOX_BUFFER_OFFSET 0x10574 /* 8 bytes */ +#define PSP_MAILBOX_COMMAND_OFFSET CONFIG_PSPV2_MBOX_CMD_OFFSET /* 4 bytes */ +#define PSP_MAILBOX_BUFFER_OFFSET (CONFIG_PSPV2_MBOX_CMD_OFFSET + 4) /* 8 bytes */ #define IOHC_MISC_PSP_MMIO_REG 0x2e0 -- To view, visit https://review.coreboot.org/c/coreboot/+/85626?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iefcc7d3b75689b43399a7a7b612417c155619211 Gerrit-Change-Number: 85626 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com>

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[S] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Shuo Liu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Jérémy Compostella, Patrick Rudolph, Subrata Banik, Uwe Poeche, yuchi.chen(a)intel.com. Shuo Liu has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 13:28:36 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Introduce early_pch_init
by Lean Sheng Tan (Code Review) 17 Dec '24

17 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85505?usp=email ) ( 3 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/xeon_sp: Introduce early_pch_init ...................................................................... soc/intel/xeon_sp: Introduce early_pch_init Stop using platform_fsp_memory_init_params_cb() as SoC specific romstage hook and introduce early_pch_init() to do PCH init in romstage before FSP-M runs. Move PCH specific code into early_pch_init and call it from common code. Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85505 Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/ebg/soc_pch.c M src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h M src/soc/intel/xeon_sp/ibl/soc_pch.c M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/lbg/soc_pch.c M src/soc/intel/xeon_sp/romstage.c M src/soc/intel/xeon_sp/skx/romstage.c M src/soc/intel/xeon_sp/spr/romstage.c 10 files changed, 33 insertions(+), 25 deletions(-) Approvals: build bot (Jenkins): Verified Shuo Liu: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 82657f9..25dc4f6 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -10,7 +10,6 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> -#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> #include <string.h> @@ -108,10 +107,6 @@ /* Adjust the "cold boot required" flag in CMOS. */ soc_set_mrc_cold_boot_flag(!mupd->FspmArchUpd.NvsBufferPtr); - - /* FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); } uint32_t get_max_capacity_mib(void) diff --git a/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h index acb1785..2b5ed25 100644 --- a/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/ebg/include/soc/soc_pch.h @@ -3,7 +3,8 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_ +void early_pch_init(void); + void pch_lock_dmictl(void); -void pch_disable_hda(void); #endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/ebg/soc_pch.c b/src/soc/intel/xeon_sp/ebg/soc_pch.c index a40af7a..053447c 100644 --- a/src/soc/intel/xeon_sp/ebg/soc_pch.c +++ b/src/soc/intel/xeon_sp/ebg/soc_pch.c @@ -10,6 +10,7 @@ #include <soc/azalia_device.h> #include <soc/bootblock.h> #include <soc/soc_pch.h> +#include <soc/pch_pci_devs.h> #include <soc/pch.h> #include <soc/pmc.h> #include <console/console.h> @@ -67,7 +68,7 @@ #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) #define PSF3_HDA_BASE_ADDRESS 0x280 -void pch_disable_hda(void) +static void pch_disable_hda(void) { /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | @@ -82,3 +83,10 @@ printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); } + +void early_pch_init(void) +{ + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); +} diff --git a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h index acb1785..00f0a1b 100644 --- a/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/ibl/include/soc/soc_pch.h @@ -3,7 +3,7 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_ +void early_pch_init(void); void pch_lock_dmictl(void); -void pch_disable_hda(void); #endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/ibl/soc_pch.c b/src/soc/intel/xeon_sp/ibl/soc_pch.c index 6bfa749..7487441 100644 --- a/src/soc/intel/xeon_sp/ibl/soc_pch.c +++ b/src/soc/intel/xeon_sp/ibl/soc_pch.c @@ -1,11 +1,12 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <device/pci_ops.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #include <intelblocks/pcr.h> #include <soc/bootblock.h> -#include <console/console.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> +#include <soc/soc_pch.h> #define PCR_PSF3_TO_SHDW_PMC_REG_BASE 0x600 #define PCR_PSFX_TO_SHDW_BAR4 0x10 @@ -44,3 +45,7 @@ */ soc_config_acpibase(); } + +void early_pch_init(void) +{ +} diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h index acb1785..2b5ed25 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h @@ -3,7 +3,8 @@ #ifndef _SOC_SOC_PCH_H_ #define _SOC_SOC_PCH_H_ +void early_pch_init(void); + void pch_lock_dmictl(void); -void pch_disable_hda(void); #endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/lbg/soc_pch.c b/src/soc/intel/xeon_sp/lbg/soc_pch.c index 8bc01f7..fda56fa 100644 --- a/src/soc/intel/xeon_sp/lbg/soc_pch.c +++ b/src/soc/intel/xeon_sp/lbg/soc_pch.c @@ -64,7 +64,7 @@ #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) #define PSF3_HDA_BASE_ADDRESS 0x1800 -void pch_disable_hda(void) +static void pch_disable_hda(void) { /* Ensure memory, io, and bus master are all disabled */ pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | @@ -82,3 +82,10 @@ printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); } + +void early_pch_init(void) +{ + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); +} diff --git a/src/soc/intel/xeon_sp/romstage.c b/src/soc/intel/xeon_sp/romstage.c index 30bbad7..024dfa5 100644 --- a/src/soc/intel/xeon_sp/romstage.c +++ b/src/soc/intel/xeon_sp/romstage.c @@ -8,11 +8,14 @@ #include <soc/ddr.h> #include <soc/intel/common/smbios.h> #include <soc/romstage.h> +#include <soc/soc_pch.h> #include <soc/util.h> #include <spd.h> void mainboard_romstage_entry(void) { + early_pch_init(); + rtc_init(); if (soc_get_rtc_failed()) mainboard_rtc_failed(); diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index f41d8f3..f66022d 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -1,11 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/romstage.h> -#include <device/pci_def.h> #include <intelblocks/rtc.h> #include <soc/romstage.h> -#include <soc/pch_pci_devs.h> -#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> @@ -27,10 +24,6 @@ m_cfg->VTdConfig.VTdSupport = config->vtd_support; m_cfg->VTdConfig.CoherencySupport = config->coherency_support; m_cfg->VTdConfig.ATS = config->ats_support; - - /* FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); } uint8_t get_error_correction_type(const uint8_t RasModesEnabled) diff --git a/src/soc/intel/xeon_sp/spr/romstage.c b/src/soc/intel/xeon_sp/spr/romstage.c index 4438a59..43eb187 100644 --- a/src/soc/intel/xeon_sp/spr/romstage.c +++ b/src/soc/intel/xeon_sp/spr/romstage.c @@ -17,7 +17,6 @@ #include <soc/chip_common.h> #include <soc/romstage.h> #include <soc/pci_devs.h> -#include <soc/soc_pch.h> #include <static.h> #include <string.h> #include <soc/config.h> @@ -245,10 +244,6 @@ } if (CONFIG(MEM_POR_FREQ)) mupd->FspmConfig.EnforceDdrMemoryFreqPor = 0x0; - - /* SPR-FSP has no UPD to disable HDA, so do it manually here... */ - if (!is_devfn_enabled(PCH_DEVFN_HDA)) - pch_disable_hda(); } uint8_t get_error_correction_type(const uint8_t RasModesEnabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/85505?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id31a2018f5820098e83782b19a1672d2e35bdb83 Gerrit-Change-Number: 85505 Gerrit-PatchSet: 6 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/intel/xeon_sp/lbg: Add support to hide HDA
by Lean Sheng Tan (Code Review) 17 Dec '24

17 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85496?usp=email ) Change subject: soc/intel/xeon_sp/lbg: Add support to hide HDA ...................................................................... soc/intel/xeon_sp/lbg: Add support to hide HDA The azalia audio device is usually unused on server platforms. Add code to hide it since FSP lacks this option and there's no official bit in the IFD to disable it. The device is disabled early to: 1. Prevent FSP from seeing the device being present. It could keep an internal state that the device is working. 2. Prevent FSP-M from trying to detect codecs. This would increase boot time. 3. Prevent FSP from becoming confused or crash when the device is suddently missing as disabled by a ramstage PCI driver. TEST: No HDA PCI device visible on ocp/tiogapass. Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85496 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/xeon_sp/cpx/romstage.c M src/soc/intel/xeon_sp/lbg/Makefile.mk A src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h M src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h M src/soc/intel/xeon_sp/lbg/include/soc/pmc.h M src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h M src/soc/intel/xeon_sp/lbg/soc_pch.c M src/soc/intel/xeon_sp/skx/romstage.c 8 files changed, 56 insertions(+), 3 deletions(-) Approvals: build bot (Jenkins): Verified Angel Pons: Looks good to me, approved diff --git a/src/soc/intel/xeon_sp/cpx/romstage.c b/src/soc/intel/xeon_sp/cpx/romstage.c index 25dc4f6..82657f9 100644 --- a/src/soc/intel/xeon_sp/cpx/romstage.c +++ b/src/soc/intel/xeon_sp/cpx/romstage.c @@ -10,6 +10,7 @@ #include <soc/romstage.h> #include <soc/pci_devs.h> #include <soc/intel/common/smbios.h> +#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> #include <string.h> @@ -107,6 +108,10 @@ /* Adjust the "cold boot required" flag in CMOS. */ soc_set_mrc_cold_boot_flag(!mupd->FspmArchUpd.NvsBufferPtr); + + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); } uint32_t get_max_capacity_mib(void) diff --git a/src/soc/intel/xeon_sp/lbg/Makefile.mk b/src/soc/intel/xeon_sp/lbg/Makefile.mk index 5dedc83..c855003 100644 --- a/src/soc/intel/xeon_sp/lbg/Makefile.mk +++ b/src/soc/intel/xeon_sp/lbg/Makefile.mk @@ -1,7 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only bootblock-y += soc_pch.c soc_gpio.c -romstage-y += soc_pmutil.c soc_gpio.c +romstage-y += soc_pmutil.c soc_pch.c soc_gpio.c ramstage-y += soc_pmutil.c soc_pch.c soc_gpio.c lockdown.c CPPFLAGS_common += -I$(src)/soc/intel/xeon_sp/lbg/include diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h b/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h new file mode 100644 index 0000000..cfe74e8 --- /dev/null +++ b/src/soc/intel/xeon_sp/lbg/include/soc/azalia_device.h @@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DEVICE_AZALIA_H +#define DEVICE_AZALIA_H + +#define HDA_PCS 0x54 +#define HDA_PCS_PS_D3HOT 3 +#define HDA_FNCFG 0x530 + +#endif /* DEVICE_AZALIA_H */ diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h b/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h index 8c0b669..d365eb5 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/pcr_ids.h @@ -6,6 +6,7 @@ #define PID_CSME0 0x90 #define PID_ITSS 0xC4 #define PID_RTC 0xC3 +#define PID_PSF3 0xBC #define PID_DMI 0xEF #define PID_GPIOCOM5 0x11 #define PID_GPIOCOM4 0xAB diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h index 88a9b10..133703a 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/pmc.h @@ -49,4 +49,7 @@ #define GPE0_DW_SHIFT(x) (4 * (x)) #define GBLRST_CAUSE0 0x124 #define GBLRST_CAUSE1 0x128 + +#define NST_PG_FDIS1 0x628 +#define NST_FDIS_DSP (1 << 23) #endif diff --git a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h index 2d87be3..acb1785 100644 --- a/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h +++ b/src/soc/intel/xeon_sp/lbg/include/soc/soc_pch.h @@ -4,5 +4,6 @@ #define _SOC_SOC_PCH_H_ void pch_lock_dmictl(void); +void pch_disable_hda(void); #endif /* _SOC_SOC_PCH_H_ */ diff --git a/src/soc/intel/xeon_sp/lbg/soc_pch.c b/src/soc/intel/xeon_sp/lbg/soc_pch.c index 83ed20a..8bc01f7 100644 --- a/src/soc/intel/xeon_sp/lbg/soc_pch.c +++ b/src/soc/intel/xeon_sp/lbg/soc_pch.c @@ -1,13 +1,16 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <device/pci_ops.h> -#include <soc/pci_devs.h> -#include <soc/pcr_ids.h> #include <intelblocks/pcr.h> +#include <intelblocks/pmclib.h> #include <intelblocks/rtc.h> #include <intelblocks/p2sb.h> +#include <soc/azalia_device.h> #include <soc/bootblock.h> #include <soc/soc_pch.h> +#include <soc/pch_pci_devs.h> +#include <soc/pci_devs.h> +#include <soc/pcr_ids.h> #include <soc/pmc.h> #include <console/console.h> @@ -56,3 +59,26 @@ uint32_t reg32 = pcr_read32(PID_DMI, PCR_DMI_DMICTL); pcr_write32(PID_DMI, PCR_DMI_DMICTL, reg32 | PCR_DMI_DMICTL_SRLOCK); } + +#define PCR_PSFX_T0_SHDW_PCIEN 0x1C +#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) +#define PSF3_HDA_BASE_ADDRESS 0x1800 + +void pch_disable_hda(void) +{ + /* Ensure memory, io, and bus master are all disabled */ + pci_and_config16(PCH_DEV_HDA, PCI_COMMAND, ~(PCI_COMMAND_MASTER | + PCI_COMMAND_MEMORY | PCI_COMMAND_IO)); + /* Put controller to D3 */ + pci_or_config32(PCH_DEV_HDA, HDA_PCS, HDA_PCS_PS_D3HOT); + /* Lock and disable everything */ + pci_write_config8(PCH_DEV_HDA, HDA_FNCFG, 0x15); + + /* Disable DSP in PMC */ + pmc_or_mmio32(NST_PG_FDIS1, NST_FDIS_DSP); + /* Hide PCI function */ + pcr_or32(PID_PSF3, PSF3_HDA_BASE_ADDRESS + PCR_PSFX_T0_SHDW_PCIEN, + PCR_PSFX_T0_SHDW_PCIEN_FUNDIS); + + printk(BIOS_INFO, "%s: Disabled HDA device 00:1f.3\n", __func__); +} diff --git a/src/soc/intel/xeon_sp/skx/romstage.c b/src/soc/intel/xeon_sp/skx/romstage.c index f66022d..f41d8f3 100644 --- a/src/soc/intel/xeon_sp/skx/romstage.c +++ b/src/soc/intel/xeon_sp/skx/romstage.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ #include <arch/romstage.h> +#include <device/pci_def.h> #include <intelblocks/rtc.h> #include <soc/romstage.h> +#include <soc/pch_pci_devs.h> +#include <soc/soc_pch.h> #include <soc/soc_util.h> #include <static.h> @@ -24,6 +27,10 @@ m_cfg->VTdConfig.VTdSupport = config->vtd_support; m_cfg->VTdConfig.CoherencySupport = config->coherency_support; m_cfg->VTdConfig.ATS = config->ats_support; + + /* FSP has no UPD to disable HDA, so do it manually here... */ + if (!is_devfn_enabled(PCH_DEVFN_HDA)) + pch_disable_hda(); } uint8_t get_error_correction_type(const uint8_t RasModesEnabled) -- To view, visit https://review.coreboot.org/c/coreboot/+/85496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I84ac53621b2dcf7baa68f2efb30d0b7e77595c8d Gerrit-Change-Number: 85496 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com

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[S] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Angel Pons (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Jérémy Compostella, Patrick Rudolph, Shuo Liu, Subrata Banik, Uwe Poeche, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 12:01:34 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[L] Change in coreboot[main]: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
by Yidi Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Vince Liu. Yidi Lin has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85616?usp=email ) Change subject: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197 Gerrit-Change-Number: 85616 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 11:50:32 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/meidatek/mt8196: Add SPM loader
by Yidi Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Ccong Chen, Hung-Te Lin, Jarried Lin, Wenzhen Yu. Yidi Lin has posted comments on this change by Ccong Chen. ( https://review.coreboot.org/c/coreboot/+/85599?usp=email ) Change subject: soc/meidatek/mt8196: Add SPM loader ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: With the refactoring in https://review.coreboot.org/c/coreboot/+/85625, you can just implement `spm_init_pcm_register` and `spm_kick_pcm_to_run` in mt8196/spm.c and define `SPM_SYSTEM_BASE_OFFSET` as `0` without adding a new Kconfig. @jarried.lin@mediatek.com @wenzhen.yu@mediatek.corp-partner.google.com Please rebase the patch after CB:85625 is merged. -- To view, visit https://review.coreboot.org/c/coreboot/+/85599?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie09346f46cb734c74776b760485e7f35d4357e5e Gerrit-Change-Number: 85599 Gerrit-PatchSet: 3 Gerrit-Owner: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Wenzhen Yu <wenzhen.yu(a)mediatek.corp-partner.google.com> Gerrit-Attention: Ccong Chen <ot_ccong.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 11:49:36 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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