coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 31: (1 comment) File src/soc/mediatek/mt8196/tracker.c: https://review.coreboot.org/c/coreboot/+/84929/comment/c558d078_4fe68d95?us… : PS30, Line 61: ms > Is this supposed to be `us`, so that 10ms would be `10000us`? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 31 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 11:19:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Paul Menzel, Xiwen Shao, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84929?usp=email to look at the new patch set (#31). The following approvals got outdated and were removed: Code-Review+2 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, including AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. Rename VLPCFG_BASE to VLP_CFG_BASE. TEST=Build pass, When we encounter a bus hang and HW watchdog triggers a reset to the platform, the tracker will print the latched information: [INFO ] **Dump %s aw debug register start** [INFO ] xxxxxx, 0x1c600000, 0x0, 63 This means that the 63rd entry latch accessing 0x1c600000 has a bus timeout. BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 5 files changed, 175 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/31 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 31 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add pwrsel driver
by Paul Menzel (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85613?usp=email ) Change subject: soc/mediatek/mt8196: Add pwrsel driver ...................................................................... Patch Set 1: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85613/comment/58294621_1b975a8a?us… : PS1, Line 11: What values (profiles?) can be written by the firmware? https://review.coreboot.org/c/coreboot/+/85613/comment/02033c6a_7e8534cc?us… : PS1, Line 14: PWR_SEL = 0x0 Aren’t two log messages added in the code? File src/soc/mediatek/mt8196/mtk_pwrsel.c: https://review.coreboot.org/c/coreboot/+/85613/comment/8dee263e_fa73ce78?us… : PS1, Line 22: printk(BIOS_INFO, "PWR_SEL = %#x\n", It’d be great to have a comment documenting the possible values. https://review.coreboot.org/c/coreboot/+/85613/comment/6ad59947_14e53b22?us… : PS1, Line 22: printk(BIOS_INFO, "PWR_SEL = %#x\n", : read32p(MCUSYS_BASE + OFFSET_PWRSEL)); : printk(BIOS_INFO, "PWRSEL_CONFIG = %#x\n", : read32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG)); For an info level messages it’d be great to make this message user readable/understandable. -- To view, visit https://review.coreboot.org/c/coreboot/+/85613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Gerrit-Change-Number: 85613 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 11:15:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add pwrsel driver
by Jarried Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85613?usp=email ) Change subject: soc/mediatek/mt8196: Add pwrsel driver ...................................................................... Patch Set 2: (7 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85613/comment/d64dbff1_24d19045?us… : PS1, Line 9: > is Done File src/mainboard/google/rauru/romstage.c: PS1: > Move to a separate patch. Done File src/soc/mediatek/mt8196/Makefile.mk: https://review.coreboot.org/c/coreboot/+/85613/comment/81ca81bf_28389e74?us… : PS1, Line 33: romstage-y += mtk_pwrsel.c > Move to line 36 Done File src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h: https://review.coreboot.org/c/coreboot/+/85613/comment/4f13484f_a7c1ad89?us… : PS1, Line 8: 0x0 > One more tab to align with `0x04A4` below. Done File src/soc/mediatek/mt8196/mtk_pwrsel.c: https://review.coreboot.org/c/coreboot/+/85613/comment/5ae8a4d2_3b5b829f?us… : PS1, Line 15: ( > remove Done https://review.coreboot.org/c/coreboot/+/85613/comment/32a9a63a_f6117913?us… : PS1, Line 22: printk(BIOS_INFO, "PWR_SEL = %#x\n", : read32p(MCUSYS_BASE + OFFSET_PWRSEL)); > one line ? Done https://review.coreboot.org/c/coreboot/+/85613/comment/84408dfd_bd537e19?us… : PS1, Line 24: printk(BIOS_INFO, "PWRSEL_CONFIG = %#x\n", : read32p(MFG_VCORE_AO_RPC_PWRSEL_CONFIG)); > ditto Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Gerrit-Change-Number: 85613 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 11:14:44 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[XS] Change in coreboot[main]: mb/google/rauru: Add pwrsel init in romstage
by Jarried Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85620?usp=email ) Change subject: mb/google/rauru: Add pwrsel init in romstage ...................................................................... mb/google/rauru: Add pwrsel init in romstage BUG=b:317009620 TEST=build pass, reg set ok, log show: PWR_SEL = 0x0 Change-Id: I37c0fb905f99491ca99f04bc5bfa6abfb1c01059 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/mainboard/google/rauru/romstage.c 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/85620/1 diff --git a/src/mainboard/google/rauru/romstage.c b/src/mainboard/google/rauru/romstage.c index ebeedb8..b6f0d4e 100644 --- a/src/mainboard/google/rauru/romstage.c +++ b/src/mainboard/google/rauru/romstage.c @@ -3,11 +3,13 @@ #include <arch/stages.h> #include <soc/emi.h> #include <soc/irq2axi.h> +#include <soc/mtk_pwrsel.h> #include <soc/pcie.h> void platform_romstage_main(void) { irq2axi_disable(); + pwrsel_init(); mtk_dram_init(); if (CONFIG(PCI)) -- To view, visit https://review.coreboot.org/c/coreboot/+/85620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37c0fb905f99491ca99f04bc5bfa6abfb1c01059 Gerrit-Change-Number: 85620 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add pwrsel driver
by Jarried Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85613?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8196: Add pwrsel driver ...................................................................... soc/mediatek/mt8196: Add pwrsel driver The MediaTek pwrsel (Power Select) is mainly used to reduce power consumption, controlled by mcupm. BUG=b:317009620 TEST=Build pass Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Signed-off-by: Jarried Lin <jarried.lin(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/mtk_pwrsel.h A src/soc/mediatek/mt8196/mtk_pwrsel.c 4 files changed, 44 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/13/85613/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Gerrit-Change-Number: 85613 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
by Vince Liu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Vince Liu has posted comments on this change by Vince Liu. ( https://review.coreboot.org/c/coreboot/+/85616?usp=email ) Change subject: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC ...................................................................... Patch Set 2: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85616/comment/ff64d521_d940760c?us… : PS1, Line 10: Also enable UART and ARM arch timer. > Please provide a brief overview about how MT8189 differs from the previous SoC (either MT8196 or MT8 […] Done File src/soc/mediatek/mt8189/include/soc/memlayout.ld: https://review.coreboot.org/c/coreboot/+/85616/comment/a2bacbf5_e0ca71bb?us… : PS1, Line 22: /* : * Since MCUPM uses most of the space, most regions are put in SRAM_L2C below. : */ : > wrong indent Done https://review.coreboot.org/c/coreboot/+/85616/comment/49072caf_d871987d?us… : PS1, Line 35: /* : * The needed size can be obtained by: : * aarch64-cros-linux-gnu-objdump -x dram.elf | grep memsz : * To move the address, dram.elf also needs to be modified accordingly. : */ > wrong indent Done https://review.coreboot.org/c/coreboot/+/85616/comment/400ed413_1ab6a015?us… : PS1, Line 42: /* : * The bootROM needs 4K starting from SRAM_L2C_START so the bootblock starting address : * is fixed at SRAM_L2C_START + 4K, and the 4K can be reused after bootblock is started. : * To move the address, gen-bl-img.py also needs to be modified accordingly. : */ > wrong indent Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197 Gerrit-Change-Number: 85616 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 10:37:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com> Comment-In-Reply-To: Yidi Lin <yidilin(a)google.com>

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[L] Change in coreboot[main]: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC
by Vince Liu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Vince Liu, Yidi Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85616?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Code-Review+1 by Yidi Lin, Code-Review+2 by Yu-Ping Wu, Verified+1 by build bot (Jenkins) Change subject: soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC ...................................................................... soc/mediatek/mt8189: Add a stub implementation of MT8189 SoC Add new folder and basic drivers for Mediatek SoC 'MT8189'. Also enable UART and ARM arch timer. This commit includes the necessary initialization files for MT8189, which cannot be shared with other existing SoCs. The modules included are: - Memory layout: MT8189 has only 64KB of SRAM, differing in space allocation compared to other SoCs. - PLL: Different SoCs have different PLL designs. In this commit, we provide the most basic settings, with more configurations to be added in future commits. - Timer: MT8189 uses timer v2, unlike other SoCs which use timer v1. - SPI: The SPI driver for different SoCs varies depending on the GPIO/ PIN MUX used. In this commit, we provide the most basic settings, with more configurations to be added in future commits. - EMI: MT8189 uses common EMI code along with MT8189-specific 'dram_parameter.h'. This commit provides an EMI stub to ensure coreboot builds successfully. Future DRAM-related commits will utilize the common EMI code. BUG=b:379008996 BRANCH=none TEST=saw the coreboot uart log to bootblock Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197 Signed-off-by: Vince Liu <vince-wl.liu(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/mt8189/Kconfig A src/soc/mediatek/mt8189/Makefile.mk A src/soc/mediatek/mt8189/bootblock.c A src/soc/mediatek/mt8189/emi.c A src/soc/mediatek/mt8189/include/soc/addressmap.h A src/soc/mediatek/mt8189/include/soc/emi.h A src/soc/mediatek/mt8189/include/soc/memlayout.ld A src/soc/mediatek/mt8189/include/soc/pll.h A src/soc/mediatek/mt8189/include/soc/spi.h A src/soc/mediatek/mt8189/include/soc/timer.h A src/soc/mediatek/mt8189/soc.c A src/soc/mediatek/mt8189/spi.c A src/soc/mediatek/mt8189/timer.c 13 files changed, 318 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/16/85616/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85616?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5d83c4c7fba49e455fac0b58f019ad225f83c197 Gerrit-Change-Number: 85616 Gerrit-PatchSet: 2 Gerrit-Owner: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Vince Liu <vince-wl.liu(a)mediatek.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: cbfs: Remove remnants of ext-win-*
by Maximilian Brune (Code Review) 17 Dec '24

17 Dec '24

Maximilian Brune has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85619?usp=email ) Change subject: cbfs: Remove remnants of ext-win-* ...................................................................... cbfs: Remove remnants of ext-win-* Since commit 34a7e66faa46 ("util/cbfstool: Add a new mechanism to provide a memory map") the ext-win-base and ext-win-size option has been replaced with the "--mmap" option. Signed-off-by: Maximilian Brune <maximilian.brune(a)9elements.com> Change-Id: I33cfb59d9dbe88c4f618301ac1506e3281b1a483 --- M Documentation/util/cbfstool/mmap_windows.md M Makefile.mk M util/cbfstool/cbfstool.c 3 files changed, 4 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/19/85619/1 diff --git a/Documentation/util/cbfstool/mmap_windows.md b/Documentation/util/cbfstool/mmap_windows.md index 66685f3..654653c 100644 --- a/Documentation/util/cbfstool/mmap_windows.md +++ b/Documentation/util/cbfstool/mmap_windows.md @@ -36,9 +36,8 @@ `(4G - 16M) to 4G`. However, the platform is free to choose where the extended window lives in the host address space. Since `cbfstool` needs to know the exact location of the extended window, it allows the -platform to pass in two parameters `ext-win-base` and `ext-win-size` -that provide the base and the size of the extended window in host -address space. +platform to pass in one parameter `mmap` that provide the base and the +size of the extended window in host address space. `cbfstool` creates two memory map windows using the knowledge about the standard decode window and the information passed in by the platform diff --git a/Makefile.mk b/Makefile.mk index ca79d05..bc547de 100644 --- a/Makefile.mk +++ b/Makefile.mk @@ -988,7 +988,6 @@ # # CBFSTOOL_ADD_CMD_OPTIONS can be used by arch/SoC/mainboard to supply # add commands with any additional arguments for cbfstool. -# Example: --ext-win-base <base> --ext-win-size <size> define cbfs-add-cmd-for-region $(CBFSTOOL) $@.tmp \ add$(if $(filter stage,$(call extract_nth,3,$(1))),-stage)$(if \ diff --git a/util/cbfstool/cbfstool.c b/util/cbfstool/cbfstool.c index 25f4847..5eb6335 100644 --- a/util/cbfstool/cbfstool.c +++ b/util/cbfstool/cbfstool.c @@ -1968,16 +1968,12 @@ " -U Unprocessed; don't decompress or make ELF\n" " -v Provide verbose output (-v=INFO -vv=DEBUG output)\n" " -h Display this help message\n\n" - " --ext-win-base Base of extended decode window in host address\n" - " space(x86 only)\n" - " --ext-win-size Size of extended decode window in host address\n" - " space(x86 only)\n" "COMMANDs:\n" " add [-r image,regions] -f FILE -n NAME -t TYPE [-A hash] \\\n" " [-c compression] [-b base-address | -a alignment] \\\n" " [-p padding size] [-y|--xip if TYPE is FSP] \\\n" " [-j topswap-size] (Intel CPUs only) [--ibb] \\\n" - " [--ext-win-base win-base --ext-win-size win-size] " + " [--mmio flash-base:mmio-base:size] " "Add a component\n" " " " -j valid size: 0x10000 0x20000 0x40000 0x80000 0x100000 \n" @@ -1990,7 +1986,7 @@ " [-S comma-separated-section(s)-to-ignore] \\\n" " [-a alignment] [-Q|--pow2page] \\\n" " [-y|--xip] [--ibb] \\\n" - " [--ext-win-base win-base --ext-win-size win-size] " + " [--mmio flash-base:mmio-base:size] " "Add a stage to the ROM\n" " add-flat-binary [-r image,regions] -f FILE -n NAME \\\n" " [-A hash] -l load-address -e entry-point \\\n" -- To view, visit https://review.coreboot.org/c/coreboot/+/85619?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I33cfb59d9dbe88c4f618301ac1506e3281b1a483 Gerrit-Change-Number: 85619 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com>

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[XS] Change in coreboot[main]: soc/intel/common/block/power_limit: Disable RAPL via MSR completely
by Uwe Poeche (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Johannes Hahn, Mario Scheithauer, Werner Zeh. Uwe Poeche has posted comments on this change by Johannes Hahn. ( https://review.coreboot.org/c/coreboot/+/85606?usp=email ) Change subject: soc/intel/common/block/power_limit: Disable RAPL via MSR completely ...................................................................... Patch Set 3: Code-Review+1 (1 comment) Patchset: PS3: I started our ci (with activated apl1/4 and ehl1 mainboards) with that patch on top and checked on ehl1 MSR 0x610 in OS before and after the patch. Result is as regarded. The effort to set ehl1 to power limit and also verify that MSR 0x196 Bit 10 was set before and after the patch not set was interrupted. The error which shows siemens-bot via his submit is caused by the known problematic upstream patch CB:84833 and has no correlation with the patch here. -- To view, visit https://review.coreboot.org/c/coreboot/+/85606?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I8272339a991667d5ba177f4755ec40e1961d729e Gerrit-Change-Number: 85606 Gerrit-PatchSet: 3 Gerrit-Owner: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Reviewer: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Attention: Mario Scheithauer <mario.scheithauer(a)siemens.com> Gerrit-Attention: Johannes Hahn <johannes-hahn(a)siemens.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 10:21:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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