coreboot-gerrit December 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: mb/amd/majolica: Call abrecovery in romstage to heal the corruption
by Bao Zheng (Code Review) 17 Dec '24

17 Dec '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84578?usp=email ) Change subject: mb/amd/majolica: Call abrecovery in romstage to heal the corruption ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84578?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e0946b9519de9f778d2f0b8c262003e00bc3fd7 Gerrit-Change-Number: 84578 Gerrit-PatchSet: 9 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: soc/amd/cezanne: Heal the corruption in A/B recovery
by Bao Zheng (Code Review) 17 Dec '24

17 Dec '24

Bao Zheng has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/84577?usp=email ) Change subject: soc/amd/cezanne: Heal the corruption in A/B recovery ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/84577?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: abandon Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2cdab00a7122e4831fe5d91cf5d390ad11db0999 Gerrit-Change-Number: 84577 Gerrit-PatchSet: 10 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Jarried Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Hope Wang, Hung-Te Lin, Yidi Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85630?usp=email to look at the new patch set (#2). Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6316 driver Add MT6316 driver in SoC folder TEST=Build pass BUG=b:317009620 Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6316.h A src/soc/mediatek/common/mt6316.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6316.c 4 files changed, 1,167 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/85630/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Yu-Ping Wu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... Patch Set 31: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 31 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 14:13:29 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: amdfwtool: Set address mode as relative table
by Bao Zheng (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Felix Held, Marshall Dawson, Zheng Bao, ritul guru. Bao Zheng has posted comments on this change by Bao Zheng. ( https://review.coreboot.org/c/coreboot/+/84530?usp=email ) Change subject: amdfwtool: Set address mode as relative table ...................................................................... Patch Set 4: (1 comment) File util/amdfwtool/amdfwtool.c: https://review.coreboot.org/c/coreboot/+/84530/comment/a02e0a12_bc02f465?us… : PS1, Line 385: 2 > the comment should changed too to match the changed code Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84530?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I156b315d350d9e7217afc7442ca80277bb7f9095 Gerrit-Change-Number: 84530 Gerrit-PatchSet: 4 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: ritul guru <ritul.bits(a)gmail.com> Gerrit-Attention: Zheng Bao Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 17 Dec 2024 14:13:18 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/rauru: Add pwrsel init in romstage
by Yu-Ping Wu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85620?usp=email ) Change subject: mb/google/rauru: Add pwrsel init in romstage ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85620?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I37c0fb905f99491ca99f04bc5bfa6abfb1c01059 Gerrit-Change-Number: 85620 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 14:12:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Add pwrsel driver
by Yu-Ping Wu (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/85613?usp=email ) Change subject: soc/mediatek/mt8196: Add pwrsel driver ...................................................................... Patch Set 2: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/85613?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib1b8588810fdad5c675dee865627337269b57d18 Gerrit-Change-Number: 85613 Gerrit-PatchSet: 2 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 14:12:40 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XL] Change in coreboot[main]: soc/mediatek/mt8196: Add PMIC MT6316 driver
by Jarried Lin (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Hope Wang. Hello Hope Wang, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85630?usp=email to review the following change. Change subject: soc/mediatek/mt8196: Add PMIC MT6316 driver ...................................................................... soc/mediatek/mt8196: Add PMIC MT6316 driver Add MT6316 driver in SoC folder TEST=Build pass BUG=b:317009620 Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Signed-off-by: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> --- A src/soc/mediatek/common/include/soc/mt6316.h A src/soc/mediatek/common/mt6316.c M src/soc/mediatek/mt8196/Makefile.mk A src/soc/mediatek/mt8196/mt6316.c 4 files changed, 1,167 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/85630/1 diff --git a/src/soc/mediatek/common/include/soc/mt6316.h b/src/soc/mediatek/common/include/soc/mt6316.h new file mode 100644 index 0000000..e53ae43 --- /dev/null +++ b/src/soc/mediatek/common/include/soc/mt6316.h @@ -0,0 +1,49 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_MT6316_H__ +#define __SOC_MEDIATEK_MT6316_H__ + +#include <soc/spmi.h> +#include <types.h> + +struct mt6316_setting { + unsigned short addr; + unsigned short val; + unsigned short mask; + unsigned char shift; +}; + +enum { + MT6316_BUCK_1 = 0, + MT6316_BUCK_2, + MT6316_BUCK_3, + MT6316_BUCK_4, + MT6316_BUCK_max, +}; + +enum { + MT6316_PMIC_SWCID_H_ADDR = 0x20B, + MT6316_BUCK_TOP_ELR0 = 0x1448, + MT6316_BUCK_TOP_ELR1 = 0x1449, + MT6316_BUCK_TOP_ELR2 = 0x144A, + MT6316_BUCK_TOP_ELR3 = 0x144B, + MT6316_BUCK_TOP_ELR4 = 0x144C, + MT6316_BUCK_TOP_ELR5 = 0x144D, + MT6316_BUCK_TOP_ELR6 = 0x144E, + MT6316_BUCK_TOP_ELR7 = 0x144F, + MT6316_BUCK_VBUCK1_DBG0 = 0x14A0, + MT6316_BUCK_VBUCK1_DBG1 = 0x14A1, + MT6316_BUCK_VBUCK3_DBG0 = 0x15A0, + MT6316_BUCK_VBUCK3_DBG1 = 0x15A1, + MT6316_BUCK_TOP_4PHASE_TOP_ANA_CON0 = 0x1688, +}; + +void mt6316_init(void); +void mt6316_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uv); +u32 mt6316_buck_get_voltage(enum spmi_slave slvid, u32 buck_id); +void mt6316_init_setting(void); +void mt6316_write_field(u32 slvid, u32 reg, u32 val, u32 mask, u32 shift); +void mt6316_buck_set_mode(u32 slvid, u32 buck_id, u8 mode); +u32 mt6316_buck_get_mode(enum spmi_slave slvid, u32 buck_id); + +#endif /* __SOC_MEDIATEK_MT6316_H__ */ diff --git a/src/soc/mediatek/common/mt6316.c b/src/soc/mediatek/common/mt6316.c new file mode 100644 index 0000000..476591d --- /dev/null +++ b/src/soc/mediatek/common/mt6316.c @@ -0,0 +1,209 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <console/console.h> +#include <delay.h> +#include <soc/mt6316.h> +#include <soc/pmif.h> +#include <soc/pmif_spmi.h> + +static struct pmif *pmif_arb = NULL; + +static void mt6316_read(enum spmi_slave slvid, u32 reg, u32 *data) +{ + assert(pmif_arb); + pmif_arb->read(pmif_arb, slvid, reg, data); +} + +static void mt6316_write(u32 slvid, u32 reg, u32 data) +{ + assert(pmif_arb); + pmif_arb->write(pmif_arb, slvid, reg, data); +} + +void mt6316_write_field(u32 slvid, u32 reg, u32 val, u32 mask, u32 shift) +{ + assert(pmif_arb); + pmif_arb->write_field(pmif_arb, slvid, reg, val, mask, shift); +} + +static u32 mt6316_read_field(u32 slvid, u32 reg, u32 mask, u32 shift) +{ + assert(pmif_arb); + return pmif_arb->read_field(pmif_arb, slvid, reg, mask, shift); +} + +static void mt6316_wdt_enable(enum spmi_slave slvid) +{ + u32 reg_val; + + /* read the current wdt setting */ + mt6316_read(slvid, 0x138, &reg_val); + printk(BIOS_INFO, "[%s]S%d TOP_RST_MISC=0x%x\n", __func__, slvid, reg_val); + mt6316_write(slvid, 0x3B1, 0xE9); + mt6316_write(slvid, 0x3B2, 0xE6); + mt6316_write(slvid, 0x139, 0x2); + mt6316_write(slvid, 0x139, 0x1); + mt6316_write(slvid, 0x139, 0x8); + udelay(50); + mt6316_write(slvid, 0x13A, 0x8); + mt6316_write(slvid, 0x3B1, 0); + mt6316_write(slvid, 0x3B2, 0); + mt6316_read(slvid, 0x138, &reg_val); + printk(BIOS_INFO, "[%s]S%d TOP_RST_MISC=0x%x\n", __func__, slvid, reg_val); +} + +void mt6316_buck_set_voltage(u32 slvid, u32 buck_id, u32 buck_uv) +{ + unsigned int vol_reg, vol_reg_l, vol_val; + + assert(pmif_arb); + + switch (buck_id) { + case MT6316_BUCK_1: + vol_reg = MT6316_BUCK_TOP_ELR0; + vol_reg_l = MT6316_BUCK_TOP_ELR1; + break; + case MT6316_BUCK_3: + vol_reg = MT6316_BUCK_TOP_ELR4; + vol_reg_l = MT6316_BUCK_TOP_ELR5; + break; + default: + printk(BIOS_ERR, "%s: Unknown buck_id %u", __func__, buck_id); + return; + }; + + vol_val = buck_uv / 2500; + mt6316_write(slvid, vol_reg_l, (vol_val & 0x1)); + mt6316_write(slvid, vol_reg, (vol_val >> 1)); + udelay(200); + printk(BIOS_INFO, "%s: %d, 0x%x, %d\n", __func__, buck_id, vol_val, buck_uv); +} + +u32 mt6316_buck_get_voltage(enum spmi_slave slvid, u32 buck_id) +{ + u32 vol_reg, vol_reg_l, vol, vol_l; + + assert(pmif_arb); + + switch (buck_id) { + case MT6316_BUCK_1: + vol_reg = MT6316_BUCK_VBUCK1_DBG0; + vol_reg_l = MT6316_BUCK_VBUCK1_DBG1; + break; + case MT6316_BUCK_3: + vol_reg = MT6316_BUCK_VBUCK3_DBG0; + vol_reg_l = MT6316_BUCK_VBUCK3_DBG1; + break; + default: + printk(BIOS_ERR, "%s: Unknown buck_id %u", __func__, buck_id); + return 0; + }; + + mt6316_read(slvid, vol_reg, &vol); + mt6316_read(slvid, vol_reg_l, &vol_l); + vol_l &= 0x1; + printk(BIOS_INFO, "%s: %d, 0x%x, 0x%x, %d\n", __func__, buck_id, vol, vol_l, + (vol * 5000 + vol_l * 2500)); + return (vol * 5000 + vol_l * 2500); +} + +void mt6316_buck_set_mode(u32 slvid, u32 buck_id, u8 mode) +{ + unsigned int mod_shift; + + assert(pmif_arb); + + switch (buck_id) { + case MT6316_BUCK_1: + mod_shift = 0; + break; + case MT6316_BUCK_3: + mod_shift = 2; + break; + default: + printk(BIOS_ERR, "%s: Unknown buck_id %u", __func__, buck_id); + return; + }; + + mt6316_write_field(slvid, MT6316_BUCK_TOP_4PHASE_TOP_ANA_CON0, + !!mode, 0x1, mod_shift); + udelay(100); + printk(BIOS_INFO, "%s: %d, %d\n", __func__, buck_id, mode); +} + +u32 mt6316_buck_get_mode(enum spmi_slave slvid, u32 buck_id) +{ + u32 mod_shift, mod; + + assert(pmif_arb); + + switch (buck_id) { + case MT6316_BUCK_1: + mod_shift = 0; + break; + case MT6316_BUCK_3: + mod_shift = 2; + break; + default: + printk(BIOS_ERR, "%s: Unknown buck_id %u", __func__, buck_id); + return -1; + }; + + mt6316_read(slvid, MT6316_BUCK_TOP_4PHASE_TOP_ANA_CON0, &mod); + mod >>= mod_shift; + mod &= 0x1; + printk(BIOS_INFO, "%s: %d, %d\n", __func__, buck_id, mod); + return mod; +} + +static void mt6316_set_all_test_con9(void) +{ + u32 reg_val_6 = 0, reg_val_7 = 0, reg_val_8 = 0, reg_val_15 = 0; + + mt6316_write(SPMI_SLAVE_6, 0x222, 0x20); + mt6316_write(SPMI_SLAVE_7, 0x222, 0x20); + mt6316_write(SPMI_SLAVE_8, 0x222, 0x20); + mt6316_write(SPMI_SLAVE_15, 0x222, 0x20); + + mt6316_read(SPMI_SLAVE_6, 0x222, &reg_val_6); + mt6316_read(SPMI_SLAVE_7, 0x222, &reg_val_7); + mt6316_read(SPMI_SLAVE_8, 0x222, &reg_val_8); + mt6316_read(SPMI_SLAVE_15, 0x222, &reg_val_15); + + printk(BIOS_INFO, "Set end MT6316 test_con9: 0x%x, 0x%x, 0x%x, 0x%x\n", + reg_val_6, reg_val_7, reg_val_8, reg_val_15); +} + +static void init_pmif_arb(void) +{ + if (!pmif_arb) { + pmif_arb = get_pmif_controller(PMIF_SPMI, SPMI_MASTER_0);/* for N*/ + assert(pmif_arb); + } + + if (pmif_arb->is_pmif_init_done(pmif_arb)) + die("ERROR - Failed to initialize pmif spmi"); + + printk(BIOS_INFO, "[%s][MT6316_6]CHIP ID = 0x%x\n", __func__, + mt6316_read_field(SPMI_SLAVE_6, MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); + printk(BIOS_INFO, "[%s][MT6316_7]CHIP ID = 0x%x\n", __func__, + mt6316_read_field(SPMI_SLAVE_7, MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); + printk(BIOS_INFO, "[%s][MT6316_8]CHIP ID = 0x%x\n", __func__, + mt6316_read_field(SPMI_SLAVE_8, MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); + printk(BIOS_INFO, "[%s][MT6316_15]CHIP ID = 0x%x\n", __func__, + mt6316_read_field(SPMI_SLAVE_15, MT6316_PMIC_SWCID_H_ADDR, 0xFF, 0x0)); +} + +void mt6316_init(void) +{ + init_pmif_arb(); + + mt6316_wdt_enable(SPMI_SLAVE_6); + mt6316_wdt_enable(SPMI_SLAVE_7); + mt6316_wdt_enable(SPMI_SLAVE_8); + mt6316_wdt_enable(SPMI_SLAVE_15); + + mt6316_init_setting(); + mt6316_set_all_test_con9(); +} diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 9652a1e..d46ddb1 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -30,6 +30,7 @@ romstage-y += ../common/memory.c memory.c romstage-y += ../common/memory_test.c romstage-y += ../common/mmu_operations.c ../common/mmu_cmops.c +romstage-y += ../common/mt6316.c mt6316.c romstage-y += ../common/mt6363.c mt6363.c romstage-y += ../common/mt6373.c mt6373.c romstage-y += ../common/pmif_clk.c pmif_clk.c diff --git a/src/soc/mediatek/mt8196/mt6316.c b/src/soc/mediatek/mt8196/mt6316.c new file mode 100644 index 0000000..3c20059 --- /dev/null +++ b/src/soc/mediatek/mt8196/mt6316.c @@ -0,0 +1,908 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +/* + * These values are used by MediaTek internally. + * We can find these registers in "MT6316_PMIC_Design_Notice_for_MT8196G_V0.2". + * The setting values are provided by MeidaTek designers. + */ + +#include <console/console.h> +#include <soc/mt6316.h> + +static const struct mt6316_setting init_setting_s6[] = { + /* Disable magic key protection */ + {0x3B1, 0xE9, 0xFF, 0}, + {0x3B2, 0xE6, 0xFF, 0}, + {0x3A8, 0xE9, 0xFF, 0}, + {0x3A9, 0xE6, 0xFF, 0}, + {0xA15, 0x29, 0xFF, 0}, + {0xA16, 0x47, 0xFF, 0}, + {0x141C, 0x43, 0xFF, 0}, + {0x141D, 0x55, 0xFF, 0}, + {0x3AA, 0xDC, 0xFF, 0}, + {0x3AB, 0xF1, 0xFF, 0}, + /* Init setting */ + {0x13, 0x7, 0xFF, 0}, + {0x16, 0x12, 0xFF, 0}, + {0x17, 0x0, 0xFF, 0}, + {0x8A, 0x6, 0xF, 0}, + {0xA1, 0xC, 0xC, 0}, + {0xA2, 0x10, 0x10, 0}, + {0x10C, 0xC, 0xC, 0}, + {0x12C, 0x1, 0x1, 0}, + {0x140, 0x30, 0x30, 0}, + {0x142, 0x30, 0xFF, 0}, + {0x991, 0x11, 0xFF, 0}, + {0x196, 0x1, 0x1, 0}, + {0x197, 0x10, 0x10, 0}, + {0x19A, 0x1, 0x1, 0}, + {0x19B, 0x10, 0x10, 0}, + {0x217, 0x22, 0x22, 0}, + {0x219, 0x1F, 0x1F, 0}, + {0x223, 0x20, 0x20, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x988, 0x0, 0x20, 0}, + {0x98C, 0xB0, 0xFF, 0}, + {0x994, 0x0, 0xFF, 0}, + {0xA13, 0x10, 0x10, 0}, + {0xA1F, 0x80, 0x80, 0}, + {0x1452, 0x0, 0xFF, 0}, + {0x1457, 0x22, 0xFF, 0}, + {0x1458, 0x22, 0xFF, 0}, + {0x148A, 0x0, 0x3, 0}, + {0x148F, 0x2, 0x3, 0}, + {0x1492, 0x40, 0x70, 0}, + {0x150A, 0x0, 0x3, 0}, + {0x150F, 0x2, 0x3, 0}, + {0x1512, 0x40, 0x70, 0}, + {0x158A, 0x0, 0x3, 0}, + {0x158F, 0x2, 0x3, 0}, + {0x1592, 0x40, 0x70, 0}, + {0x160A, 0x0, 0x3, 0}, + {0x160F, 0x2, 0x3, 0}, + {0x1612, 0x40, 0x70, 0}, + {0x1729, 0x18, 0x18, 0}, + {0x17A9, 0x18, 0x18, 0}, + {0x1829, 0x18, 0x18, 0}, + {0x18A9, 0x18, 0x18, 0}, + {0x98, 0x2, 0x7, 0}, + {0xA1F, 0xC, 0xC, 0}, + {0xA21, 0x21, 0xFF, 0}, + {0xA23, 0xF0, 0xF0, 0}, + {0xA28, 0x21, 0xFF, 0}, + {0xA29, 0x21, 0xFF, 0}, + {0xA2A, 0x1B, 0xFF, 0}, + {0xA2B, 0x21, 0xFF, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x55, 0xFF, 0}, + {0x148A, 0xD, 0xF, 0}, + {0x148C, 0x3, 0x3, 0}, + {0x148D, 0x28, 0x7F, 0}, + {0x148E, 0x7, 0x7F, 0}, + {0x1490, 0x2, 0x3, 0}, + {0x1491, 0x19, 0x7F, 0}, + {0x1507, 0x55, 0xFF, 0}, + {0x150A, 0xD, 0xF, 0}, + {0x150C, 0x3, 0x3, 0}, + {0x150D, 0x28, 0x7F, 0}, + {0x150E, 0x7, 0x7F, 0}, + {0x1510, 0x2, 0x3, 0}, + {0x1511, 0x19, 0x7F, 0}, + {0x1587, 0xD2, 0xFF, 0}, + {0x158A, 0xD, 0xF, 0}, + {0x158D, 0xD, 0x7F, 0}, + {0x158E, 0x7, 0x7F, 0}, + {0x1590, 0x2, 0x3, 0}, + {0x1591, 0x19, 0x7F, 0}, + {0x1607, 0x55, 0xFF, 0}, + {0x160A, 0xD, 0xF, 0}, + {0x160C, 0x3, 0x3, 0}, + {0x160D, 0x28, 0x7F, 0}, + {0x160E, 0x7, 0x7F, 0}, + {0x1610, 0x2, 0x3, 0}, + {0x1611, 0x19, 0x7F, 0}, + {0x1688, 0x0, 0x1F, 0}, + {0x1689, 0x10, 0x7F, 0}, + {0x168A, 0x0, 0xFF, 0}, + {0x168B, 0x1, 0xFF, 0}, + {0x168C, 0x5, 0x3F, 0}, + {0x168D, 0x9, 0xFF, 0}, + {0x168E, 0xA0, 0xFF, 0}, + {0x1708, 0xD1, 0xFF, 0}, + {0x1709, 0xFC, 0xFF, 0}, + {0x170A, 0x92, 0xFF, 0}, + {0x170B, 0x0, 0x3, 0}, + {0x170C, 0x4C, 0x7F, 0}, + {0x170D, 0x0, 0x7F, 0}, + {0x170E, 0x30, 0x3F, 0}, + {0x170F, 0x9F, 0xFF, 0}, + {0x1710, 0x29, 0x3F, 0}, + {0x1711, 0x0, 0x3F, 0}, + {0x1712, 0x0, 0xFF, 0}, + {0x1713, 0x9C, 0x9C, 0}, + {0x1714, 0x1, 0x7F, 0}, + {0x1715, 0xFF, 0xFF, 0}, + {0x1716, 0x8E, 0xFF, 0}, + {0x1717, 0x3B, 0xFF, 0}, + {0x1718, 0x6A, 0xFF, 0}, + {0x1719, 0x80, 0xFF, 0}, + {0x171A, 0x8, 0x7F, 0}, + {0x171B, 0x1, 0x3F, 0}, + {0x171C, 0x3, 0xF, 0}, + {0x171D, 0x58, 0x7F, 0}, + {0x171E, 0xD, 0x1F, 0}, + {0x1738, 0x4, 0x1F, 0}, + {0x173B, 0x7, 0x1F, 0}, + {0x1788, 0xD1, 0xFF, 0}, + {0x1789, 0xFC, 0xFF, 0}, + {0x178A, 0x92, 0xFF, 0}, + {0x178B, 0x0, 0x3, 0}, + {0x178C, 0x4C, 0x7F, 0}, + {0x178D, 0x0, 0x7F, 0}, + {0x178E, 0x30, 0x3F, 0}, + {0x178F, 0x9F, 0xFF, 0}, + {0x1790, 0x29, 0x3F, 0}, + {0x1791, 0x0, 0x3F, 0}, + {0x1792, 0x0, 0xFF, 0}, + {0x1793, 0xDC, 0xDC, 0}, + {0x1794, 0x0, 0x3F, 0}, + {0x1795, 0xFF, 0xFF, 0}, + {0x1796, 0x8E, 0xFF, 0}, + {0x1797, 0x3B, 0xFF, 0}, + {0x1798, 0x6A, 0xFF, 0}, + {0x1799, 0x80, 0xFF, 0}, + {0x179A, 0x8, 0x7F, 0}, + {0x179B, 0x1, 0x3F, 0}, + {0x179C, 0x3, 0xF, 0}, + {0x179D, 0x58, 0x7F, 0}, + {0x179E, 0xD, 0x1F, 0}, + {0x17BB, 0x7, 0x1F, 0}, + {0x1808, 0xB1, 0xFF, 0}, + {0x1809, 0xCC, 0xFF, 0}, + {0x180A, 0x92, 0xFF, 0}, + {0x180B, 0x0, 0x3, 0}, + {0x180C, 0x54, 0x7F, 0}, + {0x180D, 0x0, 0x7F, 0}, + {0x180E, 0x20, 0x3F, 0}, + {0x180F, 0x9F, 0xFF, 0}, + {0x1810, 0x29, 0x3F, 0}, + {0x1811, 0x0, 0x3F, 0}, + {0x1812, 0x0, 0xFF, 0}, + {0x1813, 0xDC, 0xDC, 0}, + {0x1814, 0x0, 0x3F, 0}, + {0x1815, 0xEF, 0xFF, 0}, + {0x1816, 0x8E, 0xFF, 0}, + {0x1817, 0x13, 0xFF, 0}, + {0x1818, 0x62, 0xFF, 0}, + {0x1819, 0x81, 0xFF, 0}, + {0x181A, 0x1, 0x7F, 0}, + {0x181B, 0x0, 0x3F, 0}, + {0x181C, 0x3, 0xF, 0}, + {0x181D, 0x48, 0x7F, 0}, + {0x181E, 0x17, 0x1F, 0}, + {0x1827, 0x3, 0xFF, 0}, + {0x1838, 0x8, 0x1F, 0}, + {0x183A, 0xB, 0x1F, 0}, + {0x1888, 0xD1, 0xFF, 0}, + {0x1889, 0xFC, 0xFF, 0}, + {0x188A, 0x92, 0xFF, 0}, + {0x188B, 0x0, 0x3, 0}, + {0x188C, 0x4C, 0x7F, 0}, + {0x188D, 0x0, 0x7F, 0}, + {0x188E, 0x30, 0x3F, 0}, + {0x188F, 0x9F, 0xFF, 0}, + {0x1890, 0x29, 0x3F, 0}, + {0x1891, 0x0, 0x3F, 0}, + {0x1892, 0x0, 0xFF, 0}, + {0x1893, 0xDC, 0xDC, 0}, + {0x1894, 0x0, 0x3F, 0}, + {0x1895, 0xFF, 0xFF, 0}, + {0x1896, 0x8E, 0xFF, 0}, + {0x1897, 0x3B, 0xFF, 0}, + {0x1898, 0x6A, 0xFF, 0}, + {0x1899, 0x80, 0xFF, 0}, + {0x189A, 0x8, 0x7F, 0}, + {0x189B, 0x1, 0x3F, 0}, + {0x189C, 0x3, 0xF, 0}, + {0x189D, 0x58, 0x7F, 0}, + {0x189E, 0xD, 0x1F, 0}, + {0x18BB, 0x7, 0x1F, 0}, + /* Add UVLO 2.0 setting */ + {0x999, 0x4, 0x7, 5}, + {0x99e, 0x1, 0x7, 3}, + /* Enable SPMI shutdown command */ + {0x136, 0x1, 0x1, 4}, + /* Enable magic key protection */ + {0x3B1, 0, 0xFF, 0}, + {0x3B2, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, + {0xA15, 0, 0xFF, 0}, + {0xA16, 0, 0xFF, 0}, + {0x141C, 0, 0xFF, 0}, + {0x141D, 0, 0xFF, 0}, + {0x3AA, 0, 0xFF, 0}, + {0x3AB, 0, 0xFF, 0}, +}; + +static const struct mt6316_setting init_setting_s7[] = { + /* Disable magic key protection */ + {0x3B1, 0xE9, 0xFF, 0}, + {0x3B2, 0xE6, 0xFF, 0}, + {0x3A8, 0xE9, 0xFF, 0}, + {0x3A9, 0xE6, 0xFF, 0}, + {0xA15, 0x29, 0xFF, 0}, + {0xA16, 0x47, 0xFF, 0}, + {0x141C, 0x43, 0xFF, 0}, + {0x141D, 0x55, 0xFF, 0}, + {0x3AA, 0xDC, 0xFF, 0}, + {0x3AB, 0xF1, 0xFF, 0}, + /* Init setting */ + {0x13, 0x7, 0xFF, 0}, + {0x16, 0x12, 0xFF, 0}, + {0x17, 0x0, 0xFF, 0}, + {0x8A, 0x6, 0xF, 0}, + {0xA1, 0xC, 0xC, 0}, + {0xA2, 0x10, 0x10, 0}, + {0x10C, 0xC, 0xC, 0}, + {0x12C, 0x1, 0x1, 0}, + {0x140, 0x30, 0x30, 0}, + {0x142, 0x30, 0xFF, 0}, + {0x991, 0x11, 0xFF, 0}, + {0x196, 0x1, 0x1, 0}, + {0x197, 0x10, 0x10, 0}, + {0x19A, 0x1, 0x1, 0}, + {0x19B, 0x10, 0x10, 0}, + {0x217, 0x22, 0x22, 0}, + {0x219, 0x1F, 0x1F, 0}, + {0x223, 0x20, 0x20, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x988, 0x0, 0x20, 0}, + {0x98C, 0xB0, 0xFF, 0}, + {0x994, 0x0, 0xFF, 0}, + {0xA13, 0x10, 0x10, 0}, + {0xA1F, 0x80, 0x80, 0}, + {0x1452, 0x0, 0xFF, 0}, + {0x1457, 0x22, 0xFF, 0}, + {0x1458, 0x22, 0xFF, 0}, + {0x148A, 0x0, 0x3, 0}, + {0x148F, 0x2, 0x3, 0}, + {0x1492, 0x40, 0x70, 0}, + {0x150A, 0x0, 0x3, 0}, + {0x150F, 0x2, 0x3, 0}, + {0x1512, 0x40, 0x70, 0}, + {0x158A, 0x0, 0x3, 0}, + {0x158F, 0x2, 0x3, 0}, + {0x1592, 0x40, 0x70, 0}, + {0x160A, 0x0, 0x3, 0}, + {0x160F, 0x2, 0x3, 0}, + {0x1612, 0x40, 0x70, 0}, + {0x1729, 0x18, 0x18, 0}, + {0x17A9, 0x18, 0x18, 0}, + {0x1829, 0x18, 0x18, 0}, + {0x18A9, 0x18, 0x18, 0}, + {0x98, 0x2, 0x7, 0}, + {0xA1F, 0xC, 0xC, 0}, + {0xA21, 0x21, 0xFF, 0}, + {0xA23, 0xF0, 0xF0, 0}, + {0xA28, 0x20, 0xFF, 0}, + {0xA29, 0x20, 0xFF, 0}, + {0xA2A, 0x20, 0xFF, 0}, + {0xA2B, 0x20, 0xFF, 0}, + {0x1440, 0x0, 0xE, 0}, + {0x1487, 0x96, 0xFF, 0}, + {0x148A, 0xD, 0xF, 0}, + {0x148C, 0x3, 0x3, 0}, + {0x148D, 0x19, 0x7F, 0}, + {0x148E, 0x7, 0x7F, 0}, + {0x1490, 0x2, 0x3, 0}, + {0x1491, 0x19, 0x7F, 0}, + {0x1507, 0x96, 0xFF, 0}, + {0x150A, 0xD, 0xF, 0}, + {0x150C, 0x3, 0x3, 0}, + {0x150D, 0x19, 0x7F, 0}, + {0x150E, 0x7, 0x7F, 0}, + {0x1510, 0x2, 0x3, 0}, + {0x1511, 0x19, 0x7F, 0}, + {0x1587, 0x96, 0xFF, 0}, + {0x158A, 0xD, 0xF, 0}, + {0x158C, 0x3, 0x3, 0}, + {0x158D, 0x19, 0x7F, 0}, + {0x158E, 0x7, 0x7F, 0}, + {0x1590, 0x2, 0x3, 0}, + {0x1591, 0x19, 0x7F, 0}, + {0x1607, 0x96, 0xFF, 0}, + {0x160A, 0xD, 0xF, 0}, + {0x160C, 0x3, 0x3, 0}, + {0x160D, 0x19, 0x7F, 0}, + {0x160E, 0x7, 0x7F, 0}, + {0x1610, 0x2, 0x3, 0}, + {0x1611, 0x19, 0x7F, 0}, + {0x1688, 0x0, 0x1F, 0}, + {0x1689, 0x10, 0x7F, 0}, + {0x168A, 0x0, 0xFF, 0}, + {0x168B, 0x1, 0xFF, 0}, + {0x168C, 0x7, 0x3F, 0}, + {0x168D, 0x9, 0xFF, 0}, + {0x168E, 0xA0, 0xFF, 0}, + {0x1708, 0xD1, 0xFF, 0}, + {0x1709, 0xFC, 0xFF, 0}, + {0x170A, 0x92, 0xFF, 0}, + {0x170B, 0x0, 0x3, 0}, + {0x170C, 0x4C, 0x7F, 0}, + {0x170D, 0x0, 0x7F, 0}, + {0x170E, 0x30, 0x3F, 0}, + {0x170F, 0x9F, 0xFF, 0}, + {0x1710, 0x29, 0x3F, 0}, + {0x1711, 0x0, 0x3F, 0}, + {0x1712, 0x0, 0xFF, 0}, + {0x1713, 0x9C, 0x9C, 0}, + {0x1714, 0x1, 0x7F, 0}, + {0x1715, 0xFF, 0xFF, 0}, + {0x1716, 0x8E, 0xFF, 0}, + {0x1717, 0x3B, 0xFF, 0}, + {0x1718, 0x6A, 0xFF, 0}, + {0x1719, 0x80, 0xFF, 0}, + {0x171A, 0x8, 0x7F, 0}, + {0x171B, 0x1, 0x3F, 0}, + {0x171C, 0x3, 0xF, 0}, + {0x171D, 0x38, 0x7F, 0}, + {0x171E, 0xD, 0x1F, 0}, + {0x173B, 0x7, 0x1F, 0}, + {0x1788, 0xD1, 0xFF, 0}, + {0x1789, 0xFC, 0xFF, 0}, + {0x178A, 0x92, 0xFF, 0}, + {0x178B, 0x0, 0x3, 0}, + {0x178C, 0x4C, 0x7F, 0}, + {0x178D, 0x0, 0x7F, 0}, + {0x178E, 0x30, 0x3F, 0}, + {0x178F, 0x9F, 0xFF, 0}, + {0x1790, 0x29, 0x3F, 0}, + {0x1791, 0x0, 0x3F, 0}, + {0x1792, 0x0, 0xFF, 0}, + {0x1793, 0xDC, 0xDC, 0}, + {0x1794, 0x0, 0x3F, 0}, + {0x1795, 0xFF, 0xFF, 0}, + {0x1796, 0x8E, 0xFF, 0}, + {0x1797, 0x3B, 0xFF, 0}, + {0x1798, 0x6A, 0xFF, 0}, + {0x1799, 0x80, 0xFF, 0}, + {0x179A, 0x8, 0x7F, 0}, + {0x179B, 0x1, 0x3F, 0}, + {0x179C, 0x3, 0xF, 0}, + {0x179D, 0x38, 0x7F, 0}, + {0x179E, 0xD, 0x1F, 0}, + {0x17BB, 0x7, 0x1F, 0}, + {0x1808, 0xD1, 0xFF, 0}, + {0x1809, 0xFC, 0xFF, 0}, + {0x180A, 0x92, 0xFF, 0}, + {0x180B, 0x0, 0x3, 0}, + {0x180C, 0x4C, 0x7F, 0}, + {0x180D, 0x0, 0x7F, 0}, + {0x180E, 0x30, 0x3F, 0}, + {0x180F, 0x9F, 0xFF, 0}, + {0x1810, 0x29, 0x3F, 0}, + {0x1811, 0x0, 0x3F, 0}, + {0x1812, 0x0, 0xFF, 0}, + {0x1813, 0xDC, 0xDC, 0}, + {0x1814, 0x0, 0x3F, 0}, + {0x1815, 0xFF, 0xFF, 0}, + {0x1816, 0x8E, 0xFF, 0}, + {0x1817, 0x3B, 0xFF, 0}, + {0x1818, 0x6A, 0xFF, 0}, + {0x1819, 0x80, 0xFF, 0}, + {0x181A, 0x8, 0x7F, 0}, + {0x181B, 0x1, 0x3F, 0}, + {0x181C, 0x3, 0xF, 0}, + {0x181D, 0x38, 0x7F, 0}, + {0x181E, 0xD, 0x1F, 0}, + {0x183B, 0x7, 0x1F, 0}, + {0x1888, 0xD1, 0xFF, 0}, + {0x1889, 0xFC, 0xFF, 0}, + {0x188A, 0x92, 0xFF, 0}, + {0x188B, 0x0, 0x3, 0}, + {0x188C, 0x4C, 0x7F, 0}, + {0x188D, 0x0, 0x7F, 0}, + {0x188E, 0x30, 0x3F, 0}, + {0x188F, 0x9F, 0xFF, 0}, + {0x1890, 0x29, 0x3F, 0}, + {0x1891, 0x0, 0x3F, 0}, + {0x1892, 0x0, 0xFF, 0}, + {0x1893, 0xDC, 0xDC, 0}, + {0x1894, 0x0, 0x3F, 0}, + {0x1895, 0xFF, 0xFF, 0}, + {0x1896, 0x8E, 0xFF, 0}, + {0x1897, 0x3B, 0xFF, 0}, + {0x1898, 0x6A, 0xFF, 0}, + {0x1899, 0x80, 0xFF, 0}, + {0x189A, 0x8, 0x7F, 0}, + {0x189B, 0x1, 0x3F, 0}, + {0x189C, 0x3, 0xF, 0}, + {0x189D, 0x58, 0x7F, 0}, + {0x189E, 0xD, 0x1F, 0}, + {0x18BB, 0x7, 0x1F, 0}, + /* Add UVLO 2.0 setting */ + {0x999, 0x4, 0x7, 5}, + {0x99e, 0x1, 0x7, 3}, + /* Enable SPMI shutdown command */ + {0x136, 0x1, 0x1, 4}, + /* Enable magic key protection */ + {0x3B1, 0, 0xFF, 0}, + {0x3B2, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, + {0xA15, 0, 0xFF, 0}, + {0xA16, 0, 0xFF, 0}, + {0x141C, 0, 0xFF, 0}, + {0x141D, 0, 0xFF, 0}, + {0x3AA, 0, 0xFF, 0}, + {0x3AB, 0, 0xFF, 0}, +}; + +static const struct mt6316_setting init_setting_s8[] = { + /* Disable magic key protection */ + {0x3B1, 0xE9, 0xFF, 0}, + {0x3B2, 0xE6, 0xFF, 0}, + {0x3A8, 0xE9, 0xFF, 0}, + {0x3A9, 0xE6, 0xFF, 0}, + {0xA15, 0x29, 0xFF, 0}, + {0xA16, 0x47, 0xFF, 0}, + {0x141C, 0x43, 0xFF, 0}, + {0x141D, 0x55, 0xFF, 0}, + {0x3AA, 0xDC, 0xFF, 0}, + {0x3AB, 0xF1, 0xFF, 0}, + /* Init setting */ + {0x13, 0x7, 0xFF, 0}, + {0x16, 0x12, 0xFF, 0}, + {0x17, 0x0, 0xFF, 0}, + {0x8A, 0x6, 0xF, 0}, + {0xA1, 0xC, 0xC, 0}, + {0xA2, 0x10, 0x10, 0}, + {0x10C, 0xC, 0xC, 0}, + {0x12C, 0x1, 0x1, 0}, + {0x140, 0x30, 0x30, 0}, + {0x142, 0x30, 0xFF, 0}, + {0x991, 0x11, 0xFF, 0}, + {0x196, 0x1, 0x1, 0}, + {0x197, 0x10, 0x10, 0}, + {0x19A, 0x1, 0x1, 0}, + {0x19B, 0x10, 0x10, 0}, + {0x217, 0x22, 0x22, 0}, + {0x219, 0x1F, 0x1F, 0}, + {0x223, 0x20, 0x20, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x988, 0x0, 0x20, 0}, + {0x98C, 0xB0, 0xFF, 0}, + {0x994, 0x0, 0xFF, 0}, + {0xA13, 0x10, 0x10, 0}, + {0xA1F, 0x80, 0x80, 0}, + {0x1452, 0x0, 0xFF, 0}, + {0x1457, 0x22, 0xFF, 0}, + {0x1458, 0x22, 0xFF, 0}, + {0x148A, 0x0, 0x3, 0}, + {0x148F, 0x2, 0x3, 0}, + {0x1492, 0x40, 0x70, 0}, + {0x150A, 0x0, 0x3, 0}, + {0x150F, 0x2, 0x3, 0}, + {0x1512, 0x40, 0x70, 0}, + {0x158A, 0x0, 0x3, 0}, + {0x158F, 0x2, 0x3, 0}, + {0x1592, 0x40, 0x70, 0}, + {0x160A, 0x0, 0x3, 0}, + {0x160F, 0x2, 0x3, 0}, + {0x1612, 0x40, 0x70, 0}, + {0x1729, 0x18, 0x18, 0}, + {0x17A9, 0x18, 0x18, 0}, + {0x1829, 0x18, 0x18, 0}, + {0x18A9, 0x18, 0x18, 0}, + {0xA18, 0x1, 0x1, 0}, + {0xA19, 0x2, 0xFF, 0}, + {0xA1A, 0x0, 0xFF, 0}, + {0xA1B, 0x0, 0xFF, 0}, + {0xA1C, 0x2, 0xFF, 0}, + {0xA1D, 0x2, 0xFF, 0}, + {0xA1F, 0xC, 0xC, 0}, + {0xA21, 0x1E, 0xFF, 0}, + {0xA23, 0xF0, 0xF0, 0}, + {0xA28, 0x1, 0xFF, 0}, + {0xA29, 0x1, 0xFF, 0}, + {0xA2A, 0x1E, 0xFF, 0}, + {0xA2B, 0x1E, 0xFF, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x96, 0xFF, 0}, + {0x148A, 0xF, 0xF, 0}, + {0x148C, 0x3, 0x3, 0}, + {0x148D, 0xD, 0x7F, 0}, + {0x148E, 0x7, 0x7F, 0}, + {0x1490, 0x2, 0x3, 0}, + {0x1491, 0x19, 0x7F, 0}, + {0x1507, 0x96, 0xFF, 0}, + {0x150A, 0xF, 0xF, 0}, + {0x150D, 0xD, 0x7F, 0}, + {0x150E, 0x7, 0x7F, 0}, + {0x1510, 0x2, 0x3, 0}, + {0x1511, 0x19, 0x7F, 0}, + {0x1587, 0x55, 0xFF, 0}, + {0x158A, 0xF, 0xF, 0}, + {0x158C, 0x7, 0x7, 0}, + {0x158D, 0x28, 0x7F, 0}, + {0x158E, 0x7, 0x7F, 0}, + {0x1590, 0x2, 0x3, 0}, + {0x1591, 0x19, 0x7F, 0}, + {0x1607, 0x55, 0xFF, 0}, + {0x160A, 0xF, 0xF, 0}, + {0x160C, 0x7, 0x7, 0}, + {0x160D, 0x28, 0x7F, 0}, + {0x160E, 0x7, 0x7F, 0}, + {0x1610, 0x2, 0x3, 0}, + {0x1611, 0x19, 0x7F, 0}, + {0x1688, 0x0, 0x1F, 0}, + {0x1689, 0x50, 0x7F, 0}, + {0x168A, 0xA2, 0xFF, 0}, + {0x168B, 0x1, 0xFF, 0}, + {0x168C, 0x5, 0x3F, 0}, + {0x168D, 0xF, 0xFF, 0}, + {0x168E, 0x23, 0xFF, 0}, + {0x1708, 0xD1, 0xFF, 0}, + {0x1709, 0xAC, 0xFF, 0}, + {0x170A, 0x92, 0xFF, 0}, + {0x170B, 0x0, 0x3, 0}, + {0x170C, 0x48, 0x7F, 0}, + {0x170D, 0x8, 0x7F, 0}, + {0x170E, 0x30, 0x3F, 0}, + {0x170F, 0x4F, 0xFF, 0}, + {0x1710, 0x24, 0x3F, 0}, + {0x1711, 0x0, 0x3F, 0}, + {0x1712, 0x0, 0xFF, 0}, + {0x1713, 0x9C, 0x9C, 0}, + {0x1714, 0x41, 0x7F, 0}, + {0x1715, 0xEF, 0xFF, 0}, + {0x1716, 0x9C, 0xFF, 0}, + {0x1717, 0x1B, 0xFF, 0}, + {0x1718, 0xDE, 0xFF, 0}, + {0x1719, 0x86, 0xFF, 0}, + {0x171A, 0x8, 0x7F, 0}, + {0x171B, 0xB, 0x3F, 0}, + {0x171C, 0x3, 0xF, 0}, + {0x171D, 0x59, 0x7F, 0}, + {0x171E, 0x19, 0x1F, 0}, + {0x1734, 0x7, 0x3F, 0}, + {0x173A, 0x1A, 0x1F, 0}, + {0x1788, 0xD9, 0xFF, 0}, + {0x1789, 0xBF, 0xFF, 0}, + {0x178A, 0x92, 0xFF, 0}, + {0x178B, 0x0, 0x3, 0}, + {0x178C, 0x54, 0x7F, 0}, + {0x178D, 0x28, 0x7F, 0}, + {0x178E, 0x30, 0x3F, 0}, + {0x178F, 0x9F, 0xFF, 0}, + {0x1790, 0x9, 0x3F, 0}, + {0x1791, 0x0, 0x3F, 0}, + {0x1792, 0x0, 0xFF, 0}, + {0x1793, 0xDC, 0xDC, 0}, + {0x1794, 0x24, 0x3F, 0}, + {0x1795, 0xFF, 0xFF, 0}, + {0x1796, 0x8E, 0xFF, 0}, + {0x1797, 0x1B, 0xFF, 0}, + {0x1798, 0xAA, 0xFF, 0}, + {0x1799, 0x83, 0xFF, 0}, + {0x179A, 0x8, 0x7F, 0}, + {0x179B, 0x1, 0x3F, 0}, + {0x179C, 0x3, 0xF, 0}, + {0x179D, 0x0, 0x7F, 0}, + {0x179E, 0x9, 0x1F, 0}, + {0x17BA, 0x1A, 0x1F, 0}, + {0x1808, 0xD1, 0xFF, 0}, + {0x1809, 0xAC, 0xFF, 0}, + {0x180A, 0x92, 0xFF, 0}, + {0x180B, 0x0, 0x3, 0}, + {0x180C, 0x48, 0x7F, 0}, + {0x180D, 0x8, 0x7F, 0}, + {0x180E, 0x30, 0x3F, 0}, + {0x180F, 0x4F, 0xFF, 0}, + {0x1810, 0x24, 0x3F, 0}, + {0x1811, 0x0, 0x3F, 0}, + {0x1812, 0x0, 0xFF, 0}, + {0x1813, 0xDC, 0xDC, 0}, + {0x1814, 0x20, 0x3F, 0}, + {0x1815, 0xEF, 0xFF, 0}, + {0x1816, 0x9C, 0xFF, 0}, + {0x1817, 0x1B, 0xFF, 0}, + {0x1818, 0xDE, 0xFF, 0}, + {0x1819, 0x86, 0xFF, 0}, + {0x181A, 0x8, 0x7F, 0}, + {0x181B, 0xB, 0x3F, 0}, + {0x181C, 0x3, 0xF, 0}, + {0x181D, 0x59, 0x7F, 0}, + {0x181E, 0x19, 0x1F, 0}, + {0x1834, 0x7, 0x3F, 0}, + {0x183A, 0x1A, 0x1F, 0}, + {0x1888, 0xD9, 0xFF, 0}, + {0x1889, 0xBF, 0xFF, 0}, + {0x188A, 0x92, 0xFF, 0}, + {0x188B, 0x0, 0x3, 0}, + {0x188C, 0x54, 0x7F, 0}, + {0x188D, 0x28, 0x7F, 0}, + {0x188E, 0x30, 0x3F, 0}, + {0x188F, 0x9F, 0xFF, 0}, + {0x1890, 0x9, 0x3F, 0}, + {0x1891, 0x0, 0x3F, 0}, + {0x1892, 0x0, 0xFF, 0}, + {0x1893, 0xDC, 0xDC, 0}, + {0x1894, 0x24, 0x3F, 0}, + {0x1895, 0xFF, 0xFF, 0}, + {0x1896, 0x8E, 0xFF, 0}, + {0x1897, 0x1B, 0xFF, 0}, + {0x1898, 0xAA, 0xFF, 0}, + {0x1899, 0x83, 0xFF, 0}, + {0x189A, 0x8, 0x7F, 0}, + {0x189B, 0x1, 0x3F, 0}, + {0x189C, 0x3, 0xF, 0}, + {0x189D, 0x0, 0x7F, 0}, + {0x189E, 0x9, 0x1F, 0}, + {0x18BA, 0x1A, 0x1F, 0}, + /* Add UVLO 2.0 setting */ + {0x999, 0x4, 0x7, 5}, + {0x99e, 0x1, 0x7, 3}, + /* Enable SPMI shutdown command */ + {0x136, 0x1, 0x1, 4}, + /* Enable magic key protection */ + {0x3B1, 0, 0xFF, 0}, + {0x3B2, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, + {0xA15, 0, 0xFF, 0}, + {0xA16, 0, 0xFF, 0}, + {0x141C, 0, 0xFF, 0}, + {0x141D, 0, 0xFF, 0}, + {0x3AA, 0, 0xFF, 0}, + {0x3AB, 0, 0xFF, 0}, +}; + +/* KP(VCPUB + DREQ) */ +static const struct mt6316_setting init_setting_s15[] = { + /* Disable magic key protection */ + {0x3B1, 0xE9, 0xFF, 0}, + {0x3B2, 0xE6, 0xFF, 0}, + {0x3A8, 0xE9, 0xFF, 0}, + {0x3A9, 0xE6, 0xFF, 0}, + {0xA15, 0x29, 0xFF, 0}, + {0xA16, 0x47, 0xFF, 0}, + {0x141C, 0x43, 0xFF, 0}, + {0x141D, 0x55, 0xFF, 0}, + {0x3AA, 0xDC, 0xFF, 0}, + {0x3AB, 0xF1, 0xFF, 0}, + /* Init setting */ + {0x13, 0x7, 0xFF, 0}, + {0x16, 0x12, 0xFF, 0}, + {0x17, 0x0, 0xFF, 0}, + {0x8A, 0x6, 0xF, 0}, + {0xA1, 0xC, 0xC, 0}, + {0xA2, 0x10, 0x10, 0}, + {0x10C, 0xC, 0xC, 0}, + {0x12C, 0x1, 0x1, 0}, + {0x140, 0x30, 0x30, 0}, + {0x142, 0x30, 0xFF, 0}, + {0x991, 0x11, 0xFF, 0}, + {0x196, 0x1, 0x1, 0}, + {0x197, 0x10, 0x10, 0}, + {0x19A, 0x1, 0x1, 0}, + {0x19B, 0x10, 0x10, 0}, + {0x217, 0x22, 0x22, 0}, + {0x219, 0x1F, 0x1F, 0}, + {0x223, 0x20, 0x20, 0}, + {0x413, 0x7, 0xFF, 0}, + {0x416, 0x12, 0xFF, 0}, + {0x417, 0x0, 0x7, 0}, + {0x988, 0x0, 0x20, 0}, + {0x98C, 0xB0, 0xFF, 0}, + {0x994, 0x0, 0xFF, 0}, + {0xA13, 0x10, 0x10, 0}, + {0xA1F, 0x80, 0x80, 0}, + {0x1452, 0x0, 0xFF, 0}, + {0x1457, 0x22, 0xFF, 0}, + {0x1458, 0x22, 0xFF, 0}, + {0x148A, 0x0, 0x3, 0}, + {0x148F, 0x2, 0x3, 0}, + {0x1492, 0x40, 0x70, 0}, + {0x150A, 0x0, 0x3, 0}, + {0x150F, 0x2, 0x3, 0}, + {0x1512, 0x40, 0x70, 0}, + {0x158A, 0x0, 0x3, 0}, + {0x158F, 0x2, 0x3, 0}, + {0x1592, 0x40, 0x70, 0}, + {0x160A, 0x0, 0x3, 0}, + {0x160F, 0x2, 0x3, 0}, + {0x1612, 0x40, 0x70, 0}, + {0x1729, 0x18, 0x18, 0}, + {0x17A9, 0x18, 0x18, 0}, + {0x1829, 0x18, 0x18, 0}, + {0x18A9, 0x18, 0x18, 0}, + {0x98, 0x2, 0x7, 0}, + {0xA1F, 0xC, 0xC, 0}, + {0xA21, 0x21, 0xFF, 0}, + {0xA23, 0xF0, 0xF0, 0}, + {0xA28, 0x1A, 0xFF, 0}, + {0xA29, 0x1A, 0xFF, 0}, + {0xA2A, 0x18, 0xFF, 0}, + {0xA2B, 0x1A, 0xFF, 0}, + {0x1440, 0x0, 0xA, 0}, + {0x1487, 0x55, 0xFF, 0}, + {0x148A, 0xD, 0xF, 0}, + {0x148C, 0x3, 0x3, 0}, + {0x148D, 0x28, 0x7F, 0}, + {0x148E, 0x7, 0x7F, 0}, + {0x1490, 0x2, 0x3, 0}, + {0x1491, 0x19, 0x7F, 0}, + {0x1507, 0x55, 0xFF, 0}, + {0x150A, 0xD, 0xF, 0}, + {0x150C, 0x3, 0x3, 0}, + {0x150D, 0x28, 0x7F, 0}, + {0x150E, 0x7, 0x7F, 0}, + {0x1510, 0x2, 0x3, 0}, + {0x1511, 0x19, 0x7F, 0}, + {0x1587, 0x96, 0xFF, 0}, + {0x158A, 0xD, 0xF, 0}, + {0x158D, 0xD, 0x7F, 0}, + {0x158E, 0x7, 0x7F, 0}, + {0x1590, 0x2, 0x3, 0}, + {0x1591, 0x19, 0x7F, 0}, + {0x1607, 0x55, 0xFF, 0}, + {0x160A, 0xD, 0xF, 0}, + {0x160C, 0x3, 0x3, 0}, + {0x160D, 0x28, 0x7F, 0}, + {0x160E, 0x7, 0x7F, 0}, + {0x1610, 0x2, 0x3, 0}, + {0x1611, 0x19, 0x7F, 0}, + {0x1688, 0x0, 0x1F, 0}, + {0x1689, 0x10, 0x7F, 0}, + {0x168A, 0x0, 0xFF, 0}, + {0x168B, 0x1, 0xFF, 0}, + {0x168C, 0x5, 0x3F, 0}, + {0x168D, 0xB, 0xFF, 0}, + {0x168E, 0xA0, 0xFF, 0}, + {0x1708, 0xD1, 0xFF, 0}, + {0x1709, 0xFC, 0xFF, 0}, + {0x170A, 0x92, 0xFF, 0}, + {0x170B, 0x0, 0x3, 0}, + {0x170C, 0x4C, 0x7F, 0}, + {0x170D, 0x0, 0x7F, 0}, + {0x170E, 0x30, 0x3F, 0}, + {0x170F, 0x9F, 0xFF, 0}, + {0x1710, 0x29, 0x3F, 0}, + {0x1711, 0x0, 0x3F, 0}, + {0x1712, 0x0, 0xFF, 0}, + {0x1713, 0x9C, 0x9C, 0}, + {0x1714, 0x1, 0x7F, 0}, + {0x1715, 0xFF, 0xFF, 0}, + {0x1716, 0x8E, 0xFF, 0}, + {0x1717, 0x3B, 0xFF, 0}, + {0x1718, 0x6A, 0xFF, 0}, + {0x1719, 0x80, 0xFF, 0}, + {0x171A, 0x8, 0x7F, 0}, + {0x171B, 0x1, 0x3F, 0}, + {0x171C, 0x3, 0xF, 0}, + {0x171D, 0x58, 0x7F, 0}, + {0x171E, 0xD, 0x1F, 0}, + {0x173B, 0x7, 0x1F, 0}, + {0x1788, 0xD1, 0xFF, 0}, + {0x1789, 0xFC, 0xFF, 0}, + {0x178A, 0x92, 0xFF, 0}, + {0x178B, 0x0, 0x3, 0}, + {0x178C, 0x4C, 0x7F, 0}, + {0x178D, 0x0, 0x7F, 0}, + {0x178E, 0x30, 0x3F, 0}, + {0x178F, 0x9F, 0xFF, 0}, + {0x1790, 0x29, 0x3F, 0}, + {0x1791, 0x0, 0x3F, 0}, + {0x1792, 0x0, 0xFF, 0}, + {0x1793, 0xDC, 0xDC, 0}, + {0x1794, 0x0, 0x3F, 0}, + {0x1795, 0xFF, 0xFF, 0}, + {0x1796, 0x8E, 0xFF, 0}, + {0x1797, 0x3B, 0xFF, 0}, + {0x1798, 0x6A, 0xFF, 0}, + {0x1799, 0x80, 0xFF, 0}, + {0x179A, 0x8, 0x7F, 0}, + {0x179B, 0x1, 0x3F, 0}, + {0x179C, 0x3, 0xF, 0}, + {0x179D, 0x58, 0x7F, 0}, + {0x179E, 0xD, 0x1F, 0}, + {0x17BB, 0x7, 0x1F, 0}, + {0x1808, 0xF1, 0xFF, 0}, + {0x1809, 0xEC, 0xFF, 0}, + {0x180A, 0x92, 0xFF, 0}, + {0x180B, 0x0, 0x3, 0}, + {0x180C, 0x54, 0x7F, 0}, + {0x180D, 0x0, 0x7F, 0}, + {0x180E, 0x10, 0x3F, 0}, + {0x180F, 0x9F, 0xFF, 0}, + {0x1810, 0x29, 0x3F, 0}, + {0x1811, 0x0, 0x3F, 0}, + {0x1812, 0x0, 0xFF, 0}, + {0x1813, 0xDC, 0xDC, 0}, + {0x1814, 0x0, 0x3F, 0}, + {0x1815, 0xEF, 0xFF, 0}, + {0x1816, 0x8C, 0xFF, 0}, + {0x1817, 0x13, 0xFF, 0}, + {0x1818, 0xE2, 0xFF, 0}, + {0x1819, 0x81, 0xFF, 0}, + {0x181A, 0x1, 0x7F, 0}, + {0x181B, 0x0, 0x3F, 0}, + {0x181C, 0x3, 0xF, 0}, + {0x181D, 0x39, 0x7F, 0}, + {0x181E, 0x15, 0x1F, 0}, + {0x1888, 0xD1, 0xFF, 0}, + {0x1889, 0xFC, 0xFF, 0}, + {0x188A, 0x92, 0xFF, 0}, + {0x188B, 0x0, 0x3, 0}, + {0x188C, 0x4C, 0x7F, 0}, + {0x188D, 0x0, 0x7F, 0}, + {0x188E, 0x30, 0x3F, 0}, + {0x188F, 0x9F, 0xFF, 0}, + {0x1890, 0x29, 0x3F, 0}, + {0x1891, 0x0, 0x3F, 0}, + {0x1892, 0x0, 0xFF, 0}, + {0x1893, 0xDC, 0xDC, 0}, + {0x1894, 0x0, 0x3F, 0}, + {0x1895, 0xFF, 0xFF, 0}, + {0x1896, 0x8E, 0xFF, 0}, + {0x1897, 0x3B, 0xFF, 0}, + {0x1898, 0x6A, 0xFF, 0}, + {0x1899, 0x80, 0xFF, 0}, + {0x189A, 0x8, 0x7F, 0}, + {0x189B, 0x1, 0x3F, 0}, + {0x189C, 0x3, 0xF, 0}, + {0x189D, 0x58, 0x7F, 0}, + {0x189E, 0xD, 0x1F, 0}, + {0x18BB, 0x7, 0x1F, 0}, + /* Add UVLO 2.0 setting */ + {0x999, 0x4, 0x7, 5}, + {0x99e, 0x1, 0x7, 3}, + /* Enable SPMI shutdown command */ + {0x136, 0x1, 0x1, 4}, + /* Enable magic key protection */ + {0x3B1, 0, 0xFF, 0}, + {0x3B2, 0, 0xFF, 0}, + {0x3A8, 0, 0xFF, 0}, + {0x3A9, 0, 0xFF, 0}, + {0xA15, 0, 0xFF, 0}, + {0xA16, 0, 0xFF, 0}, + {0x141C, 0, 0xFF, 0}, + {0x141D, 0, 0xFF, 0}, + {0x3AA, 0, 0xFF, 0}, + {0x3AB, 0, 0xFF, 0}, +}; + +void mt6316_init_setting(void) +{ + for (int i = 0; i < ARRAY_SIZE(init_setting_s8); i++) + mt6316_write_field(SPMI_SLAVE_8, + init_setting_s8[i].addr, init_setting_s8[i].val, + init_setting_s8[i].mask, init_setting_s8[i].shift); + printk(BIOS_INFO, "%s S8 done\n", __func__); + + for (int i = 0; i < ARRAY_SIZE(init_setting_s6); i++) + mt6316_write_field(SPMI_SLAVE_6, + init_setting_s6[i].addr, init_setting_s6[i].val, + init_setting_s6[i].mask, init_setting_s6[i].shift); + printk(BIOS_INFO, "%s S6 done\n", __func__); + + for (int i = 0; i < ARRAY_SIZE(init_setting_s7); i++) + mt6316_write_field(SPMI_SLAVE_7, + init_setting_s7[i].addr, init_setting_s7[i].val, + init_setting_s7[i].mask, init_setting_s7[i].shift); + printk(BIOS_INFO, "%s S7 done\n", __func__); + + for (int i = 0; i < ARRAY_SIZE(init_setting_s15); i++) + mt6316_write_field(SPMI_SLAVE_15, + init_setting_s15[i].addr, init_setting_s15[i].val, + init_setting_s15[i].mask, init_setting_s15[i].shift); + printk(BIOS_INFO, "%s S15 done\n", __func__); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/85630?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I39e91d64e77cff03281845dfbea565e6ddf748f6 Gerrit-Change-Number: 85630 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hope Wang <hope.wang(a)mediatek.corp-partner.google.com>

1 0

[S] Change in coreboot[main]: cbfs: Add COREBOOTB as backup region for A/B recovery
by Bao Zheng (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Julius Werner, Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85629?usp=email to review the following change. Change subject: cbfs: Add COREBOOTB as backup region for A/B recovery ...................................................................... cbfs: Add COREBOOTB as backup region for A/B recovery Change-Id: I019af6fbeca46e0e35d739a028655051fb466b48 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/lib/cbfs.c 1 file changed, 9 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/85629/1 diff --git a/src/lib/cbfs.c b/src/lib/cbfs.c index 03624bf..84ba894 100644 --- a/src/lib/cbfs.c +++ b/src/lib/cbfs.c @@ -19,6 +19,7 @@ #include <symbols.h> #include <thread.h> #include <timestamp.h> +#include <soc/amd/common/block/psp/psp_def.h> #if ENV_X86 && (ENV_POSTCAR || ENV_SMM) struct mem_pool cbfs_cache = MEM_POOL_INIT(NULL, 0, 0); @@ -181,6 +182,8 @@ && vboot_logic_executed()) vboot_fail_and_reboot(vboot_get_context(), VB2_RECOVERY_FW_BODY, rv); + if (CONFIG(PSP_AB_RECOVERY)) + toggle_bootpartition(); return true; } } @@ -685,8 +688,12 @@ if (region_device_sz(&ro.rdev)) return &ro; - if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev)) - die("Cannot locate primary CBFS"); + if (CONFIG(PSP_AB_RECOVERY)) { + abrecovery_locate_area_as_rdev(&ro.rdev); + } else { + if (fmap_locate_area_as_rdev("COREBOOT", &ro.rdev)) + die("Cannot locate primary CBFS"); + } if (ENV_INITIAL_STAGE) { enum cb_err err = cbfs_init_boot_device(&ro, metadata_hash_get()); -- To view, visit https://review.coreboot.org/c/coreboot/+/85629?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I019af6fbeca46e0e35d739a028655051fb466b48 Gerrit-Change-Number: 85629 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Zheng Bao

1 0

[S] Change in coreboot[main]: cbfstool: Do not compress the BIOS binary if A/B recovery
by Bao Zheng (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Zheng Bao. Hello Zheng Bao, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/85628?usp=email to review the following change. Change subject: cbfstool: Do not compress the BIOS binary if A/B recovery ...................................................................... cbfstool: Do not compress the BIOS binary if A/B recovery Change-Id: I10db7ad44d2a92c143f46d9ee6fc7824b2ff0cc6 Signed-off-by: Zheng Bao <fishbaozi(a)gmail.com> --- M src/soc/amd/cezanne/Makefile.mk M util/cbfstool/amdcompress.c 2 files changed, 24 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/85628/1 diff --git a/src/soc/amd/cezanne/Makefile.mk b/src/soc/amd/cezanne/Makefile.mk index 2747622..3983aaa 100644 --- a/src/soc/amd/cezanne/Makefile.mk +++ b/src/soc/amd/cezanne/Makefile.mk @@ -183,6 +183,8 @@ OPT_SPL_TABLE_FILE=$(call add_opt_prefix, $(SPL_TABLE_FILE), --spl-table) OPT_RECOVERY_AB=$(call add_opt_prefix, $(CONFIG_PSP_RECOVERY_AB), --recovery-ab) +OPT_BIOS_AMDCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --elfcopy, --compress) +OPT_BIOS_FWCOMPRESS=$(if $(CONFIG_CBFS_VERIFICATION), --bios-bin-uncomp) AMDFW_COMMON_ARGS=$(OPT_PSP_APCB_FILES) \ $(OPT_PSP_NVRAM_BASE) \ @@ -227,6 +229,7 @@ $(OPT_APOB_NV_BASE) \ $(OPT_VERSTAGE_FILE) \ $(OPT_VERSTAGE_SIG_FILE) \ + $(OPT_BIOS_FWCOMPRESS) \ --location $(CONFIG_AMD_FWM_POSITION) \ --multilevel \ --output $@ @@ -234,7 +237,7 @@ $(PSP_BIOSBIN_FILE): $(PSP_ELF_FILE) $(AMDCOMPRESS) rm -f $@ @printf " AMDCOMPRS $(subst $(obj)/,,$(@))\n" - $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ --compress \ + $(AMDCOMPRESS) --infile $(PSP_ELF_FILE) --outfile $@ $(OPT_BIOS_AMDCOMPRESS) \ --maxsize $(PSP_BIOSBIN_SIZE) $(obj)/amdfw_a.rom: $(obj)/amdfw.rom diff --git a/util/cbfstool/amdcompress.c b/util/cbfstool/amdcompress.c index 76089ea..57725ca 100644 --- a/util/cbfstool/amdcompress.c +++ b/util/cbfstool/amdcompress.c @@ -17,6 +17,7 @@ #define DIR_UNDEF 0 #define DIR_COMP 1 #define DIR_UNCOMP 2 +#define DIR_COPY 3 typedef struct _header { uint32_t rsvd1[5]; @@ -32,6 +33,7 @@ {"compress", no_argument, 0, 'c' }, {"maxsize", required_argument, 0, 'm' }, {"uncompress", no_argument, 0, 'u' }, + {"elfcopy", no_argument, 0, 'p' }, {"help", no_argument, 0, 'h' }, }; @@ -135,7 +137,7 @@ * | ... | * n +------------------------------+ */ -static void do_compress(char *outf, char *inf, size_t max_size) +static void do_process(char *outf, char *inf, size_t max_size, int with_compress) { int out_fd, in_fd; struct buffer inbf, outbf; @@ -182,6 +184,15 @@ goto out_free_in; } + if (!with_compress) { + err = 0; + if (write(out_fd, inbf.data, inbf.size) != (ssize_t)(inbf.size)) { + printf("\tError writing to %s\n", outf); + err = 1; + } + goto out_free_in; + } + outbf.size = inbf.size; /* todo: tbd worst case? */ outbf.size += sizeof(header); outbf.data = calloc(outbf.size, 1); @@ -328,6 +339,11 @@ usage(); direction = DIR_COMP; break; + case 'p': + if (direction != DIR_UNDEF) + usage(); + direction = DIR_COPY; + break; case 'u': if (direction != DIR_UNDEF) usage(); @@ -344,7 +360,9 @@ usage(); if (direction == DIR_COMP) - do_compress(outf, inf, max_size); + do_process(outf, inf, max_size, 1); + else if (direction == DIR_COPY) + do_process(outf, inf, max_size, 0); else do_uncompress(outf, inf, max_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/85628?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10db7ad44d2a92c143f46d9ee6fc7824b2ff0cc6 Gerrit-Change-Number: 85628 Gerrit-PatchSet: 1 Gerrit-Owner: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Zheng Bao Gerrit-Attention: Zheng Bao

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