coreboot-gerrit December 2024

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[S] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Lean Sheng Tan (Code Review) 17 Dec '24

17 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... cpu/intel/car/romstage: Fix false-positive stack corruption Fix regression introduced in commit 03518727313119a8c7a273eb745663c99f8e4d22 ("arch/x86: Add breakpoint to stack canary"). romstage_main writes to the stack-canary, but since that's expected temporarily disable the breakpoint. This only caused a warning on platforms that do select IDT_IN_EVERY_STAGE, since those install the stack canary breakpoint. TEST: No more exceptions are printed in romstage when IDT_IN_EVERY_STAGE is enabled. Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85568 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> Reviewed-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> --- M src/cpu/intel/car/romstage.c 1 file changed, 18 insertions(+), 0 deletions(-) Approvals: Angel Pons: Looks good to me, approved Shuo Liu: Looks good to me, approved build bot (Jenkins): Verified Lean Sheng Tan: Looks good to me, approved diff --git a/src/cpu/intel/car/romstage.c b/src/cpu/intel/car/romstage.c index 7df512d..63a83ab 100644 --- a/src/cpu/intel/car/romstage.c +++ b/src/cpu/intel/car/romstage.c @@ -3,6 +3,7 @@ #include <adainit.h> #include <arch/romstage.h> #include <arch/symbols.h> +#include <arch/stack_canary_breakpoint.h> #include <commonlib/helpers.h> #include <console/console.h> #include <cpu/x86/smm.h> @@ -35,9 +36,26 @@ stack_base = (u32 *)(_ecar_stack - size); + /* Disable breakpoint since stack is intentionally corrupted */ + stack_canary_breakpoint_remove(); + + /* + * The "stack guard" and the "stack canary breakpoint" can both detect excessive + * stack usage. Excessive stack usage can corrupt data and lead to undefined + * (and thus hard to debug) behaviour. + * The stack guard will be checked later on, assuming the corruption wasn't to + * severe and allowed romstage to run. It's useful to detect problems when + * HW breakpoints were disabled. + * + * When HW breakpoints are used and enabled, the stack canary breakpoint will + * report the instruction pointer immediately, which can hint at which function + * may be using too much stack. FSP might disable HW breakpoints, though. + */ for (i = 0; i < num_guards; i++) stack_base[i] = stack_guard; + stack_canary_breakpoint_init(); + if (CONFIG(VBOOT_EARLY_EC_SYNC)) vboot_sync_ec(); -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 5 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com>

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[S] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Lean Sheng Tan (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Jérémy Compostella, Patrick Rudolph, Subrata Banik, Uwe Poeche, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Only comment changes from previous patchset and has 3 +2. so will merge this. -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 17:36:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: cpu/intel/car/romstage: Fix false-positive stack corruption
by Lean Sheng Tan (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Jérémy Compostella, Patrick Rudolph, Subrata Banik, Uwe Poeche, yuchi.chen(a)intel.com. Lean Sheng Tan has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85568?usp=email ) Change subject: cpu/intel/car/romstage: Fix false-positive stack corruption ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7ebf0a5e8eaad49af77ab4d5f6b58fc849013b14 Gerrit-Change-Number: 85568 Gerrit-PatchSet: 4 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: siemens-bot Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Uwe Poeche <uwe.poeche(a)siemens.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 17:35:39 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Wait for BMC
by Lean Sheng Tan (Code Review) 17 Dec '24

17 Dec '24

Lean Sheng Tan has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85492?usp=email ) Change subject: mb/ocp/tiogapass: Wait for BMC ...................................................................... mb/ocp/tiogapass: Wait for BMC The mainboard code relies on IPMI communication with the BMC. Since the x86 and BMC start booting at the same time on ACPI G3 exit and the x86 is a bit faster, wait for the BMC to signal it's done booting by pulling GPP_F4 low. Fixes lots of error messages in coreboot about not working IPMI: [ERROR] wait_ibf timeout! [ERROR] IPMI START WRITE failed [ERROR] ipmi_kcs_send_message failed TEST: Once GPP_F4 is low IPMI communication over the KCS is also working on ocp/tiogapass. The log contains the line: [DEBUG] BMC ready after 125560 ms Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85492 Reviewed-by: Angel Pons <th3fanbus(a)gmail.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h M src/mainboard/ocp/tiogapass/romstage.c 2 files changed, 29 insertions(+), 1 deletion(-) Approvals: Angel Pons: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h index ac4422a..27ae3d4 100644 --- a/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h +++ b/src/mainboard/ocp/tiogapass/include/tp_pch_gpio.h @@ -5,6 +5,8 @@ #include <soc/gpio.h> +#define GPIO_BMC_READY_N GPP_F4 + /* Pad configuration table for C621 Lewisburg PCH */ static const struct pad_config gpio_table[] = { /* ------- GPIO Community 0 ------- */ @@ -116,7 +118,7 @@ PAD_CFG_GPI_TRIG_OWN(GPP_F2, NONE, DEEP, OFF, DRIVER), /* GPP_F3 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F3, NONE, DEEP, OFF, DRIVER), - /* GPP_F4 - GPIO */ + /* GPP_F4 - BMC_READY_N */ PAD_CFG_GPI_TRIG_OWN(GPP_F4, NONE, DEEP, OFF, DRIVER), /* GPP_F5 - GPIO */ PAD_CFG_GPI_TRIG_OWN(GPP_F5, NONE, DEEP, OFF, DRIVER), diff --git a/src/mainboard/ocp/tiogapass/romstage.c b/src/mainboard/ocp/tiogapass/romstage.c index 283d5f1..276285a 100644 --- a/src/mainboard/ocp/tiogapass/romstage.c +++ b/src/mainboard/ocp/tiogapass/romstage.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ +#include <delay.h> #include <drivers/ipmi/ipmi_if.h> #include <drivers/ipmi/ocp/ipmi_ocp.h> #include <fsp/api.h> @@ -10,8 +11,10 @@ #include <soc/romstage.h> #include <string.h> #include <skxsp_tp_iio.h> +#include <timer.h> #include "ipmi.h" +#include "tp_pch_gpio.h" static uint8_t iio_table_buf[sizeof(tp_iio_bifur_table)]; @@ -52,8 +55,31 @@ oem_update_iio(mupd); } +static void mainboard_wait_for_bmc_ready(void) +{ + struct stopwatch sw; + static const long timeout_ms = 300 * 1000; + + printk(BIOS_DEBUG, "Waiting for BMC ready\n"); + gpio_input(GPIO_BMC_READY_N); + + stopwatch_init_msecs_expire(&sw, timeout_ms); + while (gpio_get(GPIO_BMC_READY_N)) { + if (stopwatch_expired(&sw)) { + printk(BIOS_WARNING, + "BMC not ready after %ld ms. Abort.\n", timeout_ms); + return; + } + } + printk(BIOS_DEBUG, "BMC ready after %lld ms\n", + stopwatch_duration_msecs(&sw)); +} + void mainboard_memory_init_params(FSPM_UPD *mupd) { + /* Need to wait for BMC ready so that IPMI works. */ + mainboard_wait_for_bmc_ready(); + /* It's better to run get BMC selftest result first */ if (ipmi_premem_init(CONFIG_BMC_KCS_BASE, 0) == CB_SUCCESS) { ipmi_set_post_start(CONFIG_BMC_KCS_BASE); -- To view, visit https://review.coreboot.org/c/coreboot/+/85492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Gerrit-Change-Number: 85492 Gerrit-PatchSet: 9 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com

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[XS] Change in coreboot[main]: drivers/wifi: Update Drive Strength BRI Rsp Table revision
by Jérémy Compostella (Code Review) 17 Dec '24

17 Dec '24

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85586?usp=email ) Change subject: drivers/wifi: Update Drive Strength BRI Rsp Table revision ...................................................................... drivers/wifi: Update Drive Strength BRI Rsp Table revision According to document 559910 Intel Connectivity Platforms BIOS Guideline revision 8.2 and 9.2 specifications, both revision 0 and 1 are supported and share the same structure. BUG=b:346600091 Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85586 Reviewed-by: YH Lin <yueherngl(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/drivers/wifi/generic/acpi.c M src/include/sar.h 2 files changed, 2 insertions(+), 2 deletions(-) Approvals: Subrata Banik: Looks good to me, approved build bot (Jenkins): Verified YH Lin: Looks good to me, approved diff --git a/src/drivers/wifi/generic/acpi.c b/src/drivers/wifi/generic/acpi.c index 4470553..7820987 100644 --- a/src/drivers/wifi/generic/acpi.c +++ b/src/drivers/wifi/generic/acpi.c @@ -985,7 +985,7 @@ * } } }) */ - if (dsbr->revision != DSBR_REVISION) { + if (dsbr->revision > DSBR_REVISION) { printk(BIOS_ERR, "Unsupported DSBR table revision: %d\n", dsbr->revision); return; diff --git a/src/include/sar.h b/src/include/sar.h index 94763b4..d8c0e05 100644 --- a/src/include/sar.h +++ b/src/include/sar.h @@ -21,7 +21,7 @@ #define BDMM_REVISION 1 #define EBRD_REVISION 1 #define WPFC_REVISION 0 -#define DSBR_REVISION 0 +#define DSBR_REVISION 1 #define REVISION_SIZE 1 #define SAR_REV0_CHAINS_COUNT 2 #define SAR_REV0_SUBBANDS_COUNT 5 -- To view, visit https://review.coreboot.org/c/coreboot/+/85586?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id0e05a9db48445b9254701d2a09c19bfbd477284 Gerrit-Change-Number: 85586 Gerrit-PatchSet: 2 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: YH Lin <yueherngl(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: cpu/x86/topology: Simplify CPU topology initialization
by Jérémy Compostella (Code Review) 17 Dec '24

17 Dec '24

Jérémy Compostella has submitted this change. ( https://review.coreboot.org/c/coreboot/+/85576?usp=email ) Change subject: cpu/x86/topology: Simplify CPU topology initialization ...................................................................... cpu/x86/topology: Simplify CPU topology initialization This commit rewrites the CPU topology initialization code to simplify it and make it more maintainable. The previous code used a complex set of if-else statements to initialize the CPU topology based on the CPUID leaves that were supported. This has been replaced with a simpler and more readable function that follows the Intel Software Developer Manual recommendation by prioritizing CPUID EAX=0x1f over CPUID EAX=0xb if available. The new code removes the need for separate functions to handle the topology initialization for different CPUID leaves. It uses a static array of bitfield descriptors to store the APIC ID descriptor information for each level of the CPU topology. This simplifies the code and makes it easier to add new levels of topology in the future. The code populates the node ID based on the package ID, eliminating the need for an extra function call. Change-Id: Ie9424559f895af69e79c36b919e80af803861148 Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/85576 Reviewed-by: Jincheng Li <jincheng.li(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Shuo Liu <shuo.liu(a)intel.com> --- M src/cpu/x86/mp_init.c M src/cpu/x86/topology.c M src/include/cpu/x86/topology.h M src/soc/intel/xeon_sp/spr/cpu.c 4 files changed, 108 insertions(+), 123 deletions(-) Approvals: build bot (Jenkins): Verified Jincheng Li: Looks good to me, but someone else must approve Shuo Liu: Looks good to me, approved diff --git a/src/cpu/x86/mp_init.c b/src/cpu/x86/mp_init.c index bb51697..47b3a9e 100644 --- a/src/cpu/x86/mp_init.c +++ b/src/cpu/x86/mp_init.c @@ -204,7 +204,7 @@ dev->path.apic.initial_lapicid = initial_lapicid(); dev->enabled = 1; - set_cpu_topology_from_leaf_b(dev); + set_cpu_topology(dev); if (cpu_is_intel()) printk(BIOS_INFO, "AP: slot %u apic_id %x, MCU rev: 0x%08x\n", index, @@ -562,7 +562,7 @@ return CB_ERR; } bsp->path.apic.initial_lapicid = initial_lapicid(); - set_cpu_topology_from_leaf_b(bsp); + set_cpu_topology(bsp); /* Find the device structure for the boot CPU. */ set_cpu_info(0, bsp); diff --git a/src/cpu/x86/topology.c b/src/cpu/x86/topology.c index baa4a7a..b2fd202 100644 --- a/src/cpu/x86/topology.c +++ b/src/cpu/x86/topology.c @@ -1,38 +1,73 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <console/console.h> #include <cpu/cpu.h> -#include <device/device.h> #include <cpu/x86/topology.h> +#include <device/device.h> -#define CPUID_EXTENDED_CPU_TOPOLOGY2 0x1f +/* + * The following code defines functions for populating the topology information of a given CPU + * device (struct device *cpu). + * + * Reference: Intel Software Developer Manual Extended Topology Enumeration Leaves (CPUID EAX 0xb + * and 0x1f). + */ -#define CPUID_EXTENDED_CPU_TOPOLOGY 0x0b -#define LEVEL_TYPE_CORE 2 -#define LEVEL_TYPE_SMT 1 +#define CPUID_EXTENDED_CPU_TOPOLOGY 0x0b +#define CPUID_EXTENDED_CPU_TOPOLOGY2 0x1f + +enum { + LEVEL_TYPE_PACKAGE, /* Use unused level zero for package. */ + LEVEL_TYPE_SMT, + LEVEL_TYPE_CORE, + LEVEL_TYPE_MODULE, + LEVEL_TYPE_TILE, + LEVEL_TYPE_DIE, + LEVEL_TYPE_DIEGRP, + LEVEL_TYPE_MAX +}; #define CPUID_CPU_TOPOLOGY(x, val) \ (((val) >> CPUID_CPU_TOPOLOGY_##x##_SHIFT) & CPUID_CPU_TOPOLOGY_##x##_MASK) -#define CPUID_CPU_TOPOLOGY_LEVEL_TYPE_SHIFT 0x8 -#define CPUID_CPU_TOPOLOGY_LEVEL_TYPE_MASK 0xff -#define CPUID_CPU_TOPOLOGY_LEVEL(res) CPUID_CPU_TOPOLOGY(LEVEL_TYPE, (res).ecx) +#define CPUID_CPU_TOPOLOGY_LEVEL_TYPE_SHIFT 0x8 +#define CPUID_CPU_TOPOLOGY_LEVEL_TYPE_MASK 0xff +#define CPUID_CPU_TOPOLOGY_LEVEL(res) CPUID_CPU_TOPOLOGY(LEVEL_TYPE, (res).ecx) -#define CPUID_CPU_TOPOLOGY_LEVEL_BITS_SHIFT 0x0 -#define CPUID_CPU_TOPOLOGY_LEVEL_BITS_MASK 0x1f -#define CPUID_CPU_TOPOLOGY_THREAD_BITS(res) CPUID_CPU_TOPOLOGY(LEVEL_BITS, (res).eax) -#define CPUID_CPU_TOPOLOGY_CORE_BITS(res, threadbits) \ - ((CPUID_CPU_TOPOLOGY(LEVEL_BITS, (res).eax)) - threadbits) +#define CPUID_CPU_TOPOLOGY_LEVEL_BITS_SHIFT 0x0 +#define CPUID_CPU_TOPOLOGY_LEVEL_BITS_MASK 0x1f -/* Return the level shift for the highest supported level (the package) */ -static enum cb_err get_cpu_package_bits(uint32_t *package_bits) +struct bitfield_descriptor { + uint8_t first_bit; + uint8_t num_bits; +}; + +/* + * Fills in the supplied bit field APIC ID descriptor structure array. + * + * Per Intel Software Developer Manual recommendation, it prioritizes CPUID EAX=0x1f over CPUID + * EAX=0xb if available. The function iterates over the hierarchy levels to extract per-domain + * (level) APIC bit field information and populates the provided topology array with the + * bitfield descriptors for each topology level. + * + * Returns CB_ERR if: + * - CPUID EAX=0x1f is not supported. + * - CPUID EAX=0xb is not supported. + * - The first topology level is 0. + * + * Returns CB_SUCCESS otherwise. + */ +static enum cb_err read_topology_structure(struct bitfield_descriptor *topology) { - struct cpuid_result cpuid_regs; - int level_num, cpu_id_op = 0; const uint32_t cpuid_max_func = cpuid_get_max_func(); + struct cpuid_result cpuid_regs; + int level_num = 0, cpu_id_op; + unsigned int level; + uint8_t next_level_first_bit, first_bit = 0; /* - * Not all CPUs support this, those won't get topology filled in here. - * CPU specific code can do this however. + * Not all CPUs support this, those won't get topology filled in here. CPU specific + * code can do this however. */ if (cpuid_max_func >= CPUID_EXTENDED_CPU_TOPOLOGY2) cpu_id_op = CPUID_EXTENDED_CPU_TOPOLOGY2; @@ -41,124 +76,78 @@ else return CB_ERR; - *package_bits = level_num = 0; cpuid_regs = cpuid_ext(cpu_id_op, level_num); /* - * Sub-leaf index 0 enumerates SMT level, some AMD CPUs leave this CPUID leaf - * reserved so bail out. Cpu specific code can fill in the topology later. + * Sub-leaf index 0 enumerates SMT level, some AMD CPUs leave this CPUID leaf reserved + * so bail out. Cpu specific code can fill in the topology later. */ if (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs) != LEVEL_TYPE_SMT) return CB_ERR; do { - *package_bits = (CPUID_CPU_TOPOLOGY(LEVEL_BITS, (cpuid_regs).eax)); + level = CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs); + next_level_first_bit = CPUID_CPU_TOPOLOGY(LEVEL_BITS, cpuid_regs.eax); + if (level < LEVEL_TYPE_MAX) { + topology[level].num_bits = next_level_first_bit - first_bit; + topology[level].first_bit = first_bit; + } else { + printk(BIOS_ERR, "Unknown processor topology level %d\n", level); + } + first_bit = next_level_first_bit; level_num++; cpuid_regs = cpuid_ext(cpu_id_op, level_num); /* Stop when level type is invalid i.e 0. */ } while (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs)); + topology[LEVEL_TYPE_PACKAGE].first_bit = next_level_first_bit; return CB_SUCCESS; } -void set_cpu_node_id_leaf_1f_b(struct device *cpu) +void set_cpu_topology(struct device *cpu) { - static uint32_t package_bits; - static enum cb_err package_bits_ret; - static bool done = false; + const uint32_t apicid = cpu->path.apic.initial_lapicid; + static struct bitfield_descriptor topology[LEVEL_TYPE_MAX]; + static enum cb_err ret; + static bool done; + struct { + unsigned int level; + unsigned int *field; + } apic_fields[] = { + { LEVEL_TYPE_SMT, &cpu->path.apic.thread_id }, + { LEVEL_TYPE_CORE, &cpu->path.apic.core_id }, + { LEVEL_TYPE_PACKAGE, &cpu->path.apic.package_id }, + { LEVEL_TYPE_PACKAGE, &cpu->path.apic.node_id } + }; if (!done) { - package_bits_ret = get_cpu_package_bits(&package_bits); + ret = read_topology_structure(topology); done = true; } - const uint32_t apicid = cpu->path.apic.initial_lapicid; - /* - * If leaf_1f or leaf_b does not exist don't update the node_id. - */ - if (package_bits_ret == CB_SUCCESS) - cpu->path.apic.node_id = (apicid >> package_bits); -} - -/* Get number of bits for core ID and SMT ID */ -static enum cb_err get_cpu_core_thread_bits(uint32_t *core_bits, uint32_t *thread_bits) -{ - struct cpuid_result cpuid_regs; - int level_num, cpu_id_op = 0; - const uint32_t cpuid_max_func = cpuid_get_max_func(); - - /* - * Not all CPUs support this, those won't get topology filled in here. - * CPU specific code can do this however. - */ - if (cpuid_max_func < CPUID_EXTENDED_CPU_TOPOLOGY) - return CB_ERR; - - cpu_id_op = CPUID_EXTENDED_CPU_TOPOLOGY; - - *core_bits = level_num = 0; - cpuid_regs = cpuid_ext(cpu_id_op, level_num); - - /* - * Sub-leaf index 0 enumerates SMT level, some AMD CPUs leave this CPUID leaf - * reserved so bail out. Cpu specific code can fill in the topology later. - */ - if (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs) != LEVEL_TYPE_SMT) - return CB_ERR; - - *thread_bits = CPUID_CPU_TOPOLOGY_THREAD_BITS(cpuid_regs); - do { - level_num++; - cpuid_regs = cpuid_ext(cpu_id_op, level_num); - if (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs) == LEVEL_TYPE_CORE) { - *core_bits = CPUID_CPU_TOPOLOGY_CORE_BITS(cpuid_regs, *thread_bits); - break; - } - /* Stop when level type is invalid i.e 0 */ - } while (CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs)); - - return CB_SUCCESS; -} - -static void set_cpu_topology(struct device *cpu, unsigned int node, - unsigned int package, unsigned int core, - unsigned int thread) -{ - cpu->path.apic.node_id = node; - cpu->path.apic.package_id = package; - cpu->path.apic.core_id = core; - cpu->path.apic.thread_id = thread; -} - -void set_cpu_topology_from_leaf_b(struct device *cpu) -{ - static uint32_t core_bits, thread_bits; - static enum cb_err core_thread_bits_ret; - static bool done = false; - if (!done) { - core_thread_bits_ret = get_cpu_core_thread_bits(&core_bits, &thread_bits); - done = true; - } - - const uint32_t apicid = cpu->path.apic.initial_lapicid; - uint32_t package_id, core_id, thread_id; - /* - * If leaf_b does not exist set the following best-guess defaults: + * If no APIC descriptor is found, set the following best-guess defaults: * - 1 package - * - no SMP * - core_id = apicid + * - no SMP + * - 1 node * CPU specific code can always update these later on. */ - if (core_thread_bits_ret != CB_SUCCESS) { - package_id = 0; - core_id = apicid; - thread_id = 0; - } else { - package_id = apicid >> (thread_bits + core_bits); - core_id = (apicid >> thread_bits) & ((1 << core_bits) - 1); - thread_id = apicid & ((1 << thread_bits) - 1); + if (ret != CB_SUCCESS) { + cpu->path.apic.package_id = 0; + cpu->path.apic.core_id = apicid; + cpu->path.apic.thread_id = 0; + cpu->path.apic.node_id = 0; + return; } - set_cpu_topology(cpu, 0, package_id, core_id, thread_id); + for (size_t i = 0; i < ARRAY_SIZE(apic_fields); i++) { + struct bitfield_descriptor *desc = &topology[apic_fields[i].level]; + if (desc->first_bit || desc->num_bits) { + unsigned int value = apicid >> desc->first_bit; + if (desc->num_bits) + value &= (1 << (desc->num_bits)) - 1; + *apic_fields[i].field = value; + } + } } diff --git a/src/include/cpu/x86/topology.h b/src/include/cpu/x86/topology.h index d66f2eb..a40052e 100644 --- a/src/include/cpu/x86/topology.h +++ b/src/include/cpu/x86/topology.h @@ -5,15 +5,13 @@ #include <device/device.h> -/* Fill in the topology in struct path APIC based CPUID EAX=0xb. - * If leaf 0xb is not supported or is not implemented then no topology - * will be filled in. +/* + * Sets the topology information for the given CPU device using the bitfield descriptors + * obtained from the CPUID leaves. Per Intel Software Developer Manual recommendation, it + * prioritizes CPUID EAX=0x1f over CPUID EAX=0xb if available. + * + * If the topology information cannot be obtained from CPUID, it sets default values. */ -void set_cpu_topology_from_leaf_b(struct device *cpu); +void set_cpu_topology(struct device *cpu); -/* Fill in the topology node ID in struct path APIC based CPUID EAX=0x1f - * or CPUID EAX=0xb. If those leaves aren't supported then the node ID - * won't be updated. - */ -void set_cpu_node_id_leaf_1f_b(struct device *cpu); #endif diff --git a/src/soc/intel/xeon_sp/spr/cpu.c b/src/soc/intel/xeon_sp/spr/cpu.c index 7af7f9a..febc72b 100644 --- a/src/soc/intel/xeon_sp/spr/cpu.c +++ b/src/soc/intel/xeon_sp/spr/cpu.c @@ -72,8 +72,6 @@ __func__, dev_path(cpu), cpu_index(), cpu->path.apic.apic_id, cpu->path.apic.package_id); - /* Populate the node ID. It will be used as proximity ID. */ - set_cpu_node_id_leaf_1f_b(cpu); assert (cpu->path.apic.node_id < CONFIG_MAX_SOCKET); /* -- To view, visit https://review.coreboot.org/c/coreboot/+/85576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9424559f895af69e79c36b919e80af803861148 Gerrit-Change-Number: 85576 Gerrit-PatchSet: 5 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[M] Change in coreboot[main]: cpu/x86/topology: Simplify CPU topology initialization
by Jérémy Compostella (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Christian Walter, Jincheng Li, Johnny Lin, Jonathan Zhang, Lean Sheng Tan, Patrick Rudolph, Ronak Kanabar, Tim Chu. Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/85576?usp=email ) Change subject: cpu/x86/topology: Simplify CPU topology initialization ...................................................................... Patch Set 4: (1 comment) File src/cpu/x86/topology.c: https://review.coreboot.org/c/coreboot/+/85576/comment/f7c85efc_4b689e92?us… : PS4, Line 89: level = CPUID_CPU_TOPOLOGY_LEVEL(cpuid_regs); > There got double MACRO CPUID_CPU_TOPOLOGY_LEVEL call nearly, not sure if it is good to combine them […] Thank you for your feedback. I agree that we could just `break` line 89. But I liked the idea of keeping things close to the original code: the loop body is the working case and the `while` test expression is the one breaking the loop. Ideally I could do the assignment in the while test expression but mixing assignment and test is confusing. Re-working the whole thing with a `for` loop would be my favorite an option but the code is satisfying as-is and it has been widely tested, I do not want to risk to break anything at this stage. In addition, the `CPUID_CPU_TOPOLOGY_LEVEL` macro is trivial and that the compiler is most likely going to optimize the test and assignment. As the patch has been +2 for a little while already, I am going to submit it. -- To view, visit https://review.coreboot.org/c/coreboot/+/85576?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie9424559f895af69e79c36b919e80af803861148 Gerrit-Change-Number: 85576 Gerrit-PatchSet: 4 Gerrit-Owner: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Jonathan Zhang <jon.zhixiong.zhang(a)gmail.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Jincheng Li <jincheng.li(a)intel.com> Gerrit-Attention: Ronak Kanabar <ronak.kanabar(a)intel.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 17:24:03 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Jincheng Li <jincheng.li(a)intel.com>

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Nick Kochlowski (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Paul Menzel. Nick Kochlowski has posted comments on this change by Nick Kochlowski. ( https://review.coreboot.org/c/coreboot/+/85195?usp=email ) Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... Patch Set 9: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/85195/comment/eb9b2c6a_a16b4dcf?us… : PS8, Line 13: TEST=Successful build and boot. There are no longer warnings about not being able to write PCI IRQ assignments. > Please re-flow for 72 characters per line. Done https://review.coreboot.org/c/coreboot/+/85195/comment/f03e9d77_06ccadd9?us… : PS8, Line 18: [WARN ] Can't write PCI IRQ assignments because 'mainboard_pirq_data' : structure does not exist > This could be one line, as it’s logs. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 9 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 17 Dec 2024 16:55:58 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[M] Change in coreboot[main]: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table
by Nick Kochlowski (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Nick Kochlowski. Hello Felix Held, Fred Reitberger, Jason Glenesk, Marshall Dawson, Matt DeVillier, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85195?usp=email to look at the new patch set (#9). Change subject: soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table ...................................................................... soc/amd/phoenix/pci_irq_routing.c: Populate PCI IRQ routing table Populate the PCI bridge IRQ routing table for Phoenix from the SMN registers to replace the stub implementation. The base addresses are copied from Genoa OpenSIL headers, which also correspond to Phoenix. TEST=Successful build and boot. There are no longer warnings about not being able to write PCI IRQ assignments. Before applying patch: [NOTE ] get_pci_routing_table stub: returning empty IRQ routing table [WARN ] Can't write PCI IRQ assignments because 'mainboard_pirq_data' structure does not exist After applying patch: [DEBUG] 01.1: group: 0, swizzle: 0, irq: 0 [DEBUG] 01.2: group: 1, swizzle: 0, irq: 0 [DEBUG] 01.4: group: 0, swizzle: 2, irq: 2 [DEBUG] 01.5: group: 3, swizzle: 0, irq: 0 [DEBUG] 01.6: group: 4, swizzle: 0, irq: 0 [DEBUG] 02.5: group: 5, swizzle: 0, irq: 0 [DEBUG] 02.4: group: 0, swizzle: 1, irq: 2 [DEBUG] 01.3: group: 1, swizzle: 1, irq: 2 [DEBUG] 02.1: group: 2, swizzle: 2, irq: 3 [DEBUG] 02.2: group: 1, swizzle: 2, irq: 2 [DEBUG] 02.3: group: 3, swizzle: 2, irq: 1 [DEBUG] 02.6: group: 4, swizzle: 2, irq: 1 [DEBUG] 03.1: group: 2, swizzle: 0, irq: 0 [DEBUG] 03.2: group: 5, swizzle: 0, irq: 1 [DEBUG] 03.3: group: 5, swizzle: 2, irq: 1 [DEBUG] 03.4: group: 5, swizzle: 2, irq: 1 [DEBUG] 04.1: group: 2, swizzle: 2, irq: 1 [DEBUG] 08.1: group: 3, swizzle: 2, irq: 4 [DEBUG] 08.2: group: 4, swizzle: 2, irq: 4 [DEBUG] 08.3: group: 5, swizzle: 2, irq: 4 [DEBUG] PCI_CFG IRQ: Write PCI config space IRQ assignments [DEBUG] PCI_CFG IRQ: Finished writing PCI config space IRQ assignments Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Signed-off-by: Nicolas Kochlowski <nickkochlowski(a)gmail.com> --- M src/soc/amd/phoenix/pci_irq_routing.c 1 file changed, 62 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/85195/9 -- To view, visit https://review.coreboot.org/c/coreboot/+/85195?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id014ff3e675831eec42bc46c0a76271341e0e3e4 Gerrit-Change-Number: 85195 Gerrit-PatchSet: 9 Gerrit-Owner: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Marshall Dawson <marshalldawson3rd(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Nick Kochlowski <nickkochlowski(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[S] Change in coreboot[main]: mb/ocp/tiogapass: Wait for BMC
by Angel Pons (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Christian Walter, Johnny Lin, Morgan Jang, Patrick Rudolph, Paul Menzel, Shuo Liu, yuchi.chen(a)intel.com. Angel Pons has posted comments on this change by Patrick Rudolph. ( https://review.coreboot.org/c/coreboot/+/85492?usp=email ) Change subject: mb/ocp/tiogapass: Wait for BMC ...................................................................... Patch Set 8: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85492?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I925aff1ff1ffd3d7388835e62aad2ba339e52472 Gerrit-Change-Number: 85492 Gerrit-PatchSet: 8 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yuchi.chen(a)intel.com Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: yuchi.chen(a)intel.com Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Shuo Liu <shuo.liu(a)intel.com> Gerrit-Attention: Morgan Jang <Morgan_Jang(a)wiwynn.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 16:48:42 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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