coreboot-gerrit December 2024

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[M] Change in coreboot[main]: lib/{fit,fit_payload}.c: Enhance support for FIT images
by Benjamin Doron (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Felix Held, Julius Werner, Lean Sheng Tan, Matt DeVillier, Maximilian Brune. Hello Felix Held, Julius Werner, Lean Sheng Tan, Matt DeVillier, Maximilian Brune, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84796?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: lib/{fit,fit_payload}.c: Enhance support for FIT images ...................................................................... lib/{fit,fit_payload}.c: Enhance support for FIT images This is done with the intention of supporting Universal Payload. We implement support for the "load" and "entry" props. Here, these are implemented as fdt64_t. A follow-up will read prop-sized ints. The selected configuration no longer requires an FDT. In this case, we'll attempt a config matching the board ID, then fallback to the FIT default compat. Change-Id: I6a21954c0dc5fd820d135e8cd0599ce87903a1c0 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M src/include/fit.h M src/lib/fit.c M src/lib/fit_payload.c 3 files changed, 138 insertions(+), 30 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/84796/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84796?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I6a21954c0dc5fd820d135e8cd0599ce87903a1c0 Gerrit-Change-Number: 84796 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[M] Change in coreboot[main]: arch/x86/fit_payload.c: Supporting loading FIT payloads
by Benjamin Doron (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Benjamin Doron, Felix Held, Julius Werner, Jérémy Compostella, Maximilian Brune. Hello Felix Held, Julius Werner, Jérémy Compostella, Maximilian Brune, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84799?usp=email to look at the new patch set (#6). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: arch/x86/fit_payload.c: Supporting loading FIT payloads ...................................................................... arch/x86/fit_payload.c: Supporting loading FIT payloads TODO: This code is nearing completion. Drop the assert. Change-Id: I853630431c3d5015ab3b9f560fce8e94cb35ea70 Signed-off-by: Benjamin Doron <benjamin.doron(a)9elements.com> --- M payloads/Kconfig M src/arch/x86/Makefile.mk A src/arch/x86/fit_payload.c 3 files changed, 90 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/84799/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84799?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I853630431c3d5015ab3b9f560fce8e94cb35ea70 Gerrit-Change-Number: 84799 Gerrit-PatchSet: 6 Gerrit-Owner: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de>

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[XS] Change in coreboot[main]: mb/google/brox: Include CSE reset in mainboard reset expectation
by Karthik Ramasubramanian (Code Review) 17 Dec '24

17 Dec '24

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85642?usp=email ) Change subject: mb/google/brox: Include CSE reset in mainboard reset expectation ...................................................................... mb/google/brox: Include CSE reset in mainboard reset expectation If CSE is in RO, then a reset is expected for CSE to jump to RW. Include that reset in mainboard_expects_another_reset() logic. This will avoid unnecessary warm reset during regular boot flow in boards with UFS storage. BUG=None TEST=Build Brox BIOS image and boot to OS. Ensure that redundant reset to disable UFS controller is avoided. Before this change: [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! <snip> [DEBUG] HECI: Global Reset(Type:1) Command <snip> [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! After this change: [DEBUG] HECI: Global Reset(Type:1) Command <snip> [INFO ] Disabling UFS controllers [INFO ] Warm Reset after disabling UFS controllers [INFO ] system_reset() called! Change-Id: I80a46b15813b6bdfa6c029c54590f4b7c2a6754b Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/romstage.c 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/42/85642/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c index 66ed99b..6a03a9a 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c +++ b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c @@ -3,6 +3,7 @@ #include <baseboard/variants.h> #include <cbfs.h> #include <ec/google/chromeec/ec.h> +#include <intelblocks/cse.h> #include <security/vboot/vboot_common.h> #include <security/vboot/misc.h> #include <soc/romstage.h> @@ -53,9 +54,14 @@ bool mainboard_expects_another_reset(void) { + /* Do not change the order of the check in this function */ if (vboot_recovery_mode_enabled()) return false; + /* If CSE is booting from RO, CSE state switch will issue a reset anyway. */ + if (!is_cse_boot_to_rw()) + return true; + if (!CONFIG(VBOOT) || (vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC) && vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_AUXFW_SOFTWARE_SYNC))) -- To view, visit https://review.coreboot.org/c/coreboot/+/85642?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I80a46b15813b6bdfa6c029c54590f4b7c2a6754b Gerrit-Change-Number: 85642 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>

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[L] Change in coreboot[main]: mb/erying: Add Erying Polestar G613 Pro (TGL-H)
by Alicja Michalska (Code Review) 17 Dec '24

17 Dec '24

Alicja Michalska has posted comments on this change by Alicja Michalska. ( https://review.coreboot.org/c/coreboot/+/80853?usp=email ) Change subject: mb/erying: Add Erying Polestar G613 Pro (TGL-H) ...................................................................... Patch Set 16: (1 comment) File src/mainboard/erying/tgl/bootblock.c: https://review.coreboot.org/c/coreboot/+/80853/comment/a7a081ad_058e5422?us… : PS16, Line 6: <gpio.h> > maybe not used Yup! Fixed in CB:85641 :) -- To view, visit https://review.coreboot.org/c/coreboot/+/80853?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iffb9e357da2eb686bdcd9a9837df8a60fa94011e Gerrit-Change-Number: 80853 Gerrit-PatchSet: 16 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Maxim <max.senia.poliak(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: 9elements QA <hardwaretestrobot(a)gmail.com> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Michał Kopeć <michal.kopec(a)3mdeb.com> Gerrit-CC: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Tue, 17 Dec 2024 19:21:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Elyes Haouas <ehaouas(a)noos.fr>

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[M] Change in coreboot[main]: mb/erying/tgl: Cleanup the code
by Alicja Michalska (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Alicja Michalska. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/85641?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified-1 by build bot (Jenkins) Change subject: mb/erying/tgl: Cleanup the code ...................................................................... mb/erying/tgl: Cleanup the code This patch cleans the code by: - Removing CMOS layout (I need to sit down and write layout) - Moving SuperIO configuration to bootblock to make devtree cleaner - Adding sane value for PCI-E ReBAR Additionally, it fixes responsiveness of the power button (it was flaky before), and S3 state *almost* works now (RAM content doesn't get lost, but for some reason Memory Controller wipes MRC Cache on resume from S3). Change-Id: I9e395220025fc13e0589472e4732ea1495668554 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- M src/mainboard/erying/tgl/Kconfig M src/mainboard/erying/tgl/bootblock.c D src/mainboard/erying/tgl/cmos.layout M src/mainboard/erying/tgl/devicetree.cb 4 files changed, 25 insertions(+), 61 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85641/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/85641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e395220025fc13e0589472e4732ea1495668554 Gerrit-Change-Number: 85641 Gerrit-PatchSet: 2 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Alicja Michalska <ahplka19(a)gmail.com>

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[M] Change in coreboot[main]: mb/erying/tgl: Cleanup the code
by Alicja Michalska (Code Review) 17 Dec '24

17 Dec '24

Alicja Michalska has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85641?usp=email ) Change subject: mb/erying/tgl: Cleanup the code ...................................................................... mb/erying/tgl: Cleanup the code This patch cleans the code by: - Removing CMOS layout (I need to sit down and write layout) - Moving SuperIO configuration to bootblock to make devtree cleaner - Adding sane value for PCI-E ReBAR Additionally, it fixes responsiveness of the power button (it was flaky before), and S3 state *almost* works now (RAM content doesn't get lost, but for some reason Memory Controller wipes MRC Cache on resume from S3). Change-Id: I9e395220025fc13e0589472e4732ea1495668554 Signed-off-by: Alicja Michalska <ahplka19(a)gmail.com> --- M src/mainboard/erying/tgl/Kconfig M src/mainboard/erying/tgl/bootblock.c D src/mainboard/erying/tgl/cmos.layout M src/mainboard/erying/tgl/devicetree.cb M src/mainboard/erying/tgl/dsdt.asl 5 files changed, 26 insertions(+), 62 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/85641/1 diff --git a/src/mainboard/erying/tgl/Kconfig b/src/mainboard/erying/tgl/Kconfig index 01e5dd98..f32fa82 100644 --- a/src/mainboard/erying/tgl/Kconfig +++ b/src/mainboard/erying/tgl/Kconfig @@ -13,10 +13,9 @@ select HAVE_ACPI_TABLES select SUPERIO_ITE_IT8613E select DRIVERS_UART_8250IO - select HAVE_CMOS_DEFAULT - select HAVE_OPTION_TABLE select HAVE_INTEL_PTT select CRB_TPM + select PCIEXP_SUPPORT_RESIZABLE_BARS config MAINBOARD_SMBIOS_PRODUCT_NAME default "POLESTAR G613 Pro" @@ -30,6 +29,10 @@ config CBFS_SIZE default 0xA00000 +config PCIEXP_DEFAULT_MAX_RESIZABLE_BAR_BITS + int + default 42 + config USE_PM_ACPI_TIMER default n diff --git a/src/mainboard/erying/tgl/bootblock.c b/src/mainboard/erying/tgl/bootblock.c index 15be8ce..c886905 100644 --- a/src/mainboard/erying/tgl/bootblock.c +++ b/src/mainboard/erying/tgl/bootblock.c @@ -3,14 +3,25 @@ #include <bootblock_common.h> #include <superio/ite/common/ite.h> #include <superio/ite/it8613e/it8613e.h> -#include <gpio.h> #define GPIO_DEV PNP_DEV(0x2e, IT8613E_GPIO) #define UART_DEV PNP_DEV(0x2e, IT8613E_SP1) void bootblock_mainboard_early_init(void) { - ite_reg_write(GPIO_DEV, 0x29, 0xc1); /* 3VSB - RAM loses power in S3 anyway */ - ite_reg_write(GPIO_DEV, 0x2c, 0x41); /* disable k8 power seq */ + ite_reg_write(GPIO_DEV, 0x22, 0x0c); + ite_reg_write(GPIO_DEV, 0x26, 0xf3); + ite_reg_write(GPIO_DEV, 0x29, 0x01); + ite_reg_write(GPIO_DEV, 0x2c, 0x41); + ite_reg_write(GPIO_DEV, 0x2d, 0x02); + ite_reg_write(GPIO_DEV, 0x71, 0x01); + ite_reg_write(GPIO_DEV, 0xbc, 0xc0); + ite_reg_write(GPIO_DEV, 0xbd, 0x03); + ite_reg_write(GPIO_DEV, 0xc1, 0x02); + ite_reg_write(GPIO_DEV, 0xc8, 0x00); + ite_reg_write(GPIO_DEV, 0xc9, 0x02); + ite_reg_write(GPIO_DEV, 0xda, 0xb0); + ite_reg_write(GPIO_DEV, 0xdb, 0x44); + ite_enable_serial(UART_DEV, CONFIG_TTYS0_BASE); } diff --git a/src/mainboard/erying/tgl/cmos.layout b/src/mainboard/erying/tgl/cmos.layout deleted file mode 100644 index a53c3f4..0000000 --- a/src/mainboard/erying/tgl/cmos.layout +++ /dev/null @@ -1,39 +0,0 @@ -# SPDX-License-Identifier: GPL-2.0-only - -entries - -0 384 r 0 reserved_memory - -# RTC_BOOT_BYTE (coreboot hardcoded) -384 1 e 4 boot_option -388 4 h 0 reboot_counter - -# RTC_CLK_ALTCENTURY -400 8 r 0 century - -412 4 e 6 debug_level -416 1 e 2 me_state -417 3 h 0 me_state_counter -984 16 h 0 check_sum - -enumerations - -2 0 Enable -2 1 Disable - -4 0 Fallback -4 1 Normal - -6 0 Emergency -6 1 Alert -6 2 Critical -6 3 Error -6 4 Warning -6 5 Notice -6 6 Info -6 7 Debug -6 8 Spew - -checksums - -checksum 408 983 984 diff --git a/src/mainboard/erying/tgl/devicetree.cb b/src/mainboard/erying/tgl/devicetree.cb index 55744c4..57ac733 100644 --- a/src/mainboard/erying/tgl/devicetree.cb +++ b/src/mainboard/erying/tgl/devicetree.cb @@ -17,10 +17,9 @@ register "eist_enable" = "1" register "enable_c6dram" = "1" + register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN | DSX_EN_WAKE_PIN" register "deep_s3_enable_ac" = "1" - register "deep_s3_enable_dc" = "1" register "deep_s5_enable_ac" = "1" - register "deep_s5_enable_dc" = "1" # PME routing register "pmc_gpe0_dw0" = "PMC_GPP_R" @@ -134,11 +133,11 @@ device ref pch_espi on chip superio/ite/it8613e - device pnp 2e.0 off end + device pnp 2e.0 off end # FDC device pnp 2e.1 on # COM 1 io 0x60 = 0x3f8 - irq 0x70 = 4 - irq 0xf0 = 1 + irq 0x70 = 0x04 + irq 0xf0 = 0x01 end device pnp 2e.4 on # Environment Controller @@ -172,22 +171,12 @@ register "FAN3.smart.slope" = "24" end - device pnp 2e.5 off end - device pnp 2e.6 off end + device pnp 2e.5 off end # Keyboard + device pnp 2e.6 off end # Mouse device pnp 2e.7 on # GPIO - irq 0x2d = 0x02 io 0x60 = 0xa10 io 0x62 = 0xa00 - irq 0x70 = 0x00 - irq 0x71 = 0x01 - irq 0xbc = 0xc0 - irq 0xbd = 0x03 - irq 0xc1 = 0x02 - irq 0xc8 = 0x00 - irq 0xc9 = 0x02 - irq 0xda = 0xb0 - irq 0xdb = 0x44 end device pnp 2e.a off end # CIR end diff --git a/src/mainboard/erying/tgl/dsdt.asl b/src/mainboard/erying/tgl/dsdt.asl index 61898a9..e10b61c 100644 --- a/src/mainboard/erying/tgl/dsdt.asl +++ b/src/mainboard/erying/tgl/dsdt.asl @@ -21,6 +21,6 @@ #include <soc/intel/tigerlake/acpi/southbridge.asl> #include <soc/intel/tigerlake/acpi/tcss.asl> } - + #include <southbridge/intel/common/acpi/sleepstates.asl> } -- To view, visit https://review.coreboot.org/c/coreboot/+/85641?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e395220025fc13e0589472e4732ea1495668554 Gerrit-Change-Number: 85641 Gerrit-PatchSet: 1 Gerrit-Owner: Alicja Michalska <ahplka19(a)gmail.com>

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[M] Change in coreboot[main]: soc/amd/glinda/cpu: Update cache info
by Naresh Solanki (Code Review) 17 Dec '24

17 Dec '24

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85640?usp=email ) Change subject: soc/amd/glinda/cpu: Update cache info ...................................................................... soc/amd/glinda/cpu: Update cache info Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/soc/amd/glinda/cpu.c 1 file changed, 80 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/40/85640/1 diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c index a716127..2d10130 100644 --- a/src/soc/amd/glinda/cpu.c +++ b/src/soc/amd/glinda/cpu.c @@ -6,12 +6,92 @@ #include <amdblocks/mca.h> #include <cpu/amd/microcode.h> #include <cpu/cpu.h> +#include <cpu/x86/mp.h> +#include <cpu/x86/mtrr.h> #include <device/device.h> +#include <lib.h> +#include <smbios.h> #include <soc/cpu.h> _Static_assert(CONFIG_MAX_CPUS == 24, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); +static void ap_get_cache(void *cache_list) +{ + struct cpu_cache_info *info = (struct cpu_cache_info *)cache_list; + uint32_t leaf = DETERMINISTIC_CACHE_PARAMETERS_CPUID_AMD; + info += cpu_index(); + uint8_t level = info->level; + + struct cpuid_result cache_info_res = cpuid_ext(leaf, level); + + info->type = CPUID_CACHE_TYPE(cache_info_res); + info->level = CPUID_CACHE_LEVEL(cache_info_res); + info->num_ways = CPUID_CACHE_WAYS_OF_ASSOC(cache_info_res) + 1; + info->num_sets = CPUID_CACHE_NO_OF_SETS(cache_info_res) + 1; + info->line_size = CPUID_CACHE_COHER_LINE(cache_info_res) + 1; + info->physical_partitions = CPUID_CACHE_PHYS_LINE(cache_info_res) + 1; + info->num_cores_shared = CPUID_CACHE_SHARING_CACHE(cache_info_res) + 1; + info->fully_associative = CPUID_CACHE_FULL_ASSOC(cache_info_res); + info->size = get_cache_size(info); + + struct cpuid_result res = cpuid(0x8000001e); + unsigned int cpuid_cpu_id = res.ebx & 0xff; + info->id = cpuid_cpu_id >> __fls(info->num_cores_shared); +} + +bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) +{ + uint32_t total_cache = 0; + + if (!info) + return false; + + uint32_t leaf = DETERMINISTIC_CACHE_PARAMETERS_CPUID_AMD; + struct cpuid_result cache_info_res = cpuid_ext(leaf, level); + + if (!cache_info_res.eax) { + // No cache at current level. + info->type = 0; + return true; + } + + bool seen_cache_ids[CONFIG_MAX_CPUS] = {false}; + struct cpu_cache_info info_list[CONFIG_MAX_CPUS]; + for (int i = 0; i < CONFIG_MAX_CPUS; i++) + info_list[i].level = level; + + mp_run_on_all_cpus_synchronously(ap_get_cache, info_list); + + memcpy( info, &info_list[0], sizeof(*info) ); + + for (int i = 0; i < get_cpu_count(); i++ ) { + printk(BIOS_SPEW, "CPU %d:\n", i); + printk(BIOS_SPEW, " Cache Level: %d\n", info_list[i].level); + printk(BIOS_SPEW, " Cache Type: %d\n", info_list[i].type); + printk(BIOS_SPEW, " Cache Size: %zu byte\n", info_list[i].size); + printk(BIOS_SPEW, " Line Size: %zu bytes\n", info_list[i].line_size); + printk(BIOS_SPEW, " Number of Ways: %zu\n", info_list[i].num_ways); + printk(BIOS_SPEW, " Number of Sets: %zu\n", info_list[i].num_sets); + printk(BIOS_SPEW, " Physical Partitions: %zu\n", info_list[i].physical_partitions); + printk(BIOS_SPEW, " Number of Cores Sharing Cache: %zu\n", info_list[i].num_cores_shared); + printk(BIOS_SPEW, " Fully Associative: %s\n", info_list[i].fully_associative ? "Yes" : "No"); + printk(BIOS_SPEW, " Cache ID:: %d\n", info_list[i].id); + + if (!seen_cache_ids[info_list[i].id] && level == 3) { + total_cache += info_list[i].size; + seen_cache_ids[info_list[i].id] = true; + } + } + if (level == 3) { + info->num_cores_shared = get_cpu_count(); + info->size = total_cache; + } + + printk(BIOS_DEBUG, ": Max cache at level: %d is:%ld\n", level, info->size); + return true; +} + static void zen_2_3_init(struct device *dev) { check_mca(); -- To view, visit https://review.coreboot.org/c/coreboot/+/85640?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46947e8ac62c903036a81642e03201e353c3dac6 Gerrit-Change-Number: 85640 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com>

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[XS] Change in coreboot[main]: arch/x86/cpu: Add element id to struct cpu_cache_info
by Naresh Solanki (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Jérémy Compostella. Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85639?usp=email ) Change subject: arch/x86/cpu: Add element id to struct cpu_cache_info ...................................................................... arch/x86/cpu: Add element id to struct cpu_cache_info Add variable 'id' to track cache ID. Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/arch/x86/include/arch/cpu.h 1 file changed, 1 insertion(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/85639/1 diff --git a/src/arch/x86/include/arch/cpu.h b/src/arch/x86/include/arch/cpu.h index 8bc6a18..c42530b 100644 --- a/src/arch/x86/include/arch/cpu.h +++ b/src/arch/x86/include/arch/cpu.h @@ -277,6 +277,7 @@ size_t physical_partitions; size_t num_cores_shared; bool fully_associative; + uint8_t id; }; enum cpu_type cpu_check_deterministic_cache_cpuid_supported(void); -- To view, visit https://review.coreboot.org/c/coreboot/+/85639?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I29002931b559a05756419e0c4ec5c78586d3c3a5 Gerrit-Change-Number: 85639 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com>

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[XS] Change in coreboot[main]: arch/x86/cpu: Mark fill_cpu_cache_info as weak
by Naresh Solanki (Code Review) 17 Dec '24

17 Dec '24

Naresh Solanki has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/85638?usp=email ) Change subject: arch/x86/cpu: Mark fill_cpu_cache_info as weak ...................................................................... arch/x86/cpu: Mark fill_cpu_cache_info as weak This allows SoC to implement silicon specific implementation. Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Signed-off-by: Naresh Solanki <naresh.solanki(a)9elements.com> --- M src/arch/x86/cpu_common.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/85638/1 diff --git a/src/arch/x86/cpu_common.c b/src/arch/x86/cpu_common.c index 5f7cd5d..b7db635 100644 --- a/src/arch/x86/cpu_common.c +++ b/src/arch/x86/cpu_common.c @@ -212,7 +212,7 @@ return (cpuid_edx(5) >> (state * 4)) & 0xf; } -bool fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) +bool __weak fill_cpu_cache_info(uint8_t level, struct cpu_cache_info *info) { if (!info) return false; -- To view, visit https://review.coreboot.org/c/coreboot/+/85638?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I60707de4c8242a8fbda8cb5b791a1db762d94449 Gerrit-Change-Number: 85638 Gerrit-PatchSet: 1 Gerrit-Owner: Naresh Solanki <naresh.solanki(a)9elements.com>

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[XL] Change in coreboot[main]: drivers/option: Add forms in cbtables
by Christian Walter (Code Review) 17 Dec '24

17 Dec '24

Attention is currently required from: Angel Pons, Benjamin Doron, Lean Sheng Tan, Martin L Roth, Maximilian Brune, Nico Huber, Patrick Rudolph, Sean Rhodes, Werner Zeh. Christian Walter has posted comments on this change by Angel Pons. ( https://review.coreboot.org/c/coreboot/+/74121?usp=email ) Change subject: drivers/option: Add forms in cbtables ...................................................................... Patch Set 29: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/74121?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I304de7d26d79245a2e31a6d01f6c5643b31cb772 Gerrit-Change-Number: 74121 Gerrit-PatchSet: 29 Gerrit-Owner: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Daniel Maslowski <info(a)orangecms.org> Gerrit-CC: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-CC: Nico Huber <nico.h(a)gmx.de> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Benjamin Doron <benjamin.doron00(a)gmail.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Attention: Werner Zeh <werner.zeh(a)siemens.com> Gerrit-Comment-Date: Tue, 17 Dec 2024 18:04:33 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit December 2024