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Hello Angel Pons, build bot (Jenkins),
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Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
......................................................................
mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
This board is based off ga-b75m-d3h, which uses the same SuperIO chip.
It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with
2 SATA3 ports next to the 4 SATA2 ports.
Flashing notes:
These boards come with dual-BIOS feature. This is set of two
unremovable what appears to be identical chips marked M_BIOS and
B_BIOS. Flash the B_BIOS chip, and boot the system. Ensure you have
a payload and setup ready to boot a Linux system with iomem=relaxed or
similar. Immediately use flashrom -p internal to flash the same
firmware again. If you skip this step your next boot will show weird
exception traces in either coreboot or your payload. Flashing from
there via the chip is very difficult (you have to try many times in
order to get a booting run), which can all be remedied by doing a
flash from internal. I suppose the dual-BIOS feature is somewhat in
the way here.
Tested with:
- CPU Core i7-3770S
- RAM single bank 4GB CL11, two banks 4+4GB CL11
- OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72)
Working:
- GRUB2 payload
- Intel ME stripped
- Integrated graphics with libgfxinit
- (boot from) SATA2, SATA3 ports
- Rear and mainboard connector USB ports, supporting boot
- Atheros GbE NIC
- 2.0 channel audio via lineout jack output
- ACPI (power button triggers OS events)
- S3 suspend/resume
- PWM FAN control, FAN speed readings
- Temperature sensor readings
Signed-off-by: Fabian Groffen <grobian(a)gentoo.org>
Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab
---
A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig
A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name
A src/mainboard/gigabyte/ga-h77m-d3h/Makefile.mk
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl
A src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt
A src/mainboard/gigabyte/ga-h77m-d3h/cmos.default
A src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout
A src/mainboard/gigabyte/ga-h77m-d3h/data.vbt
A src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb
A src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl
A src/mainboard/gigabyte/ga-h77m-d3h/early_init.c
A src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads
A src/mainboard/gigabyte/ga-h77m-d3h/gpio.c
A src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c
A src/mainboard/gigabyte/ga-h77m-d3h/thermal.h
17 files changed, 582 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/77046/8
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Gerrit-Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab
Gerrit-Change-Number: 77046
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Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84940?usp=email )
Change subject: drivers/wifi: Remove unnecessary data structure copy
......................................................................
Patch Set 1:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/84940/comment/05484bdf_302a79cb?us… :
PS1, Line 672: /*
> add sar_limits null check?
This is a static (private) function and we only call it with sar_limits != NULL
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Attention is currently required from: Felix Singer.
Hello Felix Singer,
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84955?usp=email
to look at the new patch set (#2).
Change subject: mb/google/fizz: Fix USB port defintions
......................................................................
mb/google/fizz: Fix USB port defintions
commit 6c83a71b0a80 ("skl mainboards/dt: Move usb{2,3}_ports settings
into XHCI device scope") not only moved the USB port definitions under
the XHCI device reference, but also combined multiple register
definitions. In doing so, it broke the inheritance from the baseboard,
since the variant overridetree registers now replaced the entire
usb2_ports/usb3_ports structs, rather than replacing individual array
elements therein. This resulted in any USB ports inherited from the
baseboard and not overridden by the variant being non-functional as they
were not included in the resulting combined devicetree.
To fix this, return to overriding individual array elements in the
usb2/3_ports structs.
TEST=build/boot google/fizz/var/karma. Verify all USB ports present and
functional. Verify mainboard/static.c in built shows all ports.
Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/fizz/variants/baseboard/devicetree.cb
M src/mainboard/google/fizz/variants/endeavour/overridetree.cb
M src/mainboard/google/fizz/variants/karma/overridetree.cb
3 files changed, 34 insertions(+), 44 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/55/84955/2
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Karthik Ramasubramanian has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84939?usp=email )
Change subject: soc/intel/alderlake: Fix uninitialized usb_cfg pointer
......................................................................
Patch Set 2:
(1 comment)
File src/soc/intel/alderlake/fsp_params.c:
https://review.coreboot.org/c/coreboot/+/84939/comment/8cc25392_9501a47a?us… :
PS2, Line 908:
: usb_cfg = port->chip_info;
> can we add a NULL check here ?
The next line confirms that usb_cfg is not NULL.
From the static analyzer's standpoint, we may not even enter the while loop or everything in the loop is skipped based on if block in line 906. So usb_cfg will be NULL and hence needs to be checked specifically in line 934.
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Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel.
Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84931?usp=email )
Change subject: mb/google/rauru: Enable ChromeOS EC
......................................................................
Patch Set 4:
(1 comment)
File src/mainboard/google/rauru/bootblock.c:
https://review.coreboot.org/c/coreboot/+/84931/comment/e53ab4c0_0cb2447a?us… :
PS2, Line 20: mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0);
> I’d be great if you mentioned the datasheet in the commit message, where it’s specified, that it ope […]
This function call simply indicates that the AP's SPI speed is set to 3MHz on the SPI bus that connects to the ChromeOS EC.
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Attention is currently required from: Robert Chen.
Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84953?usp=email
to look at the new patch set (#2).
The following approvals got outdated and were removed:
Verified-1 by build bot (Jenkins)
Change subject: mb/google/dedede/var/drawcia: Fix devicetree_update
......................................................................
mb/google/dedede/var/drawcia: Fix devicetree_update
ext_vr_update should be run after board version 0xbw, but skipped by
return.
BUG=b:376828839
BRANCH=firmware-dedede-13606.B
TEST=emerge-dedede coreboot chromeos-bootimage
Change-Id: I13f4709b6f490169f69054cf2b26430b4de0746a
Signed-off-by: Robert Chen <robert.chen(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/dedede/variants/drawcia/ramstage.c
1 file changed, 14 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/84953/2
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