coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[main]: soc/mediatek/common: Refactor `struct tracker`
by Yidi Lin (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Hello Hung-Te Lin, Yu-Ping Wu, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84958?usp=email to look at the new patch set (#3). Change subject: soc/mediatek/common: Refactor `struct tracker` ...................................................................... soc/mediatek/common: Refactor `struct tracker` Rather than using a static array size for the `offset` variable, use a pointer named `offsets` that points to a dynamically allocated array. A separate variable called `offset_size` stores the size of this array. TEST=emerge-corsola coreboot && emerge-geralt coreboot Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/tracker_common.h M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v1.c M src/soc/mediatek/common/tracker_v2.c 4 files changed, 20 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/84958/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Gerrit-Change-Number: 84958 Gerrit-PatchSet: 3 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-CC: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Add devicetree for MAX98357A codec
by Subrata Banik (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Anil Kumar K, Pranava Y N. Subrata Banik has posted comments on this change by Anil Kumar K. ( https://review.coreboot.org/c/coreboot/+/84888?usp=email ) Change subject: mb/google/fatcat: Add devicetree for MAX98357A codec ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS2: > can we please merge this change ? this CL was rebased on top of CB:84863 which was not CR+2 therefore, noone can merge this CL without testing there is zero dependency and no rebase to maintain such dependency relationship. -- To view, visit https://review.coreboot.org/c/coreboot/+/84888?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20de87f673e947f0e2332b818ebca01c0fa5e200 Gerrit-Change-Number: 84888 Gerrit-PatchSet: 3 Gerrit-Owner: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Sat, 02 Nov 2024 03:37:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Anil Kumar K <anil.kumar.k(a)intel.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Use write32p and read32p for tracker
by Yidi Lin (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Hung-Te Lin, Yu-Ping Wu. Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84959?usp=email ) Change subject: soc/mediatek/common: Use write32p and read32p for tracker ...................................................................... soc/mediatek/common: Use write32p and read32p for tracker TEST=emerge-geralt coreboot Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v2.c 2 files changed, 10 insertions(+), 10 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/59/84959/1 diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 1341d5a..be83999 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -21,7 +21,7 @@ for (j = 0; j < TRACKER_NUM; j++) { tra = &tracker_data[j]; - if (!(read32((void *)(tra->base_addr)) & tra->timeout)) + if (!(read32p(tra->base_addr) & tra->timeout)) continue; printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); @@ -29,7 +29,7 @@ size = 2 * tra->entry; for (i = 0; i < size; i++) { reg = tra->base_addr + tra->offsets[k] + i * 4; - printk(BIOS_INFO, "%#lx:%#x,", reg, read32((void *)reg)); + printk(BIOS_INFO, "%#lx:%#x,", reg, read32p(reg)); if (i % 4 == 3 || i == size - 1) printk(BIOS_INFO, "\n"); diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c index 415cd0b..5eb9974 100644 --- a/src/soc/mediatek/common/tracker_v2.c +++ b/src/soc/mediatek/common/tracker_v2.c @@ -61,16 +61,16 @@ * peri tracker clock: 78MHz */ val = 156 * 1000 / 16 * 200; - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON0, val); + write32p(INFRA_TRACKER_BASE + BUS_DBG_TIMER_CON1, val); val = 78 * 1000 / 16 * 200; - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0), val); - write32((void *)(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1), val); + write32p(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON0, val); + write32p(PERI_TRACKER_BASE + BUS_DBG_TIMER_CON1, val); /* Enable infra/peri tracer because tracker and tracer share the same enable bit. */ - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1), 1 << BUS_TRACE_EN); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2), 1 << BUS_TRACE_EN); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_1, 1 << BUS_TRACE_EN); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_2, 1 << BUS_TRACE_EN); /* * Enable infra/peri tracker. @@ -81,6 +81,6 @@ * bit[14] - BUS_OT_WEN_CTRL */ val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); - write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1, val); + write32p(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2, val); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84959?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9ee64677e9126789a07db1963a2c17a504cb4d9c Gerrit-Change-Number: 84959 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[S] Change in coreboot[main]: soc/mediatek/common: Refactor `struct tracker`
by Yidi Lin (Code Review) 02 Nov '24

02 Nov '24

Yidi Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84958?usp=email ) Change subject: soc/mediatek/common: Refactor `struct tracker` ...................................................................... soc/mediatek/common: Refactor `struct tracker` Rather than using a static array size for the `offset` variable, use a pointer named `offsets` that points to a dynamically allocated array. A separate variable called `offset_size` stores the size of this array. TEST=emerge-corsola coreboot && emerge-geralt coreboot Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/soc/mediatek/common/include/soc/tracker_common.h M src/soc/mediatek/common/tracker.c M src/soc/mediatek/common/tracker_v1.c M src/soc/mediatek/common/tracker_v2.c 4 files changed, 20 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/58/84958/1 diff --git a/src/soc/mediatek/common/include/soc/tracker_common.h b/src/soc/mediatek/common/include/soc/tracker_common.h index 0269457..ee9d94c 100644 --- a/src/soc/mediatek/common/include/soc/tracker_common.h +++ b/src/soc/mediatek/common/include/soc/tracker_common.h @@ -16,7 +16,8 @@ uintptr_t base_addr; u32 timeout; u32 entry; - u32 offset[2]; + u32 *offsets; + u32 offsets_size; const char *str; }; diff --git a/src/soc/mediatek/common/tracker.c b/src/soc/mediatek/common/tracker.c index 3485449..1341d5a 100644 --- a/src/soc/mediatek/common/tracker.c +++ b/src/soc/mediatek/common/tracker.c @@ -25,10 +25,10 @@ continue; printk(BIOS_INFO, "**Dump %s debug register start**\n", tra->str); - for (k = 0; k < 2; k++) { + for (k = 0; k < tra->offsets_size; k++) { size = 2 * tra->entry; for (i = 0; i < size; i++) { - reg = tra->base_addr + tra->offset[k] + i * 4; + reg = tra->base_addr + tra->offsets[k] + i * 4; printk(BIOS_INFO, "%#lx:%#x,", reg, read32((void *)reg)); if (i % 4 == 3 || i == size - 1) diff --git a/src/soc/mediatek/common/tracker_v1.c b/src/soc/mediatek/common/tracker_v1.c index 746951b..b2736c4 100644 --- a/src/soc/mediatek/common/tracker_v1.c +++ b/src/soc/mediatek/common/tracker_v1.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> #include <soc/addressmap.h> #include <soc/tracker.h> #include <soc/tracker_common.h> @@ -9,13 +10,16 @@ * offset[0] dump from offset 0x100 ~ 0x13C. * offset[1] dump from offset 0x200 ~ 0x23C. */ + +static u32 offsets[] = { AR_TRACK_OFFSET, AW_TRACK_OFFSET }; + struct tracker tracker_data[TRACKER_NUM] = { [TRACKER_SYSTRACKER] = { .base_addr = DBG_TRACKER_BASE, .timeout = BUS_DBG_CON_TIMEOUT, .entry = SYS_TRACK_ENTRY, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), .str = "systracker", }, }; diff --git a/src/soc/mediatek/common/tracker_v2.c b/src/soc/mediatek/common/tracker_v2.c index fecde16..415cd0b 100644 --- a/src/soc/mediatek/common/tracker_v2.c +++ b/src/soc/mediatek/common/tracker_v2.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <commonlib/bsd/helpers.h> #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/tracker.h> @@ -18,29 +19,32 @@ * offset[0] dump from offset 0x100 ~ 0x2F8 * offset[1] dump from offset 0x300 ~ 0x4FC */ + +static u32 offsets[] = { AR_TRACK_OFFSET, AW_TRACK_OFFSET }; + struct tracker tracker_data[TRACKER_NUM] = { [TRACKER_SYSTRACKER] = { .base_addr = DBG_TRACKER_BASE, .timeout = BUS_DBG_CON_TIMEOUT, .entry = SYS_TRACK_ENTRY, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), .str = "systracker", }, [TRACKER_INFRATRACKER] = { .base_addr = INFRA_TRACKER_BASE, .timeout = BUSTRACKER_TIMEOUT, .entry = INFRA_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), .str = "infra_tracker", }, [TRACKER_PERISYSTRACKER] = { .base_addr = PERI_TRACKER_BASE, .timeout = BUSTRACKER_TIMEOUT, .entry = PERI_ENTRY_NUM, - .offset[0] = AR_TRACK_OFFSET, - .offset[1] = AW_TRACK_OFFSET, + .offsets = offsets, + .offsets_size = ARRAY_SIZE(offsets), .str = "peri_tracker", }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/84958?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4b89c27fd693ee08e670c1a9ab4cbdbec220bee7 Gerrit-Change-Number: 84958 Gerrit-PatchSet: 1 Gerrit-Owner: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: ec/dell/mec5035: Add S3 suspend SMI handler
by Nicholas Sudsgaard (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Angel Pons, Nicholas Chin, Paul Menzel. Nicholas Sudsgaard has posted comments on this change by Nicholas Chin. ( https://review.coreboot.org/c/coreboot/+/82170?usp=email ) Change subject: ec/dell/mec5035: Add S3 suspend SMI handler ...................................................................... Patch Set 7: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/82170/comment/7809d6b0_9d8a7ae3?us… : PS7, Line 10: If a command isn't sent, the EC cuts power to the DIMMs, : preventing the system from resuming. > the system immediately locks up and the screen goes dark Maybe the system doesn't appreciate the EC unexpectedly going to sleep. 😊 This sounds similar to how my device reacts if I suddenly put the EC into a sleeping state. However, it seems to work fine when done through the ACPI `WAK`/`PTS` methods. Maybe you could try that? File src/ec/dell/mec5035/smihandler.c: https://review.coreboot.org/c/coreboot/+/82170/comment/2cc68b2c_2c2f771e?us… : PS7, Line 13: mec5035_change_wake(EC_ACPI_WAKE_LID, WAKE_OFF); Does this need to be called every time the system goes into S3? -- To view, visit https://review.coreboot.org/c/coreboot/+/82170?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I655868aba46911d128f6c24f410dc6fdf83f3070 Gerrit-Change-Number: 82170 Gerrit-PatchSet: 7 Gerrit-Owner: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Chin <nic.c3.14(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Nov 2024 02:13:48 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Angel Pons <th3fanbus(a)gmail.com> Comment-In-Reply-To: Nicholas Chin <nic.c3.14(a)gmail.com>

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[M] Change in coreboot[main]: mb/google/fizz: Fix USB port defintions
by Nicholas Sudsgaard (Code Review) 02 Nov '24

02 Nov '24

Attention is currently required from: Felix Singer, Matt DeVillier. Nicholas Sudsgaard has posted comments on this change by Matt DeVillier. ( https://review.coreboot.org/c/coreboot/+/84955?usp=email ) Change subject: mb/google/fizz: Fix USB port defintions ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84955?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e80bf4949a857c21d44537eb720a7a8a7db2f80 Gerrit-Change-Number: 84955 Gerrit-PatchSet: 2 Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Comment-Date: Sat, 02 Nov 2024 01:37:57 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/fatcat: configure espi alarm gpio
by Sukumar Ghorai (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Pranava Y N, Subrata Banik. Hello Pranava Y N, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84957?usp=email to look at the new patch set (#3). Change subject: mb/google/fatcat: configure espi alarm gpio ...................................................................... mb/google/fatcat: configure espi alarm gpio configuration for the eSPI alarm GPIO PADS (ESPI_SOC_ALERT_L) necessary for the SOC to enter low power mode (S0ix). TEST=Build fatcat and check the platform boots without an issue. Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/84957/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f Gerrit-Change-Number: 84957 Gerrit-PatchSet: 3 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: configure espi alarm gpio
by Sukumar Ghorai (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Pranava Y N, Subrata Banik. Hello Pranava Y N, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84957?usp=email to look at the new patch set (#2). Change subject: mb/google/fatcat: configure espi alarm gpio ...................................................................... mb/google/fatcat: configure espi alarm gpio configuration for the eSPI alarm GPIO PADS (ESPI_SOC_ALERT_L) necessary for the SOC to enter low power mode (S0ix). Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/84957/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f Gerrit-Change-Number: 84957 Gerrit-PatchSet: 2 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: configure espi alarm gpio
by Sukumar Ghorai (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Pranava Y N, Subrata Banik. Sukumar Ghorai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84957?usp=email ) Change subject: mb/google/fatcat: configure espi alarm gpio ...................................................................... mb/google/fatcat: configure espi alarm gpio espi alarm gpio PADS (ESPI_SOC_ALERT_L) configuratin required soc to enter low power mode (for S0ix). Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/fatcat/variants/fatcat/gpio.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/84957/1 diff --git a/src/mainboard/google/fatcat/variants/fatcat/gpio.c b/src/mainboard/google/fatcat/variants/fatcat/gpio.c index ca59446..65873ab 100644 --- a/src/mainboard/google/fatcat/variants/fatcat/gpio.c +++ b/src/mainboard/google/fatcat/variants/fatcat/gpio.c @@ -43,7 +43,7 @@ /* GPP_A15: GPP_A15_DNX_FORCE_RELOAD */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1), /* GPP_A16: BT_RF_KILL_N */ - PAD_CFG_GPO(GPP_A16, 1, DEEP), + PAD_NC(GPP_A16, NONE), /* GPP_A17: WIFI_RF_KILL_N */ PAD_CFG_GPO(GPP_A17, 1, DEEP), -- To view, visit https://review.coreboot.org/c/coreboot/+/84957?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f Gerrit-Change-Number: 84957 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com>

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[XS] Change in coreboot[main]: mb/google/fatcat: Disable package c-state auto-demotion
by Sukumar Ghorai (Code Review) 01 Nov '24

01 Nov '24

Sukumar Ghorai has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84956?usp=email ) Change subject: mb/google/fatcat: Disable package c-state auto-demotion ...................................................................... mb/google/fatcat: Disable package c-state auto-demotion Package C-state auto demotion feature allows hardware to determine lower C-state as per platform policy. Since platform sets performance policy to balanced from hardware, auto demotion can be disabled without performance impact. TEST=Build fatcat and check the platform boots without an issue. Change-Id: I01f2cb8ac1093ae98cc076e35ad1924baa53aa59 Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 2 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/84956/1 diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index 1b1fc73..a9cc3ee 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -39,6 +39,8 @@ # TODO: Safe Setting. Needs to be removed later # Disable C1 C-state auto-demotion register "disable_c1_state_auto_demotion" = "true" + # Disable PKGC-state demotion + register "disable_package_c_state_demotion" = "true" # Enable CNVi BT register "cnvi_bt_core" = "true" -- To view, visit https://review.coreboot.org/c/coreboot/+/84956?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I01f2cb8ac1093ae98cc076e35ad1924baa53aa59 Gerrit-Change-Number: 84956 Gerrit-PatchSet: 1 Gerrit-Owner: Sukumar Ghorai <sukumar.ghorai(a)intel.com>

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