Subrata Banik has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84974?usp=email )
Change subject: soc/intel/alderlake: Disable UFS controllers only on S5 resume
......................................................................
soc/intel/alderlake: Disable UFS controllers only on S5 resume
Disable UFS controllers during romstage initialization only when
resuming from S5 (full power off).
On warm reboot, the UFS controllers are already disabled by the
previous boot cycle, so disabling them again is unnecessary.
TEST=Able to ensure UFS controller is already disabled in warm reboot
path and not causing any problem during S0ix cycle test.
Change-Id: Ia27d2156a002cef032d5f57d212cf4eb520b3bdf
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/soc/intel/alderlake/romstage/romstage.c
1 file changed, 2 insertions(+), 2 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/84974/1
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index 2f50cd2..3acd2fd 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -188,9 +188,9 @@
/* Program to Disable UFS Controllers */
if (!is_devfn_enabled(PCH_DEVFN_UFS) &&
(CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {
- printk(BIOS_INFO, "Disabling UFS controllers\n");
- disable_ufs();
if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) {
+ printk(BIOS_INFO, "Disabling UFS controllers\n");
+ disable_ufs();
printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");
system_reset();
}
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Gerrit-Change-Id: Ia27d2156a002cef032d5f57d212cf4eb520b3bdf
Gerrit-Change-Number: 84974
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Gerrit-Owner: Subrata Banik <subratabanik(a)google.com>
Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84935?usp=email )
(
2 is the latest approved patch-set.
No files were changed between the latest approved patch-set and the submitted one.
)Change subject: soc/intel/alderlake: Do lazy reset after disabling UFS
......................................................................
soc/intel/alderlake: Do lazy reset after disabling UFS
If the mainboard expects upcoming reset, then skip the reset after
disabling UFS. This will reduce the number of resets during firmware
update.
BUG=b:375444631
TEST=Build Brox BIOS image and boot to OS. Perform a firmware update and
confirm that the number of reset is reduced by 2 resets.
Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/84935
Reviewed-by: Subrata Banik <subratabanik(a)google.com>
Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org>
Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org>
---
M src/soc/intel/alderlake/include/soc/romstage.h
M src/soc/intel/alderlake/romstage/romstage.c
2 files changed, 17 insertions(+), 1 deletion(-)
Approvals:
Paul Menzel: Looks good to me, but someone else must approve
build bot (Jenkins): Verified
Subrata Banik: Looks good to me, approved
diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h
index 679d538..574c9b7 100644
--- a/src/soc/intel/alderlake/include/soc/romstage.h
+++ b/src/soc/intel/alderlake/include/soc/romstage.h
@@ -20,4 +20,15 @@
BOARD_TYPE_SERVER = 8
};
+/*
+ * Default implementation indicates that the mainboard does not expect another reset.
+ * Mainboards can override the default implementation to indicate whether they expect
+ * another reset eg. FW Sync for another component on the mainboard. Some silicon init
+ * code eg. disabling UFS, can use this hint to suppress any redundant resets that they
+ * trigger. If the mainboard does not expect another reset, then the silicon init code
+ * can trigger their required reset.
+ *
+ * Return: true when the mainboard expects another reset, false otherwise.
+ */
+bool mainboard_expects_another_reset(void);
#endif /* _SOC_ROMSTAGE_H_ */
diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c
index ff600db..2f50cd2 100644
--- a/src/soc/intel/alderlake/romstage/romstage.c
+++ b/src/soc/intel/alderlake/romstage/romstage.c
@@ -32,6 +32,11 @@
#define PCR_PSFX_T0_SHDW_PCIEN 0x1C
#define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8)
+bool __weak mainboard_expects_another_reset(void)
+{
+ return false;
+}
+
static void disable_ufs(void)
{
/* disable USF0 */
@@ -185,7 +190,7 @@
(CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) {
printk(BIOS_INFO, "Disabling UFS controllers\n");
disable_ufs();
- if (ps->prev_sleep_state == ACPI_S5) {
+ if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) {
printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n");
system_reset();
}
--
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Change subject: mb/google/fatcat: Disable package c-state auto-demotion
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/84956/comment/26d8194f_5b59dd2a?us… :
PS1, Line 42: # Disable PKGC-state demotion
```suggestion
# Disable PKGC-state auto-demotion
```
https://review.coreboot.org/c/coreboot/+/84956/comment/d4e3fbb9_4322d383?us… :
PS1, Line 42: demotion
> Acknowledged
looks like u said `ACK` but nothing has been changed ?
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Subrata Banik has posted comments on this change by Sukumar Ghorai. ( https://review.coreboot.org/c/coreboot/+/84957?usp=email )
Change subject: mb/google/fatcat: configure espi alarm gpio
......................................................................
Patch Set 4: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84957/comment/6267670f_b686c5a2?us… :
PS4, Line 7: mb/google/fatcat: configure espi alarm gpio
mb/google/fatcat/var/fatcat: Configure eSPI alarm GPIO
This patch configures the ESPI_SOC_ALERT_L GPIO pad on fatcat as NC to enable S0ix low power entry.
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Change subject: mb/google/fatcat: Disable package c-state auto-demotion
......................................................................
Patch Set 1:
(2 comments)
File src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb:
https://review.coreboot.org/c/coreboot/+/84956/comment/12f69250_73a0f6f2?us… :
PS1, Line 42: demotion
> nit: […]
Acknowledged
https://review.coreboot.org/c/coreboot/+/84956/comment/4a9cee3b_ff61992d?us… :
PS1, Line 43: register "disable_package_c_state_demotion" = "true"
> initially when this was implemented in ADL, I thought this is a W/A and we won't need this in future […]
Auto demotion is disable for all Chrome platform. MTL ref. a5596a351e633 mb/intel/mtlrvp: Disable package C-state auto demotion.
EPB (Dynamic Energy Performance Preference) value comes into playfor C1 demotion heuristics use EPB parameter to balance between power and performance, i.e. low threshold when EPB is low in-order to get C1 demotion faster and vice-versa. Some OS changes the EPB value dynamically in AC/DC mode so in AC gets more demotions and gains performance while in DC it hits less demotion and gains power. Unfortunately, ChromeOS operates at default EPB=0x7 (low EPB) in both AC/DC, so in DC mode it gets much C1 demotion hits than expected (similar to AC mode) and loses power, respectively. Chrome customers decided to disable C1 demotion since they lost power in some KPI when it’s enabled.
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Hello Pranava Y N, Subrata Banik, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84957?usp=email
to look at the new patch set (#4).
The following approvals got outdated and were removed:
Verified+1 by build bot (Jenkins)
Change subject: mb/google/fatcat: configure espi alarm gpio
......................................................................
mb/google/fatcat: configure espi alarm gpio
configuration for the eSPI alarm GPIO PADS (ESPI_SOC_ALERT_L) necessary
for the SOC to enter low power mode (S0ix).
TEST=Build fatcat and check the platform boots without an issue.
Change-Id: Icb80a56177105c0281d05fe1f5daa87e6f7e291f
Signed-off-by: Sukumar Ghorai <sukumar.ghorai(a)intel.com>
---
M src/mainboard/google/fatcat/variants/fatcat/gpio.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/57/84957/4
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Change subject: mb/google/fatcat: configure espi alarm gpio
......................................................................
Patch Set 3:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84957/comment/488cbd3c_afe606dd?us… :
PS3, Line 7: configure espi alarm gpio
> looks like you are configuring BT_RF_KILL_N from GPO to NC. […]
Acknowledged
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Change subject: soc/mediatek/common: Refactor `struct tracker`
......................................................................
Patch Set 3: Code-Review+2
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Change subject: soc/mediatek/common: Use write32p and read32p for tracker
......................................................................
Patch Set 3: Code-Review+2
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