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Hello Paul Menzel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Code-Review+1 by Paul Menzel, Verified+1 by build bot (Jenkins)
Change subject: mb/google/brox: Hint romstage init about upcoming reset
......................................................................
mb/google/brox: Hint romstage init about upcoming reset
Add support for the mainboard to check for any potential firmware
component update and hence the assosicated reset. This indication can be
used to avoid any redundant resets during the boot flow.
BUG=b:375444631
TEST=Build Brox BIOS image and boot to OS. Ensure that the hints are
provided correctly and 2 redundant resets are filtered out.
Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk
A src/mainboard/google/brox/variants/baseboard/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brox/variants/brox/Makefile.mk
M src/mainboard/google/brox/variants/brox/variant.c
M src/mainboard/google/brox/variants/jubilant/Makefile.mk
M src/mainboard/google/brox/variants/jubilant/variant.c
M src/mainboard/google/brox/variants/lotso/Makefile.mk
M src/mainboard/google/brox/variants/lotso/variant.c
9 files changed, 93 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/84937/5
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Gerrit-Change-Number: 84937
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Jérémy Compostella has posted comments on this change by Jérémy Compostella. ( https://review.coreboot.org/c/coreboot/+/84941?usp=email )
Change subject: drivers/wifi: Support Bluetooth Per-Platform Antenna Gain
......................................................................
Patch Set 2:
(1 comment)
File src/drivers/wifi/generic/acpi.c:
https://review.coreboot.org/c/coreboot/+/84941/comment/3206445c_1f094a89?us… :
PS1, Line 675: BTPPAG
> should it be PPAG since acpigen_write_name("PPAG");?
Done
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Hello Anil Kumar K, Bora Guvendik, Cliff Huang, Hannah Williams, Jamie Ryu, Zhixing Ma, build bot (Jenkins), dinesh.sharma(a)intel.com,
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: drivers/wifi: Support Bluetooth Per-Platform Antenna Gain
......................................................................
drivers/wifi: Support Bluetooth Per-Platform Antenna Gain
The ACPI BTPPAG method provide information to controls the antenna
gain method to be used per country.
The ANTenna gain mode is a bit field (0 - disabled, 1 -enabled)
defined as follow:
- Bit 0 - Antenna gain in EU
- Bit 1 - Antenna gain in China Mainland
The implementation follows document 559910 Intel Connectivity
Platforms BIOS Guideline revision 8.3 specification.
BUG=b:346600091
TEST=BTPPAG method is added to the bluetooth companion device and
return the data supplied by the SAR binary blob
Change-Id: Iebe95815c944d045f4cf686abcd1874a8a45e210
Signed-off-by: Jeremy Compostella <jeremy.compostella(a)intel.com>
---
M src/drivers/wifi/generic/acpi.c
M src/include/sar.h
M src/vendorcode/google/chromeos/sar.c
3 files changed, 53 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/41/84941/2
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Change subject: mb/google/fatcat: Add devicetree for MAX98357A codec
......................................................................
Patch Set 2:
(1 comment)
Patchset:
PS2:
can we please merge this change ?
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Hello Angel Pons, build bot (Jenkins),
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Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
......................................................................
mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
This board is based off ga-b75m-d3h, which uses the same SuperIO chip.
It doesn't have the ASMedia SATA3 controller, the H77 chipset comes with
2 SATA3 ports next to the 4 SATA2 ports.
Flashing notes:
These boards come with dual-BIOS feature. This is set of two
unremovable what appears to be identical chips marked M_BIOS and
B_BIOS. Flash the B_BIOS chip, and boot the system. Ensure you have
a payload and setup ready to boot a Linux system with iomem=relaxed or
similar. Immediately use flashrom -p internal to flash the same
firmware again. If you skip this step your next boot will show weird
exception traces in either coreboot or your payload. Flashing from
there via the chip is very difficult (you have to try many times in
order to get a booting run), which can all be remedied by doing a
flash from internal. I suppose the dual-BIOS feature is somewhat in
the way here.
Tested with:
- CPU Core i7-3770S
- RAM single bank 4GB CL11, two banks 4+4GB CL11
- OS Gentoo Linux LiveUSB, KDE desktop (Linux 5.15.72)
Working:
- GRUB2 payload
- Intel ME stripped
- Integrated graphics with libgfxinit
- (boot from) SATA2, SATA3 ports
- Rear and mainboard connector USB ports, supporting boot
- Atheros GbE NIC
- 2.0 channel audio via lineout jack output
- ACPI (power button triggers OS events)
- S3 suspend/resume
- PWM FAN control, FAN speed readings
- Temperature sensor readings
Signed-off-by: Fabian Groffen <grobian(a)gentoo.org>
Change-Id: Icb3e74326a0a7aaf770d1917a2a0931feadd7eab
---
A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig
A src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name
A src/mainboard/gigabyte/ga-h77m-d3h/Makefile.mk
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/ec.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/platform.asl
A src/mainboard/gigabyte/ga-h77m-d3h/acpi/superio.asl
A src/mainboard/gigabyte/ga-h77m-d3h/board_info.txt
A src/mainboard/gigabyte/ga-h77m-d3h/cmos.default
A src/mainboard/gigabyte/ga-h77m-d3h/cmos.layout
A src/mainboard/gigabyte/ga-h77m-d3h/data.vbt
A src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb
A src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl
A src/mainboard/gigabyte/ga-h77m-d3h/early_init.c
A src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads
A src/mainboard/gigabyte/ga-h77m-d3h/gpio.c
A src/mainboard/gigabyte/ga-h77m-d3h/hda_verb.c
A src/mainboard/gigabyte/ga-h77m-d3h/thermal.h
17 files changed, 552 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/46/77046/9
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Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
......................................................................
Patch Set 8:
(5 comments)
Patchset:
PS8:
more comments addressed
File src/mainboard/gigabyte/ga-h77m-d3h/acpi/mainboard.asl:
https://review.coreboot.org/c/coreboot/+/77046/comment/312aebd4_eb96912b?us… :
PS7, Line 3: Scope (\_SB)
: {
: Device (PWRB)
: {
: Name (_HID, EisaId ("PNP0C0C"))
: }
: }
:
> Does this also come from the B75 board? I remember checking the ACPI spec, and there's no reason to […]
Done
File src/mainboard/gigabyte/ga-h77m-d3h/acpi/pci.asl:
https://review.coreboot.org/c/coreboot/+/77046/comment/7ccf2f58_08a87585?us… :
PS7, Line 7: Name (_ADR, 0x001E0000)
> Then I would simply remove this file
Done
File src/mainboard/gigabyte/ga-h77m-d3h/acpi/thermal.asl:
PS7:
> I remember similar code caused ACPI errors for me on one of the H61 boards. […]
Done
File src/mainboard/gigabyte/ga-h77m-d3h/acpi_tables.c:
https://review.coreboot.org/c/coreboot/+/77046/comment/88b8a253_e06cb3a9?us… :
PS7, Line 10: gnvs->tpsv = PASSIVE_TEMPERATURE;
> After removing `thermal. […]
Done
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Change subject: mb/gigabyte/ga-h77m-d3h: Add Sandy/Ivy Bridge board GA-H77M-D3H
......................................................................
Patch Set 8:
(14 comments)
Patchset:
PS8:
rebased, addressed comments
File src/mainboard/gigabyte/ga-h77m-d3h/Kconfig:
PS7:
> Missing license header
Done
https://review.coreboot.org/c/coreboot/+/77046/comment/5698282c_812352e3?us… :
PS7, Line 21: default 25
> As per schematics, this board doesn't seem to use a DRAM reset gate GPIO at all (the DRAMRST# signal […]
Done
File src/mainboard/gigabyte/ga-h77m-d3h/Kconfig.name:
PS7:
> Missing license header
Done
File src/mainboard/gigabyte/ga-h77m-d3h/devicetree.cb:
PS7:
> Missing license header
Done
https://review.coreboot.org/c/coreboot/+/77046/comment/297d8356_7092cc46?us… :
PS7, Line 5: subsystemid 0x1458 0x5000
> See this very file, two lines above this one.
Done
https://review.coreboot.org/c/coreboot/+/77046/comment/9afc9200_122a3274?us… :
PS7, Line 26: device ref mei2 off end # Management Engine Interface 2
> I think the chipset devicetree already provides default on/off states for named devices, so you shou […]
Done
https://review.coreboot.org/c/coreboot/+/77046/comment/cdffa7cb_1fdf11bd?us… :
PS7, Line 36: device ref pcie_rp1 on end # PCIe Port #1
: device ref pcie_rp2 off end # PCIe Port #2
: device ref pcie_rp3 off end # PCIe Port #3
: device ref pcie_rp4 off end # PCIe Port #4
: device ref pcie_rp5 on # PCIe Port #5
: device pci 00.0 on # AR8161 GbE
: end
: end
: device ref pcie_rp6 off end # PCIe Port #6
: device ref pcie_rp7 off end # PCIe Port #7
: device ref pcie_rp8 off end # PCIe Port #8
> Based on what I can see in board pictures [1], this is not accurate. […]
Done
https://review.coreboot.org/c/coreboot/+/77046/comment/93cb29c4_eb601f4e?us… :
PS7, Line 50: device ref pci_bridge on end # PCI bridge
> The PCI bridge in the southbridge doesn't seem to be used. You should disable it.
Done
https://review.coreboot.org/c/coreboot/+/77046/comment/e1d501fb_3f826d77?us… :
PS7, Line 107: device pci 1f.4 off end
> I don't think this device is supposed to exist
Done
File src/mainboard/gigabyte/ga-h77m-d3h/dsdt.asl:
https://review.coreboot.org/c/coreboot/+/77046/comment/acd7c99c_c3af5d05?us… :
PS7, Line 10: // OEM revision
> Still, it's most likely autoport copy-paste. I'd drop the comment anyway.
Done
File src/mainboard/gigabyte/ga-h77m-d3h/gma-mainboard.ads:
https://review.coreboot.org/c/coreboot/+/77046/comment/162b1eae_2c30fad5?us… :
PS7, Line 1: GPL-2.0-only
> GPL-2. […]
Done
File src/mainboard/gigabyte/ga-h77m-d3h/gpio.c:
PS7:
> Was this file copied as-is from the other board? I hope not, because bad GPIO configuration can brea […]
Done
File src/mainboard/gigabyte/ga-h77m-d3h/thermal.h:
https://review.coreboot.org/c/coreboot/+/77046/comment/3379d9a6_d5fb1713?us… :
PS7, Line 9: /* Temperature which OS will throttle CPU */
> We usually don't indent defines. Please remove.
Done
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