coreboot-gerrit November 2024

coreboot-gerrit@coreboot.org

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[XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism
by Paul Menzel (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Lawrence Chang, Nick Vaccaro, Simon Yang. Paul Menzel has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/84866?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/jasperlake: add support for RP LTR mechanism ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84866/comment/f6b4e8d5_4681e85a?us… : PS3, Line 13: Tested on Awasuki with RTL8852BE > You can check root port configuration space dump, LTR Mechanism Enable bit is offset 68h[10]. Please add these details, and the command how to dump the root port configuration space. -- To view, visit https://review.coreboot.org/c/coreboot/+/84866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Gerrit-Change-Number: 84866 Gerrit-PatchSet: 3 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: David Ruth <druth(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: David Ruth <druth(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Attention: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 07:14:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lawrence Chang <lawrence.chang(a)intel.com>

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[XS] Change in coreboot[main]: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs
by Paul Menzel (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Yu-Ping Wu. Paul Menzel has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/84950?usp=email ) Change subject: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c44f09b3cdadbbf039b95efca7144f213672092 Gerrit-Change-Number: 84950 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 07:13:21 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Increase the VccIn Aux Imon IccMax to 30A
by Yu-Ping Wu (Code Review) 01 Nov '24

01 Nov '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84922?usp=email ) Change subject: mb/google/nissa/var/riven: Increase the VccIn Aux Imon IccMax to 30A ...................................................................... mb/google/nissa/var/riven: Increase the VccIn Aux Imon IccMax to 30A From power team's recommendation, increase the VccIn Aux Imon IccMax to 30A to meet HW settings. BUG=b:376306118 TEST=Build firmware and check the value is changing as expected. Paste the firmware log. [SPEW ] VccInAuxImonIccImax= 0x78 [SPEW ] (MAILBOX) VccInAuxImonIccImax = 120 (1/4 Amp) [INFO ] Override VccInAuxImonIccImax = 120 Change-Id: I71020c2f631cb517a52d4bb65e35277eb731ced7 Signed-off-by: David Wu <david_wu(a)quanta.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84922 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Zhuohao Lee <zhuohao(a)google.com> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Subrata Banik <subratabanik(a)google.com> --- M src/mainboard/google/brya/variants/riven/ramstage.c 1 file changed, 1 insertion(+), 1 deletion(-) Approvals: Zhuohao Lee: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Subrata Banik: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/riven/ramstage.c b/src/mainboard/google/brya/variants/riven/ramstage.c index 5ed9a37f..90517bd 100644 --- a/src/mainboard/google/brya/variants/riven/ramstage.c +++ b/src/mainboard/google/brya/variants/riven/ramstage.c @@ -7,6 +7,6 @@ { /* Refer to FSP Silicon (soc/intel/alderlake/fsp_params.c) VccIn Aux Imon IccMax. Values are in 1/4 Amp increments */ - params->VccInAuxImonIccImax = 100; /* 25000(25A) * 4 / 1000 */ + params->VccInAuxImonIccImax = 120; /* 30000(30A) * 4 / 1000 */ printk(BIOS_INFO, "Override VccInAuxImonIccImax = %d\n", params->VccInAuxImonIccImax); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84922?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71020c2f631cb517a52d4bb65e35277eb731ced7 Gerrit-Change-Number: 84922 Gerrit-PatchSet: 4 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: mb/google/nissa/var/riven: Increase the VccIn Aux Imon IccMax to 30A
by Zhuohao Lee (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: David Wu, Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Paul Menzel. Zhuohao Lee has posted comments on this change by David Wu. ( https://review.coreboot.org/c/coreboot/+/84922?usp=email ) Change subject: mb/google/nissa/var/riven: Increase the VccIn Aux Imon IccMax to 30A ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84922?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I71020c2f631cb517a52d4bb65e35277eb731ced7 Gerrit-Change-Number: 84922 Gerrit-PatchSet: 3 Gerrit-Owner: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Zhuohao Lee <zhuohao(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: David Wu <david_wu(a)quanta.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Comment-Date: Fri, 01 Nov 2024 06:09:00 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Yidi Lin (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Runyang Chen. Yidi Lin has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84896?usp=email ) Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... Patch Set 5: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 06:05:17 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs
by Yidi Lin (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Yu-Ping Wu. Yidi Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/84950?usp=email ) Change subject: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c44f09b3cdadbbf039b95efca7144f213672092 Gerrit-Change-Number: 84950 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 06:02:23 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: soc/intel/jasperlake: add support for RP LTR mechanism
by Lawrence Chang (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Curtis Chen, David Ruth, Jamie Chen, Nick Vaccaro, Paul Menzel, Simon Yang. Lawrence Chang has posted comments on this change by Lawrence Chang. ( https://review.coreboot.org/c/coreboot/+/84866?usp=email ) Change subject: soc/intel/jasperlake: add support for RP LTR mechanism ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84866/comment/f516a348_f6ba310a?us… : PS3, Line 13: Tested on Awasuki with RTL8852BE > How to check this exactly? coreboot logs or `lspci`? You can check root port configuration space dump, LTR Mechanism Enable bit is offset 68h[10]. -- To view, visit https://review.coreboot.org/c/coreboot/+/84866?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I85e50b01cc9fb5522d457cfce3700b7c85d7012f Gerrit-Change-Number: 84866 Gerrit-PatchSet: 3 Gerrit-Owner: Lawrence Chang <lawrence.chang(a)intel.com> Gerrit-Reviewer: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Reviewer: David Ruth <druth(a)chromium.org> Gerrit-Reviewer: David Ruth <druth(a)google.com> Gerrit-Reviewer: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Reviewer: Simon Yang <simon1.yang(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jamie Chen <jamie.chen(a)intel.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Simon Yang <simon1.yang(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Attention: David Ruth <druth(a)google.com> Gerrit-Attention: Curtis Chen <curtis.chen(a)intel.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 05:09:50 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs
by Hung-Te Lin (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Yidi Lin, Yu-Ping Wu. Hung-Te Lin has posted comments on this change by Yu-Ping Wu. ( https://review.coreboot.org/c/coreboot/+/84950?usp=email ) Change subject: soc/mediatek/mt8188/spi: Fix out-of-bound array access for pad_funcs ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84950?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9c44f09b3cdadbbf039b95efca7144f213672092 Gerrit-Change-Number: 84950 Gerrit-PatchSet: 1 Gerrit-Owner: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 04:05:18 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Yu-Ping Wu (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Paul Menzel, Runyang Chen, Yidi Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84896?usp=email ) Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... Patch Set 5: Code-Review+2 (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84896/comment/5f32eb4b_59362752?us… : PS5, Line 12: If the interrupt is not handled, it will cause the system fail to boot. Either move this to the previous line, or add a blank line above to start a new paragraph. -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 5 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 03:46:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/rauru: Pass reset gpio parameter to BL31
by Yu-Ping Wu (Code Review) 01 Nov '24

01 Nov '24

Attention is currently required from: Hung-Te Lin, Jarried Lin. Yu-Ping Wu has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84933?usp=email ) Change subject: mb/google/rauru: Pass reset gpio parameter to BL31 ...................................................................... Patch Set 4: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84933?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4ddecfb8f36a8f721b57ca16e6a861f933b058b4 Gerrit-Change-Number: 84933 Gerrit-PatchSet: 4 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Fri, 01 Nov 2024 03:44:15 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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coreboot-gerrit November 2024