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Change subject: soc/intel/common/gpio: add function to lock GPIO configuration
......................................................................
Patch Set 3:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/84901/comment/7dfa13dc_b3e03058?us… :
PS3, Line 485: /* Clear lock for the exception PADs */
> we won't be able to clear the locking after we reaches ramstage (after FSP-S exits)
Yes. that is the intention. This function only updates the base table lock_action field. After the base table is overridden via fw_config for the final configuration in the mainboard.c, we perform configuration lock. Currently, this function is called to add the lock property to the table before we actually write to GPIO config registers prior to calling FSP-S. We could defer locking after FSP-S exit. The lock configuration bits are located in different registers other than the individual DW0/1 registers and we update those lock bits according to this GPIO base table.
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Change subject: mb/google/fatcat: support ISH
......................................................................
Patch Set 3:
(1 comment)
Patchset:
PS3:
we need to hold the ISH enabling unless we have right strategy in place.
At minimal we need few blobs to support ISH bring up, w/o those I don't understand the point to enable ISH.
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Change subject: [wip]acpi: Use boolean instead of int
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Patch Set 3:
(1 comment)
Patchset:
PS3:
enum cb_err should be used instead, since that one is much less ambiguous compared to bool or int
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Change subject: soc/mediatek/mt8196: Enable lastbus debug hardware
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Patch Set 1: Code-Review+2
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Change subject: soc/mediatek/mt8196: Add early init support
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Patch Set 5:
(1 comment)
Patchset:
PS5:
@jarried.lin@mediatek.com @jianjun.wang@mediatek.com please abandon this patch.
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Change subject: mb/google/nissa/var/glassway: Add initial LTE related settings
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Patch Set 4: Code-Review+1
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Change subject: soc/mediatek/mt8196: Add SPI driver support
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Patch Set 1:
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84930/comment/597508cd_03c0a1f9?us… :
PS1, Line 11: Test=Build pass
When will it be run time tested? Any new log messages?
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Change subject: soc/mediatek/mt8196: Add SPI driver support
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Patch Set 1:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84930/comment/4f4ac00a_e1fc76c7?us… :
PS1, Line 9: controlleer
controller
https://review.coreboot.org/c/coreboot/+/84930/comment/3a8e7b63_8e97511e?us… :
PS1, Line 10:
Mention that 8 busses are supported?
File src/soc/mediatek/mt8196/spi.c:
https://review.coreboot.org/c/coreboot/+/84930/comment/2021454a_56bf6b38?us… :
PS1, Line 123: unsigned int
size_t
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Change subject: soc/mediatek/mt8196: Add tracker driver
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Patch Set 1:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84929/comment/2d0234c8_8d695027?us… :
PS1, Line 9: include
including
https://review.coreboot.org/c/coreboot/+/84929/comment/845a1918_c989cd2c?us… :
PS1, Line 10: latches some
: values which could be used for debug
How can this be used? It’d be great if you elaborated?
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