coreboot-gerrit October 2024

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[S] Change in coreboot[main]: Rauru: Enable ChromeOS EC
by Jarried Lin (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Hello Yidi Lin, I'd like you to do a code review. Please visit https://review.coreboot.org/c/coreboot/+/84931?usp=email to review the following change. Change subject: Rauru: Enable ChromeOS EC ...................................................................... Rauru: Enable ChromeOS EC 1. Configure ChromeOS EC 2. Pass GPIO_EC_AP_INT_ODL to the payload Change-Id: I20828eee93975e75dfb777fe29d5e1c3454b5059 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/bootblock.c M src/mainboard/google/rauru/chromeos.c M src/mainboard/google/rauru/gpio.h M src/mainboard/google/rauru/reset.c 5 files changed, 19 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/31/84931/1 diff --git a/src/mainboard/google/rauru/Kconfig b/src/mainboard/google/rauru/Kconfig index 3d9c3e6..011beed 100644 --- a/src/mainboard/google/rauru/Kconfig +++ b/src/mainboard/google/rauru/Kconfig @@ -9,7 +9,7 @@ config VBOOT select VBOOT_VBNV_FLASH - select VBOOT_NO_BOARD_SUPPORT + select EC_GOOGLE_CHROMEEC_SWITCHES select VBOOT_MOCK_SECDATA config BOARD_SPECIFIC_OPTIONS @@ -20,6 +20,10 @@ select COMMON_CBFS_SPI_WRAPPER select SPI_FLASH select SPI_FLASH_INCLUDE_ALL_DRIVERS + select CHROMEOS_USE_EC_WATCHDOG_FLAG if CHROMEOS + select EC_GOOGLE_CHROMEEC + select EC_GOOGLE_CHROMEEC_BOARDID + select EC_GOOGLE_CHROMEEC_SPI config MAINBOARD_DIR string @@ -33,4 +37,8 @@ config BOOT_DEVICE_SPI_FLASH_BUS int default 8 + +config EC_GOOGLE_CHROMEEC_SPI_BUS + hex + default 0x1 endif diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index e0717aa..bbebf52 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -17,6 +17,7 @@ if (CONFIG(PCI)) mtk_pcie_pre_init(); + mtk_spi_init(CONFIG_EC_GOOGLE_CHROMEEC_SPI_BUS, SPI_PAD0_MASK, 3 * MHz, 0); mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios(); diff --git a/src/mainboard/google/rauru/chromeos.c b/src/mainboard/google/rauru/chromeos.c index 863e9a2..a24995f 100644 --- a/src/mainboard/google/rauru/chromeos.c +++ b/src/mainboard/google/rauru/chromeos.c @@ -7,6 +7,8 @@ void setup_chromeos_gpios(void) { + gpio_input(GPIO_EC_AP_INT_ODL); + gpio_output(GPIO_AP_EC_WARM_RST_REQ, 0); gpio_output(GPIO_AP_FP_FW_UP_STRAP, 0); gpio_output(GPIO_BEEP_ON_OD, 0); gpio_output(GPIO_EN_PWR_FP, 0); @@ -20,6 +22,7 @@ struct lb_gpio chromeos_gpios[] = { { GPIO_XHCI_INIT_DONE.id, ACTIVE_HIGH, -1, "XHCI init done" }, { GPIO_EN_SPKR.id, ACTIVE_HIGH, -1, "speaker enable" }, + { GPIO_EC_AP_INT_ODL.id, ACTIVE_LOW, -1, "EC interrupt" }, { GPIO_BEEP_ON_OD.id, ACTIVE_HIGH, -1, "beep enable" }, }; lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios)); diff --git a/src/mainboard/google/rauru/gpio.h b/src/mainboard/google/rauru/gpio.h index 870a02f..b8c9a82 100644 --- a/src/mainboard/google/rauru/gpio.h +++ b/src/mainboard/google/rauru/gpio.h @@ -7,7 +7,9 @@ #define GPIO_BEEP_ON_OD GPIO(PERIPHERAL_EN1) #define GPIO_EN_SPKR GPIO(PERIPHERAL_EN0) +#define GPIO_EC_AP_INT_ODL GPIO(EINT19) #define GPIO_XHCI_INIT_DONE GPIO(EINT28) +#define GPIO_AP_EC_WARM_RST_REQ GPIO(EINT29) #define GPIO_FP_RST_1V8_S3_L GPIO(EINT26) #define GPIO_AP_FP_FW_UP_STRAP GPIO(EINT27) #define GPIO_EN_PWR_FP GPIO(PERIPHERAL_EN3) diff --git a/src/mainboard/google/rauru/reset.c b/src/mainboard/google/rauru/reset.c index 3eb1390..05a576b 100644 --- a/src/mainboard/google/rauru/reset.c +++ b/src/mainboard/google/rauru/reset.c @@ -1,8 +1,11 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include <gpio.h> #include <reset.h> +#include "gpio.h" + void do_board_reset(void) { - /* TODO: add reset function when gpio is ready */ + gpio_output(GPIO_AP_EC_WARM_RST_REQ, 1); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84931?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I20828eee93975e75dfb777fe29d5e1c3454b5059 Gerrit-Change-Number: 84931 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add SPI driver support
by Jarried Lin (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84930?usp=email ) Change subject: soc/mediatek/mt8196: Add SPI driver support ...................................................................... soc/mediatek/mt8196: Add SPI driver support Add SPI controlleer driver code. Test=Build pass BUG=b:317009620 Change-Id: I10dd1105931c4911ce5257803073b7af76115c75 Signed-off-by: Liya Li <ot_liya.li(a)mediatek.corp-partner.google.com> --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/include/soc/spi.h M src/soc/mediatek/mt8196/spi.c 3 files changed, 122 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/30/84930/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 7df8e8a..53d9b35 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -7,7 +7,7 @@ all-y += ../common/i2c.c i2c.c all-y += mtcmos.c all-y += ../common/pll.c pll.c -all-$(CONFIG_SPI_FLASH) += spi.c +all-$(CONFIG_SPI_FLASH) += ../common/spi.c spi.c all-y += timer.c timer_prepare.c all-y += ../common/uart.c diff --git a/src/soc/mediatek/mt8196/include/soc/spi.h b/src/soc/mediatek/mt8196/include/soc/spi.h index 43edc89..4722ae5 100644 --- a/src/soc/mediatek/mt8196/include/soc/spi.h +++ b/src/soc/mediatek/mt8196/include/soc/spi.h @@ -5,10 +5,24 @@ * Chapter number: 13.9 */ -#ifndef SOC_MEDIATEK_MT8196_SPI_H -#define SOC_MEDIATEK_MT8196_SPI_H +#ifndef __SOC_MEDIATEK_MT8196_SPI_H__ +#define __SOC_MEDIATEK_MT8196_SPI_H__ -#include <spi-generic.h> +#include <soc/spi_common.h> + +#define SPI_BUS_NUMBER 8 + +#define GET_SCK_REG(x) x->spi_cfg2_reg +#define GET_TICK_DLY_REG(x) x->spi_cmd_reg + +DEFINE_BITFIELD(SPI_CFG_CS_HOLD, 15, 0) +DEFINE_BITFIELD(SPI_CFG_CS_SETUP, 31, 16) +DEFINE_BITFIELD(SPI_CFG_SCK_LOW, 15, 0) +DEFINE_BITFIELD(SPI_CFG_SCK_HIGH, 31, 16) +DEFINE_BITFIELD(SPI_CFG1_CS_IDLE, 7, 0) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LOOP, 15, 8) +DEFINE_BITFIELD(SPI_CFG1_PACKET_LENGTH, 32, 16) +DEFINE_BITFIELD(SPI_TICK_DLY, 24, 22) /* Initialize SPI NOR Flash Controller */ void mtk_snfc_init(void); diff --git a/src/soc/mediatek/mt8196/spi.c b/src/soc/mediatek/mt8196/spi.c index 770b5b0..f86253e 100644 --- a/src/soc/mediatek/mt8196/spi.c +++ b/src/soc/mediatek/mt8196/spi.c @@ -5,6 +5,8 @@ * Chapter number: 13.9 */ +#include <assert.h> +#include <console/console.h> #include <device/mmio.h> #include <gpio.h> #include <soc/addressmap.h> @@ -12,6 +14,92 @@ #include <soc/spi.h> #include <spi_flash.h> +struct mtk_spi_bus spi_bus[SPI_BUS_NUMBER] = { + { + .regs = (void *)SPI0_BASE, + .cs_gpio = GPIO(SPI0_CSB), + }, + { + .regs = (void *)SPI1_BASE, + .cs_gpio = GPIO(SPI1_CSB), + }, + { + .regs = (void *)SPI2_BASE, + .cs_gpio = GPIO(EINT31), + }, + { + .regs = (void *)SPI3_BASE, + .cs_gpio = GPIO(INT_SIM2), + }, + { + .regs = (void *)SPI4_BASE, + .cs_gpio = GPIO(SPI_CSB_SEC), + }, + { + .regs = (void *)SPI5_BASE, + .cs_gpio = GPIO(SPI5_CSB), + }, + { + .regs = (void *)SPI6_BASE, + .cs_gpio = GPIO(I2SIN1_LRCK), + }, + { + .regs = (void *)SPI7_BASE, + .cs_gpio = GPIO(EINT6), + }, +}; + +static const struct pad_func pad_funcs[SPI_BUS_NUMBER][4] = { + { + PAD_FUNC_DOWN(SPI0_MI, SPI0_MI), + PAD_FUNC_GPIO(SPI0_CSB), + PAD_FUNC_DOWN(SPI0_MO, SPI0_MO), + PAD_FUNC_DOWN(SPI0_CLK, SPI0_CLK), + }, + { + PAD_FUNC_DOWN(SPI1_MI, SPI1_MI), + PAD_FUNC_GPIO(SPI1_CSB), + PAD_FUNC_DOWN(SPI1_MO, SPI1_MO), + PAD_FUNC_DOWN(SPI1_CLK, SPI1_CLK), + }, + { + PAD_FUNC_DOWN(EINT28, SPI2_A_MI), + PAD_FUNC_GPIO(EINT31), + PAD_FUNC_DOWN(EINT29, SPI2_A_MO), + PAD_FUNC_DOWN(EINT30, SPI2_A_CLK), + }, + { + PAD_FUNC_DOWN(EINT1, SPI3_A_MI), + PAD_FUNC_GPIO(INT_SIM2), + PAD_FUNC_DOWN(EINT0, SPI3_A_MO), + PAD_FUNC_DOWN(INT_SIM1, SPI3_A_CLK), + }, + { + PAD_FUNC_DOWN(SPI_MI_SEC, SPI4_A_MI), + PAD_FUNC_GPIO(SPI_CSB_SEC), + PAD_FUNC_DOWN(SPI_MO_SEC, SPI4_A_MO), + PAD_FUNC_DOWN(SPI_CLK_SEC, SPI4_A_CLK), + }, + { + PAD_FUNC_DOWN(SPI5_MI, SPI5_MI), + PAD_FUNC_GPIO(SPI5_CSB), + PAD_FUNC_DOWN(SPI5_MO, SPI5_MO), + PAD_FUNC_DOWN(SPI5_CLK, SPI5_CLK), + }, + { + PAD_FUNC_DOWN(I2SOUT1_DO, SPI6_A_MI), + PAD_FUNC_GPIO(I2SIN1_LRCK), + PAD_FUNC_DOWN(I2SIN1_DI, SPI6_A_MO), + PAD_FUNC_DOWN(I2SIN1_BCK, SPI6_A_CLK), + }, + { + PAD_FUNC_DOWN(EINT8, SPI7_A_MI), + PAD_FUNC_GPIO(EINT6), + PAD_FUNC_DOWN(EINT7, SPI7_A_MO), + PAD_FUNC_DOWN(EINT5, SPI7_A_CLK), + }, +}; + static const struct pad_func nor_pinmux[4] = { PAD_FUNC(SDA10, SF_CK, GPIO_PULL_DOWN), PAD_FUNC(SCL10, SF_CS, GPIO_PULL_UP), @@ -25,6 +113,17 @@ mtk_snfc_init_pad_func(&nor_pinmux[i], GPIO_DRV_14_MA); } +void mtk_spi_set_gpio_pinmux(unsigned int bus, enum spi_pad_mask pad_select) +{ + assert(bus < SPI_BUS_NUMBER); + const struct pad_func *ptr; + + ptr = pad_funcs[bus]; + + for (unsigned int i = 0; i < SPI_BUS_NUMBER; i++) + gpio_set_mode(ptr[i].gpio, ptr[i].func); +} + static const struct spi_ctrlr spi_flash_ctrlr = { .max_xfer_size = 65535, .flash_probe = mtk_spi_flash_probe, @@ -32,6 +131,11 @@ const struct spi_ctrlr_buses spi_ctrlr_bus_map[] = { { + .ctrlr = &spi_ctrlr, + .bus_start = 0, + .bus_end = SPI_BUS_NUMBER - 1, + }, + { .ctrlr = &spi_flash_ctrlr, .bus_start = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, .bus_end = CONFIG_BOOT_DEVICE_SPI_FLASH_BUS, -- To view, visit https://review.coreboot.org/c/coreboot/+/84930?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I10dd1105931c4911ce5257803073b7af76115c75 Gerrit-Change-Number: 84930 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Add tracker driver
by Jarried Lin (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Hung-Te Lin, Yidi Lin, Yu-Ping Wu. Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84929?usp=email ) Change subject: soc/mediatek/mt8196: Add tracker driver ...................................................................... soc/mediatek/mt8196: Add tracker driver Tracker is a debugging tool, include AP/INFRA/PERI tracker. When bus timeout occurs, the system reboots and latches some values which could be used for debug. TEST=build pass BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/include/soc/tracker.h A src/soc/mediatek/mt8196/tracker.c 5 files changed, 204 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/29/84929/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index ff3c54f..7df8e8a 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -17,6 +17,7 @@ bootblock-y += ../common/lastbus_v2.c lastbus.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c +bootblock-y += tracker.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c romstage-y += ../common/cbmem.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index 0aba127..5011e8d 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -6,11 +6,13 @@ #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/spm_mtcmos.h> +#include <soc/tracker.h> #include <soc/wdt.h> void bootblock_soc_init(void) { mtk_mmu_init(); + bustracker_init(); lastbus_init(); mtk_wdt_init(); mt_pll_init(); diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 24cea8f..32a116e 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -139,6 +139,7 @@ UFSHCI_BASE = IO_PHYS + 0x06810000, SSR_TOP_BASE = IO_PHYS + 0x08000000, APINFRA_SSR_AO_DEBUG_BASE = IO_PHYS + 0x080F1000, + VLP_AO_BASE = IO_PHYS + 0x0C000000, VLPCFG_BASE = IO_PHYS + 0x0C001000, SCP_BASE = IO_PHYS + 0x0C004000, SCP_PBUS_BASE = IO_PHYS + 0x0C00D000, diff --git a/src/soc/mediatek/mt8196/include/soc/tracker.h b/src/soc/mediatek/mt8196/include/soc/tracker.h new file mode 100644 index 0000000..cfc36ef --- /dev/null +++ b/src/soc/mediatek/mt8196/include/soc/tracker.h @@ -0,0 +1,60 @@ +/* SPDX-License-Identifier: GPL-2.0-only OR MIT */ + +#ifndef SOC_MEDIATEK_MT8196_TRACKER_H +#define SOC_MEDIATEK_MT8196_TRACKER_H + +#include <stdint.h> + +#define BUS_DBG_CON 0x000 +#define BUS_TRACE_CON_AO_PRESCALE 0x8f8 +#define BUS_TRACE_CON_AO_1_PRESCALE 0x9f8 +#define VLP_TRACE_CON_AO_PRESCALE 0x114 +#define BUS_TRACE_CON_1 0x800 +#define BUS_TRACE_CON_AO_1 0x8FC +#define BUS_TRACE_CON_2 0x900 +#define BUS_TRACE_CON_AO_2 0x9FC +#define VLP_CON_AO 0x30C +#define BUS_TRACE_EN 16 + +#define SYS_TRACK_ENTRY 64 +#define INFRA_ENTRY_NUM 32 +#define VLP_ENTRY_NUM 4 + +#define AR_TRACK_LOG_OFFSET 0x0200 +#define AR_ENTRY_ID_OFFSET 0x0300 +#define AR_TRACK_L_OFFSET 0x0400 +#define AR_TRACK_H_OFFSET 0x0600 +#define AW_TRACK_LOG_OFFSET 0x0800 +#define AW_ENTRY_ID_OFFSET 0x0900 +#define AW_TRACK_L_OFFSET 0x0A00 +#define AW_TRACK_H_OFFSET 0x0C00 + +#define BUSTRACKER_TIMEOUT 0x300 + +enum { + TRACKER_SYSTRACKER = 0, + TRACKER_INFRATRACKER, + TRACKER_VLPSYSTRACKER, + TRACKER_NUM, +}; + +#define BUS_DBG_CON_IRQ_AR_STA0 0x00000100 +#define BUS_DBG_CON_IRQ_AW_STA0 0x00000200 +#define BUS_DBG_CON_IRQ_AR_STA1 0x00100000 +#define BUS_DBG_CON_IRQ_AW_STA1 0x00200000 +#define BUS_DBG_CON_TIMEOUT (BUS_DBG_CON_IRQ_AR_STA0 | BUS_DBG_CON_IRQ_AW_STA0 | \ + BUS_DBG_CON_IRQ_AR_STA1 | BUS_DBG_CON_IRQ_AW_STA1) + +struct tracker { + uintptr_t base_addr; + u32 timeout; + u32 entry; + u32 offset[8]; + const char *str; +}; + +extern struct tracker tracker_data[]; + +void tracker_setup(void); +void bustracker_init(void); +#endif diff --git a/src/soc/mediatek/mt8196/tracker.c b/src/soc/mediatek/mt8196/tracker.c new file mode 100644 index 0000000..37ed082 --- /dev/null +++ b/src/soc/mediatek/mt8196/tracker.c @@ -0,0 +1,140 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/tracker.h> + +/* + * for systracker: + * offset[0] dump from offset 0x100 ~ 0x2F8 + * offset[1] dump from offset 0x300 ~ 0x4FC + * + * for infra tracker: + * offset[0] dump from offset 0x100 ~ 0x1F8 + * offset[1] dump from offset 0x300 ~ 0x3FC + * + * for vlpsys tracker: + * offset[0] dump from offset 0x100 ~ 0x2F8 + * offset[1] dump from offset 0x300 ~ 0x4FC + */ + +struct tracker tracker_data[TRACKER_NUM] = { + [TRACKER_SYSTRACKER] = { + .base_addr = INFRA_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = SYS_TRACK_ENTRY, + .offset[0] = AR_TRACK_LOG_OFFSET, + .offset[1] = AR_ENTRY_ID_OFFSET, + .offset[2] = AR_TRACK_L_OFFSET, + .offset[3] = AR_TRACK_H_OFFSET, + .offset[4] = AW_TRACK_LOG_OFFSET, + .offset[5] = AW_ENTRY_ID_OFFSET, + .offset[6] = AW_TRACK_L_OFFSET, + .offset[7] = AW_TRACK_H_OFFSET, + .str = "systracker", + }, + [TRACKER_INFRATRACKER] = { + .base_addr = INFRA_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = INFRA_ENTRY_NUM, + .offset[0] = AR_TRACK_LOG_OFFSET, + .offset[1] = AR_ENTRY_ID_OFFSET, + .offset[2] = AR_TRACK_L_OFFSET, + .offset[3] = AR_TRACK_H_OFFSET, + .offset[4] = AW_TRACK_LOG_OFFSET, + .offset[5] = AW_ENTRY_ID_OFFSET, + .offset[6] = AW_TRACK_L_OFFSET, + .offset[7] = AW_TRACK_H_OFFSET, + .str = "infra_tracker", + }, + [TRACKER_VLPSYSTRACKER] = { + .base_addr = VLP_TRACKER_BASE, + .timeout = BUS_DBG_CON_TIMEOUT, + .entry = VLP_ENTRY_NUM, + .offset[0] = AR_TRACK_LOG_OFFSET, + .offset[1] = AR_ENTRY_ID_OFFSET, + .offset[2] = AR_TRACK_L_OFFSET, + .offset[3] = AR_TRACK_H_OFFSET, + .offset[4] = AW_TRACK_LOG_OFFSET, + .offset[5] = AW_ENTRY_ID_OFFSET, + .offset[6] = AW_TRACK_L_OFFSET, + .offset[7] = AW_TRACK_H_OFFSET, + .str = "vlp_tracker", + }, +}; + +void tracker_setup(void) +{ + u32 val; + /* + * Set infra/peri tracker timeout. + * timeout = clock_in_mhz / 15 * timeout_in_ms + * + * timeout: 10ms + * ap tracker clock: 26MHz + * infra tracker clock: 26MHz + * vlp tracker clock: 26MHz + */ + val = 26 / 15 * 10000; + + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_PRESCALE), val); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1_PRESCALE), val); + write32((void *)(VLPCFG_BASE + VLP_TRACE_CON_AO_PRESCALE), val); + /* + * Enable infra/peri tracker. + * bit[0] - BUS_DBG_EN + * bit[1] - TIMEOUT_EN + * bit[2] - SLV_ERR_EN + * bit[13] - HALT_ON_TIMEOUT_EN + * bit[14] - BUS_OT_WEN_CTRL + */ + val = BIT(0) | BIT(1) | BIT(2) | BIT(13) | BIT(14); + write32((void *)(VLP_AO_BASE + VLP_CON_AO), val); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_1), val); + write32((void *)(BUS_TRACE_MONITOR_BASE + BUS_TRACE_CON_AO_2), val); +} + +static void tracker_dump_data(void) +{ + u64 reg_entry; + int i, j; + uintptr_t reg_log, reg_id, reg_low, reg_high; + struct tracker *tra; + + for (j = 0; j < TRACKER_NUM; j++) { + tra = &tracker_data[j]; + + if (!(read32((void *)(tra->base_addr)) & tra->timeout)) + continue; + printk(BIOS_INFO, "**Dump %s ar debug register start**\n", tra->str); + for (i = 0; i < tra->entry; i++) { + reg_log = tra->base_addr + tra->offset[0] + i * 4; + reg_id = tra->base_addr + tra->offset[1] + i * 4; + reg_low = tra->base_addr + tra->offset[2] + i * 4; + reg_high = tra->base_addr + tra->offset[3] + i * 4; + reg_entry = ((u64)read32((void *)reg_high)) << 32 | read32((void *)reg_low); + printk(BIOS_INFO, "%#lx:%#x:%#x:%#x:%#x:%#llx\n", reg_low, + read32((void *)reg_log), read32((void *)reg_id), + read32((void *)reg_low), read32((void *)reg_high), reg_entry); + } + printk(BIOS_INFO, "**Dump %s aw debug register start**\n", tra->str); + for (i = 0; i < tra->entry; i++) { + reg_log = tra->base_addr + tra->offset[4] + i * 4; + reg_id = tra->base_addr + tra->offset[5] + i * 4; + reg_low = tra->base_addr + tra->offset[6] + i * 4; + reg_high = tra->base_addr + tra->offset[7] + i * 4; + reg_entry = ((u64)read32((void *)reg_high)) << 32 | read32((void *)reg_low); + printk(BIOS_INFO, "%#lx:%#x:%#x:%#x:%#x:%#llx\n", reg_low, + read32((void *)reg_log), read32((void *)reg_id), + read32((void *)reg_low), read32((void *)reg_high), reg_entry); + } + printk(BIOS_INFO, "**Dump %s debug register end**\n", tra->str); + } +} + +void bustracker_init(void) +{ + tracker_dump_data(); + tracker_setup(); +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84929?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib9784a370acec45ce36a800f3955b9cf96651298 Gerrit-Change-Number: 84929 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com>

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[M] Change in coreboot[main]: soc/mediatek/mt8196: Enable lastbus debug hardware
by Jarried Lin (Code Review) 30 Oct '24

30 Oct '24

Jarried Lin has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84928?usp=email ) Change subject: soc/mediatek/mt8196: Enable lastbus debug hardware ...................................................................... soc/mediatek/mt8196: Enable lastbus debug hardware Lastbus is a bus debug tool. When the bus hangs, the bus transmission information before resetting will be recorded. The watchdog cannot clear it and it will be printed out for bus hanging analysis. TEST=build pass BUG=b:317009620 Signed-off-by: Xiwen Shao <xiwen.shao(a)mediatek.corp-partner.google.com> Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c --- M src/soc/mediatek/mt8196/Makefile.mk M src/soc/mediatek/mt8196/bootblock.c M src/soc/mediatek/mt8196/include/soc/addressmap.h A src/soc/mediatek/mt8196/lastbus.c 4 files changed, 164 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/28/84928/1 diff --git a/src/soc/mediatek/mt8196/Makefile.mk b/src/soc/mediatek/mt8196/Makefile.mk index 6f8f889..ff3c54f 100644 --- a/src/soc/mediatek/mt8196/Makefile.mk +++ b/src/soc/mediatek/mt8196/Makefile.mk @@ -14,6 +14,7 @@ bootblock-y += bootblock.c bootblock-y += ../common/bootblock.c bootblock.c bootblock-y += ../common/early_init.c +bootblock-y += ../common/lastbus_v2.c lastbus.c bootblock-y += ../common/mmu_operations.c bootblock-$(CONFIG_PCI) += ../common/pcie.c pcie.c bootblock-y += ../common/wdt.c ../common/wdt_req.c wdt.c diff --git a/src/soc/mediatek/mt8196/bootblock.c b/src/soc/mediatek/mt8196/bootblock.c index 9adaae0..0aba127 100644 --- a/src/soc/mediatek/mt8196/bootblock.c +++ b/src/soc/mediatek/mt8196/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <soc/early_init.h> +#include <soc/lastbus_v2.h> #include <soc/mmu_operations.h> #include <soc/pll.h> #include <soc/spm_mtcmos.h> @@ -10,6 +11,7 @@ void bootblock_soc_init(void) { mtk_mmu_init(); + lastbus_init(); mtk_wdt_init(); mt_pll_init(); mtcmos_init(); diff --git a/src/soc/mediatek/mt8196/include/soc/addressmap.h b/src/soc/mediatek/mt8196/include/soc/addressmap.h index 73702bf..24cea8f 100644 --- a/src/soc/mediatek/mt8196/include/soc/addressmap.h +++ b/src/soc/mediatek/mt8196/include/soc/addressmap.h @@ -6,6 +6,7 @@ enum { MCUSYS_BASE = 0x0C000000, MCUPM_CFG_BASE = 0x0C240000, + BUS_TRACE_MONITOR_BASE = 0x0D040000, IO_PHYS = 0x10000000, }; @@ -35,11 +36,20 @@ BCRM_INFRA_AO_BASE = IO_PHYS + 0x00022000, BCRM_INFRA1_AO_BASE = IO_PHYS + 0x0002A000, GPIO_BASE = IO_PHYS + 0x0002D000, + DBGSYS_AO_DEBUG_BASE = IO_PHYS + 0x00031000, + APINFRA_IO_AO_DEBUG_BASE = IO_PHYS + 0x00155000, APINFRA_IO_CTRL_AO_BCRM_BASE = IO_PHYS + 0x00156000, + APINFRA_IO_CTRL_AO_DEBUG_BASE = IO_PHYS + 0x00157000, DRAMC_CHA_AO_BASE = IO_PHYS + 0x00230000, + APINFRA_DRAMC_AO_DEBUG_BASE = IO_PHYS + 0x002F1000, EMI0_BASE = IO_PHYS + 0x00469000, EMI0_MPU_BASE = IO_PHYS + 0x00468000, + NEMI_AO_DEBUG_BASE = IO_PHYS + 0x00416000, + SEMI_AO_DEBUG_BASE = IO_PHYS + 0x00516000, EMI1_BASE = IO_PHYS + 0x00569000, + APINFRA_EMI_AO_DEBUG_BASE = IO_PHYS + 0x00611000, + EMI_INFRA_AO_DEBUG_BASE = IO_PHYS + 0x00644000, + APINFRA_BIG4_AO_DEBUG_BASE = IO_PHYS + 0x00691000, DPM_PM_SRAM_BASE = IO_PHYS + 0x00900000, DPM_DM_SRAM_BASE = IO_PHYS + 0x00920000, DPM_CFG_BASE = IO_PHYS + 0x00940000, @@ -75,12 +85,21 @@ I2C8_BASE = IO_PHYS + 0x03B30000, I2C9_BASE = IO_PHYS + 0x03BB0000, IMP_IIC_WRAP_N_BASE = IO_PHYS + 0x03C30000, + APINFRA_IO_INTF_AO_DEBUG_BASE = IO_PHYS + 0x04011000, APINFRA_IO_NOC_AO_BCRM_BASE = IO_PHYS + 0x04012000, + APINFRA_MEM_INTF_AO_DEBUG_BASE = IO_PHYS + 0x04031000, APINFRA_MEM_NOC_AO_BCRM_BASE = IO_PHYS + 0x04032000, + APINFRA_INT_AO_DEBUG_BASE = IO_PHYS + 0x04051000, + APINFRA_MMU_AO_DEBUG_BASE = IO_PHYS + 0x04071000, + APINFRA_SLB_AO_DEBUG_BASE = IO_PHYS + 0x04091000, + APINFRA_MEM_AO_DEBUG_BASE = IO_PHYS + 0x04116000, APINFRA_MEM_CTRL_AO_BCRM_BASE = IO_PHYS + 0x04124000, + APINFRA_MEM_CTRL_AO_DEBUG_BASE = IO_PHYS + 0x04125000, APIFRBUS_AO_MEM_REG_BASE = IO_PHYS + 0x04126000, THERM_CTRL_BASE = IO_PHYS + 0x04414000, VOTE_BASE = IO_PHYS + 0x04500000, + DBG_TRACKER_BASE = IO_PHYS + 0x04780000, + INFRA_TRACKER_BASE = IO_PHYS + 0x047A0000, UART0_BASE = IO_PHYS + 0x06000000, SPI0_BASE = IO_PHYS + 0x06110000, SPI1_BASE = IO_PHYS + 0x06130000, @@ -113,11 +132,13 @@ PERI_PAR_BCRM_BASE = IO_PHYS + 0x06610000, PERICFG_AO_SEC_BASE = IO_PHYS + 0x06630000, PERICFG_AO_BASE = IO_PHYS + 0x06640000, + PERI_PAR_AO_DEBUG_BASE = IO_PHYS + 0x06680000, SSUSB_IPPC_BASE = IO_PHYS + 0x06703E00, SSUSB_SIF_BASE = IO_PHYS + 0x06730300, USB_BUS_BCRM_BASE = IO_PHYS + 0x06781000, UFSHCI_BASE = IO_PHYS + 0x06810000, SSR_TOP_BASE = IO_PHYS + 0x08000000, + APINFRA_SSR_AO_DEBUG_BASE = IO_PHYS + 0x080F1000, VLPCFG_BASE = IO_PHYS + 0x0C001000, SCP_BASE = IO_PHYS + 0x0C004000, SCP_PBUS_BASE = IO_PHYS + 0x0C00D000, @@ -128,7 +149,9 @@ PMIF_SPMI_BASE = IO_PHYS + 0x0C01A000, SPMI_MST_BASE = IO_PHYS + 0x0C01C000, SPMI_MST_P_BASE = IO_PHYS + 0x0C01C800, + VLP_AO_DEBUG_BASE = IO_PHYS + 0x0C031000, SYSTIMER_BASE = IO_PHYS + 0x0C400000, + VLP_TRACKER_BASE = IO_PHYS + 0x0C4E0000, MMVOTE_MMSYS_CONFIG_BASE = IO_PHYS + 0x12000000, MMVOTE_MMSYS1_CONFIG_BASE = IO_PHYS + 0x12400000, MMVOTE_OVLSYS_CONFIG_BASE = IO_PHYS + 0x12800000, @@ -143,6 +166,7 @@ MMVOTE_CAM_MAIN_R1A_BASE = IO_PHYS + 0x1A000000, MMVOTE_CCU_MAIN_BASE = IO_PHYS + 0x1C800000, MMVOTE_DISP_VDISP_AO_CONFIG_BASE = IO_PHYS + 0x1E800000, + MMUP_AO_DEBUG_BASE = IO_PHYS + 0x21A22000, MMVOTE_BASE = IO_PHYS + 0x21B00000, MMPC_BASE = IO_PHYS + 0x21B50000, MMSYS_CONFIG_BASE = IO_PHYS + 0x22000000, diff --git a/src/soc/mediatek/mt8196/lastbus.c b/src/soc/mediatek/mt8196/lastbus.c new file mode 100644 index 0000000..6e2f032 --- /dev/null +++ b/src/soc/mediatek/mt8196/lastbus.c @@ -0,0 +1,137 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <console/console.h> +#include <device/mmio.h> +#include <soc/addressmap.h> +#include <soc/lastbus_v2.h> + +static const struct lastbus_monitor monitors[] = { + { + .name = "debug_ctrl_ao_DBGSYS_AO", + .base = DBGSYS_AO_DEBUG_BASE, + .num_ports = 1, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_IO_AO", + .base = APINFRA_IO_AO_DEBUG_BASE, + .num_ports = 37, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_IO_CTRL_AO", + .base = APINFRA_IO_CTRL_AO_DEBUG_BASE, + .num_ports = 3, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_DRAMC_AO", + .base = APINFRA_DRAMC_AO_DEBUG_BASE, + .num_ports = 11, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_EMI_AO", + .base = APINFRA_EMI_AO_DEBUG_BASE, + .num_ports = 15, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_BIG4_AO", + .base = APINFRA_BIG4_AO_DEBUG_BASE, + .num_ports = 13, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_IO_INTF_AO", + .base = APINFRA_IO_INTF_AO_DEBUG_BASE, + .num_ports = 33, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_MEM_INTF_AO", + .base = APINFRA_MEM_INTF_AO_DEBUG_BASE, + .num_ports = 42, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_INT_AO", + .base = APINFRA_INT_AO_DEBUG_BASE, + .num_ports = 7, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_MMU_AO", + .base = APINFRA_MMU_AO_DEBUG_BASE, + .num_ports = 8, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_SLB_AO", + .base = APINFRA_SLB_AO_DEBUG_BASE, + .num_ports = 8, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_MEM_AO", + .base = APINFRA_MEM_AO_DEBUG_BASE, + .num_ports = 26, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_MEM_CTRL_AO", + .base = APINFRA_MEM_CTRL_AO_DEBUG_BASE, + .num_ports = 2, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_APINFRA_SSR_AO", + .base = APINFRA_SSR_AO_DEBUG_BASE, + .num_ports = 5, + .bus_freq_mhz = 26, + }, + { + .name = "debug_ctrl_ao_NEMI_AO", + .base = NEMI_AO_DEBUG_BASE, + .num_ports = 18, + .bus_freq_mhz = 800, + }, + { + .name = "debug_ctrl_ao_SEMI_AO", + .base = SEMI_AO_DEBUG_BASE, + .num_ports = 18, + .bus_freq_mhz = 800, + }, + { + .name = "debug_ctrl_ao_EMI_INFRA_AO", + .base = EMI_INFRA_AO_DEBUG_BASE, + .num_ports = 70, + .bus_freq_mhz = 800, + }, + { + .name = "debug_ctrl_ao_PERI_PAR_AO", + .base = PERI_PAR_AO_DEBUG_BASE, + .num_ports = 27, + .bus_freq_mhz = 78, + }, + { + .name = "debug_ctrl_ao_VLP_AO", + .base = VLP_AO_DEBUG_BASE, + .num_ports = 17, + .bus_freq_mhz = 156, + }, + { + .name = "debug_ctrl_ao_MMUP_AO", + .base = MMUP_AO_DEBUG_BASE, + .num_ports = 25, + .bus_freq_mhz = 728, + }, +}; + +const struct lastbus_config lastbus_cfg = { + .latch_platform = "MT8196", + .timeout_ms = 200, + .timeout_type = 0, + .num_used_monitors = ARRAY_SIZE(monitors), + .monitors = monitors, +}; -- To view, visit https://review.coreboot.org/c/coreboot/+/84928?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib030d88faa2d4d6f6a8501f8c752deeafff92c5c Gerrit-Change-Number: 84928 Gerrit-PatchSet: 1 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Add initial LTE related settings
by Daniel Peng (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84925?usp=email to look at the new patch set (#3). Change subject: mb/google/nissa/var/glassway: Add initial LTE related settings ...................................................................... mb/google/nissa/var/glassway: Add initial LTE related settings 1. Add DB_1C_LTE 4 on DB_USB fw_config. 2. Implement WWAN power sequencing. 3. Disable LTE-related GPIOs based on fw_config. 4. Add I2C SX9324 (P-sensor) support. BUG=b:374666995 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/glassway/fw_config.c M src/mainboard/google/brya/variants/glassway/include/variant/gpio.h M src/mainboard/google/brya/variants/glassway/overridetree.cb 4 files changed, 117 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/84925/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Gerrit-Change-Number: 84925 Gerrit-PatchSet: 3 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Initial LTE Related Settings
by Paul Menzel (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Daniel Peng, Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Paul Menzel has posted comments on this change by Daniel Peng. ( https://review.coreboot.org/c/coreboot/+/84925?usp=email ) Change subject: mb/google/nissa/var/glassway: Initial LTE Related Settings ...................................................................... Patch Set 2: (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84925/comment/aa6ee3bd_a8be5db9?us… : PS2, Line 7: Initial LTE Related Settings Please make it a statement by adding a verb (in imperative mood): > Add initial LTE related settings https://review.coreboot.org/c/coreboot/+/84925/comment/24d8f0ee_d311eafc?us… : PS2, Line 9: fw_config . Please remove the space before the dot/period, or remove the period at the end of the items. https://review.coreboot.org/c/coreboot/+/84925/comment/9e552618_9a36854e?us… : PS2, Line 12: SX9324(P-sensor) Please add a space before (. https://review.coreboot.org/c/coreboot/+/84925/comment/404108c1_dd5f5e10?us… : PS2, Line 12: 4. Add I2C SX9324(P-sensor) support. What is the sensor needed for in LTE setting? Should the proximity sensor be a separate commit? https://review.coreboot.org/c/coreboot/+/84925/comment/8533d8f5_b0523dd4?us… : PS2, Line 13: Please add the schematics file name. -- To view, visit https://review.coreboot.org/c/coreboot/+/84925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Gerrit-Change-Number: 84925 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 12:18:09 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs
by Michał Żygowski (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Paul Menzel. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/84926?usp=email ) Change subject: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs ...................................................................... Patch Set 3: (1 comment) File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/84926/comment/46e80058_d3246556?us… : PS2, Line 890: fprintf(stderr, "Invalid TPM1.2 log entry overflowing cbmem area\n"); > Nothing you can do actually. There is just garbage in memory. The subsequent patch is supposed to ensure it never happens CB:84927 -- To view, visit https://review.coreboot.org/c/coreboot/+/84926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Gerrit-Change-Number: 84926 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Oct 2024 10:03:26 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Michał Żygowski <michal.zygowski(a)3mdeb.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs
by Michał Żygowski (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Paul Menzel. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/84926?usp=email ) Change subject: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs ...................................................................... Patch Set 3: (1 comment) File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/84926/comment/290782a2_2ee04e6a?us… : PS2, Line 890: fprintf(stderr, "Invalid TPM1.2 log entry overflowing cbmem area\n"); > Would it be helpful to add the length/size numbers? […] Nothing you can do actually. There is just garbage in memory. -- To view, visit https://review.coreboot.org/c/coreboot/+/84926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Gerrit-Change-Number: 84926 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Oct 2024 10:03:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs
by Michał Żygowski (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Paul Menzel. Michał Żygowski has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/84926?usp=email ) Change subject: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs ...................................................................... Patch Set 3: (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84926/comment/e985ec72_1aa21b6c?us… : PS2, Line 9: utilit yassumed > utilit*y* assumed Done https://review.coreboot.org/c/coreboot/+/84926/comment/94c3a0fd_2cfea89e?us… : PS2, Line 15: TEST=Dump TCG TPM1.2 event log on Dell OptiPlex 7010 and see > Please add the exact command you used. Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Gerrit-Change-Number: 84926 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Oct 2024 10:02:32 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs
by Michał Żygowski (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Michał Żygowski. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84926?usp=email to look at the new patch set (#3). Change subject: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs ...................................................................... util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs The utility assumed that TCG TPM log area is zeroed and then filled with events but it does not have to be true. If there is garbage after the last valid event entry, the utility will most likely access data outside of the cbmem area containing the logs. Relevant issue: https://github.com/linuxboot/heads/issues/1608 TEST=Dump TCG TPM1.2 event log on Dell OptiPlex 7010 with 'cbmem -L' and see "Invalid TPM1.2 log entry overflowing cbmem area" error is printed. Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M util/cbmem/cbmem.c 1 file changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/84926/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Gerrit-Change-Number: 84926 Gerrit-PatchSet: 3 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com>

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