coreboot-gerrit October 2024

coreboot-gerrit@coreboot.org

1 participants
2622 discussions

[S] Change in coreboot[main]: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs
by Paul Menzel (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Michał Żygowski. Paul Menzel has posted comments on this change by Michał Żygowski. ( https://review.coreboot.org/c/coreboot/+/84926?usp=email ) Change subject: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs ...................................................................... Patch Set 2: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84926/comment/1625f5cb_f807c396?us… : PS2, Line 9: utilit yassumed utilit*y* assumed https://review.coreboot.org/c/coreboot/+/84926/comment/79f183fd_d64208be?us… : PS2, Line 15: TEST=Dump TCG TPM1.2 event log on Dell OptiPlex 7010 and see Please add the exact command you used. File util/cbmem/cbmem.c: https://review.coreboot.org/c/coreboot/+/84926/comment/84a61fb0_b4371ad7?us… : PS2, Line 890: fprintf(stderr, "Invalid TPM1.2 log entry overflowing cbmem area\n"); Would it be helpful to add the length/size numbers? What should users do, if they see this message? -- To view, visit https://review.coreboot.org/c/coreboot/+/84926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Gerrit-Change-Number: 84926 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 09:54:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: security/tpm/tspi/log-tpm1.c: Clear whole log area on creation
by Michał Żygowski (Code Review) 30 Oct '24

30 Oct '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84927?usp=email ) Change subject: security/tpm/tspi/log-tpm1.c: Clear whole log area on creation ...................................................................... security/tpm/tspi/log-tpm1.c: Clear whole log area on creation The log area was not entirely cleared on creation resulting in garbage after the last valid lgo entry. It caused the cbmem utility to parse invalid events and access data outside the log area. In the TPM2 log sources, the entire area is being cleared, thus the issue has not been observed. Change-Id: I7c780b62b1c6507e1dd1806b20b0270e364cde3d Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M src/security/tpm/tspi/log-tpm1.c 1 file changed, 1 insertion(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/27/84927/1 diff --git a/src/security/tpm/tspi/log-tpm1.c b/src/security/tpm/tspi/log-tpm1.c index 481b569..453e74b 100644 --- a/src/security/tpm/tspi/log-tpm1.c +++ b/src/security/tpm/tspi/log-tpm1.c @@ -33,7 +33,7 @@ if (!tclt) return NULL; - memset(tclt, 0, sizeof(*tclt)); + memset(tclt, 0, tpm_log_len); hdr = &tclt->spec_id; /* Fill in first "header" entry. */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84927?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7c780b62b1c6507e1dd1806b20b0270e364cde3d Gerrit-Change-Number: 84927 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

[S] Change in coreboot[main]: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs
by Michał Żygowski (Code Review) 30 Oct '24

30 Oct '24

Michał Żygowski has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/84926?usp=email ) Change subject: util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs ...................................................................... util/cbmem/cbmem.c: Avoid overflows when parsing TCG TPM logs The utilit yassumed that TCG TPM log area is zeroed and then filled with events but it does not have to be true. If there is garbage after the last valid event entry, the utility will most likely access data outside of the cbmem area containing the logs. Relevant issue: https://github.com/linuxboot/heads/issues/1608 TEST=Dump TCG TPM1.2 event log on Dell OptiPlex 7010 and see "Invalid TPM1.2 log entry overflowing cbmem area" error is printed. Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M util/cbmem/cbmem.c 1 file changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/84926/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Gerrit-Change-Number: 84926 Gerrit-PatchSet: 2 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

[S] Change in coreboot[main]: util/cbmem/cbmem.c: Avoid overflwos when parsing TCG TPM logs
by Michał Żygowski (Code Review) 30 Oct '24

30 Oct '24

Michał Żygowski has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84926?usp=email ) Change subject: util/cbmem/cbmem.c: Avoid overflwos when parsing TCG TPM logs ...................................................................... util/cbmem/cbmem.c: Avoid overflwos when parsing TCG TPM logs The utilit yassumed that TCG TPM log area is zeroed and then filled with events but it does not have to be true. If there is garbage after the last valid event entry, the utility will most likely access data outside of the cbmem area containing the logs. Relevant issue: https://github.com/linuxboot/heads/issues/1608 TEST=Dump TCG TPM1.2 event log on Dell OptiPlex 7010 and see "Invalid TPM1.2 log entry overflowing cbmem area" error is printed. Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Signed-off-by: Michał Żygowski <michal.zygowski(a)3mdeb.com> --- M util/cbmem/cbmem.c 1 file changed, 17 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/26/84926/1 diff --git a/util/cbmem/cbmem.c b/util/cbmem/cbmem.c index 15b6770..47444d3 100644 --- a/util/cbmem/cbmem.c +++ b/util/cbmem/cbmem.c @@ -862,7 +862,7 @@ printf("%s", tpm_event_types[event_type]); } -static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log) +static void parse_tpm12_log(const struct tcpa_spec_entry *spec_log, size_t size) { const uint8_t zero_block[sizeof(struct tcpa_spec_entry)] = {0}; @@ -883,6 +883,13 @@ uint32_t len; struct tcpa_log_entry *log_entry = (void *)current; uint32_t event_type = le32toh(log_entry->event_type); + current += sizeof(struct tcpa_log_entry); + len = le32toh(log_entry->event_data_size); + + if (current + len >= (uintptr_t)spec_log + size) { + fprintf(stderr, "Invalid TPM1.2 log entry overflowing cbmem area\n"); + break; + } printf("TCPA log entry %u:\n", ++counter); printf("\tPCR: %d\n", le32toh(log_entry->pcr)); @@ -891,8 +898,6 @@ printf("\n"); printf("\tDigest: "); print_hex_line(log_entry->digest, SHA1_DIGEST_SIZE); - current += sizeof(struct tcpa_log_entry); - len = le32toh(log_entry->event_data_size); if (len != 0) { current += len; printf("\tEvent data: "); @@ -947,7 +952,7 @@ return current - (uintptr_t)&log_entry->digest_count; } -static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log) +static void parse_tpm2_log(const struct tcg_efi_spec_id_event *tpm2_log, size_t size) { const uint8_t zero_block[12] = {0}; /* Only PCR index, event type and digest count */ @@ -990,6 +995,12 @@ /* Now event size and event are left to be parsed */ len = le32toh(*(uint32_t *)current); current += sizeof(uint32_t); + + if (current + len >= (uintptr_t)tpm2_log + size) { + fprintf(stderr, "Invalid TPM2.0 log entry overflowing cbmem area\n"); + break; + } + if (len != 0) { printf("\tEvent data: %.*s\n", len, (const char *)current); current += len; @@ -1017,7 +1028,7 @@ tspec_entry->spec_version_minor == 2 && tspec_entry->spec_errata >= 1 && le32toh(tspec_entry->entry.event_type) == EV_NO_ACTION) { - parse_tpm12_log(tspec_entry); + parse_tpm12_log(tspec_entry, size); } else { fprintf(stderr, "Unknown TPM1.2 log specification\n"); } @@ -1030,7 +1041,7 @@ if (tcg_spec_entry->spec_version_major == 2 && tcg_spec_entry->spec_version_minor == 0 && le32toh(tcg_spec_entry->event_type) == EV_NO_ACTION) { - parse_tpm2_log(tcg_spec_entry); + parse_tpm2_log(tcg_spec_entry, size); } else { fprintf(stderr, "Unknown TPM2 log specification.\n"); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84926?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I7e057db3378b701d046d4e578272b10f294142a7 Gerrit-Change-Number: 84926 Gerrit-PatchSet: 1 Gerrit-Owner: Michał Żygowski <michal.zygowski(a)3mdeb.com>

1 0

[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Initial LTE Related Settings
by Daniel Peng (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Subrata Banik, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84925?usp=email to look at the new patch set (#2). Change subject: mb/google/nissa/var/glassway: Initial LTE Related Settings ...................................................................... mb/google/nissa/var/glassway: Initial LTE Related Settings 1. Add DB_1C_LTE 4 on DB_USB fw_config . 2. Implement WWAN power sequencing. 3. Disable LTE-related GPIOs based on fw_config. 4. Add I2C SX9324(P-sensor) support. BUG=b:374666995 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/glassway/fw_config.c M src/mainboard/google/brya/variants/glassway/include/variant/gpio.h M src/mainboard/google/brya/variants/glassway/overridetree.cb 4 files changed, 117 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/84925/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Gerrit-Change-Number: 84925 Gerrit-PatchSet: 2 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>

1 0

[M] Change in coreboot[main]: mb/google/nissa/var/glassway: Initial LTE Related Settings
by Daniel Peng (Code Review) 30 Oct '24

30 Oct '24

Daniel Peng has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84925?usp=email ) Change subject: mb/google/nissa/var/glassway: Initial LTE Related Settings ...................................................................... mb/google/nissa/var/glassway: Initial LTE Related Settings 1. Add DB_1C_LTE 4 on DB_USB fw_config . 2. Implement WWAN power sequencing. 3. Disable LTE-related GPIOs based on fw_config. 4. Add I2C SX9324(P-sensor) support. BUG=b:374666995 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot chromeos-bootimage Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Signed-off-by: Daniel Peng <Daniel_Peng(a)pegatron.corp-partner.google.com> --- M src/mainboard/google/brya/Kconfig M src/mainboard/google/brya/variants/glassway/fw_config.c M src/mainboard/google/brya/variants/glassway/include/variant/gpio.h M src/mainboard/google/brya/variants/glassway/overridetree.cb 4 files changed, 117 insertions(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/25/84925/1 diff --git a/src/mainboard/google/brya/Kconfig b/src/mainboard/google/brya/Kconfig index 2981ea7..7af921c 100644 --- a/src/mainboard/google/brya/Kconfig +++ b/src/mainboard/google/brya/Kconfig @@ -277,7 +277,10 @@ select CHROMEOS_WIFI_SAR if CHROMEOS select DRIVERS_GENERIC_GPIO_KEYS select DRIVERS_GENESYSLOGIC_GL9750 + select DRIVERS_I2C_SX9324 + select DRIVERS_I2C_SX9324_SUPPORT_LEGACY_LINUX_DRIVER select EC_GOOGLE_CHROMEEC_INCLUDE_SSFC_IN_FW_CONFIG + select HAVE_WWAN_POWER_SEQUENCE select INTEL_GMA_HAVE_VBT config BOARD_GOOGLE_GOTHRAX diff --git a/src/mainboard/google/brya/variants/glassway/fw_config.c b/src/mainboard/google/brya/variants/glassway/fw_config.c index b4dfc50..3cca3fe 100644 --- a/src/mainboard/google/brya/variants/glassway/fw_config.c +++ b/src/mainboard/google/brya/variants/glassway/fw_config.c @@ -5,6 +5,19 @@ #include <console/console.h> #include <fw_config.h> +static const struct pad_config lte_disable_pads[] = { + /* A8 : WWAN_RF_DISABLE_ODL */ + PAD_NC(GPP_A8, NONE), + /* D6 : WWAN_EN */ + PAD_NC(GPP_D6, NONE), + /* F12 : WWAN_RST_L */ + PAD_NC_LOCK(GPP_F12, NONE, LOCK_CONFIG), + /* H19 : SOC_I2C_SUB_INT_ODL */ + PAD_NC(GPP_H19, NONE), + /* H23 : WWAN_SAR_DETECT_ODL */ + PAD_NC(GPP_H23, NONE), +}; + static const struct pad_config stylus_disable_pads[] = { /* F13 : SOC_PEN_DETECT_R_ODL */ PAD_NC_LOCK(GPP_F13, NONE, LOCK_CONFIG), @@ -14,6 +27,12 @@ void fw_config_gpio_padbased_override(struct pad_config *padbased_table) { + if (!fw_config_probe(FW_CONFIG(DB_USB, DB_1C_LTE))) { + printk(BIOS_INFO, "Disable LTE-related GPIO pins on Glassway serial projects.\n"); + gpio_padbased_override(padbased_table, lte_disable_pads, + ARRAY_SIZE(lte_disable_pads)); + } + if (fw_config_probe(FW_CONFIG(STYLUS, STYLUS_ABSENT))) { printk(BIOS_INFO, "Disable Stylus GPIO pins.\n"); gpio_padbased_override(padbased_table, stylus_disable_pads, diff --git a/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h index c4fe342..c96b01f 100644 --- a/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h +++ b/src/mainboard/google/brya/variants/glassway/include/variant/gpio.h @@ -5,4 +5,8 @@ #include <baseboard/gpio.h> +#define WWAN_FCPO GPP_D6 +#define WWAN_RST GPP_F12 +#define T2_OFF_MS 20 + #endif diff --git a/src/mainboard/google/brya/variants/glassway/overridetree.cb b/src/mainboard/google/brya/variants/glassway/overridetree.cb index 85c08db..47b990e 100644 --- a/src/mainboard/google/brya/variants/glassway/overridetree.cb +++ b/src/mainboard/google/brya/variants/glassway/overridetree.cb @@ -8,10 +8,11 @@ option AUDIO_ALC5650_ALC5650 1 end field DB_USB 5 7 - option DB_NONE 0 - option DB_1C 1 - option DB_1A 2 - option DB_1C_1A 3 + option DB_NONE 0 + option DB_1C 1 + option DB_1A 2 + option DB_1C_1A 3 + option DB_1C_LTE 4 end field SD_CARD 8 option SD_ABSENT 0 @@ -426,6 +427,78 @@ end end end #I2C1 + device ref i2c2 on + chip drivers/i2c/sx9324 + register "desc" = ""SAR Proximity Sensor"" + register "irq" = "ACPI_IRQ_LEVEL_LOW(GPP_H19_IRQ)" + register "speed" = "I2C_SPEED_FAST" + register "uid" = "1" + register "reg_gnrl_ctrl0" = "0x16" + register "reg_gnrl_ctrl1" = "0x21" + register "reg_afe_ctrl0" = "0x20" + register "reg_afe_ctrl3" = "0x00" + register "reg_afe_ctrl4" = "0x46" + register "reg_afe_ctrl6" = "0x00" + register "reg_afe_ctrl7" = "0x46" + register "reg_afe_ph0" = "0x3d" + register "reg_afe_ph1" = "0x1b" + register "reg_afe_ph2" = "0x1f" + register "reg_afe_ph3" = "0x3d" + register "reg_afe_ctrl8" = "0x12" + register "reg_afe_ctrl9" = "0x08" + register "reg_prox_ctrl0" = "0x0b" + register "reg_prox_ctrl1" = "0x0b" + register "reg_prox_ctrl2" = "0x20" + register "reg_prox_ctrl3" = "0x20" + register "reg_prox_ctrl4" = "0x0c" + register "reg_prox_ctrl5" = "0x00" + register "reg_prox_ctrl6" = "0x20" + register "reg_prox_ctrl7" = "0xc0" + register "reg_adv_ctrl0" = "0x00" + register "reg_adv_ctrl1" = "0x00" + register "reg_adv_ctrl2" = "0x00" + register "reg_adv_ctrl3" = "0x00" + register "reg_adv_ctrl4" = "0x00" + register "reg_adv_ctrl5" = "0x05" + register "reg_adv_ctrl6" = "0x00" + register "reg_adv_ctrl7" = "0x00" + register "reg_adv_ctrl8" = "0x00" + register "reg_adv_ctrl9" = "0x00" + register "reg_adv_ctrl10" = "0x00" + register "reg_adv_ctrl11" = "0x00" + register "reg_adv_ctrl12" = "0x00" + register "reg_adv_ctrl13" = "0x00" + register "reg_adv_ctrl14" = "0x80" + register "reg_adv_ctrl15" = "0x0c" + register "reg_adv_ctrl16" = "0x04" + register "reg_adv_ctrl17" = "0x70" + register "reg_adv_ctrl18" = "0x20" + register "reg_adv_ctrl19" = "0x00" + register "reg_adv_ctrl20" = "0x00" + register "reg_irq_msk" = "0x60" + register "reg_irq_cfg0" = "0x00" + register "reg_irq_cfg1" = "0x80" + register "reg_irq_cfg2" = "0x00" + + register "ph0_pin" = "{1, 3, 3}" + register "ph1_pin" = "{3, 2, 1}" + register "ph2_pin" = "{3, 3, 1}" + register "ph3_pin" = "{1, 3, 3}" + register "ph01_resolution" = "512" + register "ph23_resolution" = "512" + register "startup_sensor" = "1" + register "ph01_proxraw_strength" = "3" + register "ph23_proxraw_strength" = "3" + register "avg_pos_strength" = "256" + register "cs_idle_sleep" = ""gnd"" + register "int_comp_resistor" = ""lowest"" + register "input_precharge_resistor_ohms" = "4000" + register "input_analog_gain" = "1" + device i2c 28 on + probe DB_USB DB_1C_LTE + end + end + end #I2C2 device ref i2c3 on chip drivers/i2c/generic register "hid" = ""RTL5682"" @@ -598,6 +671,13 @@ end end chip drivers/usb/acpi + register "desc" = ""USB2 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb2_port4 on + probe DB_USB DB_1C_LTE + end + end + chip drivers/usb/acpi register "desc" = ""USB2 Camera"" register "type" = "UPC_TYPE_INTERNAL" device ref usb2_port6 on end @@ -632,6 +712,13 @@ probe DB_USB DB_1C_1A end end + chip drivers/usb/acpi + register "desc" = ""USB3 WWAN"" + register "type" = "UPC_TYPE_INTERNAL" + device ref usb3_port2 on + probe DB_USB DB_1C_LTE + end + end end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/84925?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ida56ff338d82f48aef419a65830a3380c83123d5 Gerrit-Change-Number: 84925 Gerrit-PatchSet: 1 Gerrit-Owner: Daniel Peng <daniel_peng(a)pegatron.corp-partner.google.com>

1 0

[S] Change in coreboot[main]: soc/mediatek/mt8196: Disable irq2axi feature
by Paul Menzel (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Hung-Te Lin, Jarried Lin, Runyang Chen. Paul Menzel has posted comments on this change by Jarried Lin. ( https://review.coreboot.org/c/coreboot/+/84896?usp=email ) Change subject: soc/mediatek/mt8196: Disable irq2axi feature ...................................................................... Patch Set 3: (3 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84896/comment/09e3c19d_72cfbba5?us… : PS1, Line 13: TEST=Build pass and the interrupt can be correctly handled. Please mention the problems/symptoms in the commit message. > Yes, we have checked it, What do you refer to? `/proc/interrupts`? File src/soc/mediatek/mt8196/irq2axi.c: https://review.coreboot.org/c/coreboot/+/84896/comment/8f2b2e57_409fb157?us… : PS3, Line 8: printk(BIOS_INFO, "%s\n", __func__); Please make it debug level or reword it. info level messages should be written, that users can understand it. File src/soc/mediatek/mt8196/irq2axi_init.c: https://review.coreboot.org/c/coreboot/+/84896/comment/ce2871be_a70457fb?us… : PS1, Line 9: printk(BIOS_INFO, "%s irq uninit\n", __func__); > Done I made a new comment. -- To view, visit https://review.coreboot.org/c/coreboot/+/84896?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e89a0ee75e574a4b9e8df0a0f6a5f6e03bba2d6 Gerrit-Change-Number: 84896 Gerrit-PatchSet: 3 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Gerrit-Attention: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 08:45:29 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Runyang Chen <runyang.chen(a)mediatek.corp-partner.google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[S] Change in coreboot[main]: mb/google/rauru: Add new board variant Hylia
by Yu-Ping Wu (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84924?usp=email ) Change subject: mb/google/rauru: Add new board variant Hylia ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Gerrit-Change-Number: 84924 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 08:40:43 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[S] Change in coreboot[main]: soc/intel/common/gpio: add function to lock GPIO configuration
by Subrata Banik (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Bora Guvendik, Cliff Huang, Jérémy Compostella, Pranava Y N. Subrata Banik has posted comments on this change by Cliff Huang. ( https://review.coreboot.org/c/coreboot/+/84901?usp=email ) Change subject: soc/intel/common/gpio: add function to lock GPIO configuration ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/common/block/gpio/gpio.c: https://review.coreboot.org/c/coreboot/+/84901/comment/1bb2a68d_f6b996c1?us… : PS3, Line 485: /* Clear lock for the exception PADs */ we won't be able to clear the locking after we reaches ramstage (after FSP-S exits) -- To view, visit https://review.coreboot.org/c/coreboot/+/84901?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iabe4e4b1d282a5f6cae8f330100c9139e0c2691d Gerrit-Change-Number: 84901 Gerrit-PatchSet: 3 Gerrit-Owner: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Wonkyu Kim <wonkyu.kim(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Hannah Williams <hannah.williams(a)intel.com> Gerrit-Attention: Bora Guvendik <bora.guvendik(a)intel.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Pranava Y N <pranavayn(a)google.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 08:37:14 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[S] Change in coreboot[main]: mb/google/rauru: Add new board variant Hylia
by Yang Wu (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yidi Lin, Yu-Ping Wu. Yang Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84924?usp=email ) Change subject: mb/google/rauru: Add new board variant Hylia ...................................................................... Patch Set 3: (1 comment) File src/mainboard/google/rauru/Kconfig.name: https://review.coreboot.org/c/coreboot/+/84924/comment/18ab2809_2a4be8c5?us… : PS2, Line 8: config BOARD_GOOGLE_HYLIA > sort all the 3 boards Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Gerrit-Change-Number: 84924 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 08:19:11 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Yu-Ping Wu <yupingso(a)google.com>

1 0

← Newer
1
...
8
9
10
11
12
13
14
...
263
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2024