coreboot-gerrit October 2024

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[S] Change in coreboot[main]: mb/google/rauru: Add new board variant Hylia
by Yang Wu (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu, Yidi Lin. Hello Hung-Te Lin, Xinxiong Xu, Yidi Lin, Yu-Ping Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84924?usp=email to look at the new patch set (#3). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/rauru: Add new board variant Hylia ...................................................................... mb/google/rauru: Add new board variant Hylia Add a new Rauru follower 'Hylia'. BRANCH=rauru BUG=b:376357839 TEST=emerge-rauru coreboot chromeos-bootimage Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Signed-off-by: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/rauru/Kconfig M src/mainboard/google/rauru/Kconfig.name 2 files changed, 8 insertions(+), 3 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/24/84924/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/84924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Gerrit-Change-Number: 84924 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add is_battery_present()
by Sowmya Aralguppe (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Nick Vaccaro, Rishika Raj, Shelly Chang, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83735?usp=email ) Change subject: ec/google/chromeec: Add is_battery_present() ...................................................................... Patch Set 7: (1 comment) Patchset: PS7: I have reopened this patch as we need have an interface to check from EC if battery is physically present /connected -- To view, visit https://review.coreboot.org/c/coreboot/+/83735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie49ed8f6d8b0fa59ec0e7b06efea9cac4d253957 Gerrit-Change-Number: 83735 Gerrit-PatchSet: 7 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 08:00:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[S] Change in coreboot[main]: ec/google/chromeec: Add is_battery_present()
by Sowmya Aralguppe (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Caveh Jalali, Dinesh Gehlot, Eric Herrmann, Forest Mittelberg, Kapil Porwal, Karthik Ramasubramanian, Keith Short, Nick Vaccaro, Rishika Raj, Shelly Chang, Subrata Banik. Sowmya Aralguppe has posted comments on this change by Sowmya Aralguppe. ( https://review.coreboot.org/c/coreboot/+/83735?usp=email ) Change subject: ec/google/chromeec: Add is_battery_present() ...................................................................... Set Ready For Review -- To view, visit https://review.coreboot.org/c/coreboot/+/83735?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie49ed8f6d8b0fa59ec0e7b06efea9cac4d253957 Gerrit-Change-Number: 83735 Gerrit-PatchSet: 7 Gerrit-Owner: Sowmya Aralguppe <sowmya.aralguppe(a)intel.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Herrmann <eherrmann(a)google.com> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Keith Short <keithshort(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Rishika Raj <rishikaraj(a)google.com> Gerrit-Reviewer: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ashish Kumar Mishra <ashish.k.mishra(a)intel.com> Gerrit-CC: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-CC: Vinay Kumar <vinay.kumar(a)intel.com> Gerrit-Attention: Rishika Raj <rishikaraj(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Eric Herrmann <eherrmann(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Keith Short <keithshort(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Shelly Chang <Shelly_Chang(a)wiwynn.com> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 07:58:05 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/rauru: Add new board variant Hylia
by Yu-Ping Wu (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu, Yidi Lin. Yu-Ping Wu has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84924?usp=email ) Change subject: mb/google/rauru: Add new board variant Hylia ...................................................................... Patch Set 2: (1 comment) File src/mainboard/google/rauru/Kconfig.name: https://review.coreboot.org/c/coreboot/+/84924/comment/87737ef5_95c2d8f5?us… : PS2, Line 8: config BOARD_GOOGLE_HYLIA sort all the 3 boards -- To view, visit https://review.coreboot.org/c/coreboot/+/84924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Gerrit-Change-Number: 84924 Gerrit-PatchSet: 2 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yidi Lin <yidilin(a)google.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 07:39:30 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[M] Change in coreboot[main]: soc/intel/pantherlake: Populate and pass DRAM info for SMBIOS
by Subrata Banik (Code Review) 30 Oct '24

30 Oct '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84903?usp=email ) Change subject: soc/intel/pantherlake: Populate and pass DRAM info for SMBIOS ...................................................................... soc/intel/pantherlake: Populate and pass DRAM info for SMBIOS This patch implements the `save_dimm_info()` API to populate and pass DRAM-related information to the next stage. This information is used to generate the SMBIOS memory table, providing details about installed DIMMs. This addresses the issue where SMBIOS lacked detailed DIMM information. Verified that `dmidecode` correctly dumps the DIMM information from the SMBIOS table after this change. BUG=b:376103463 TEST=Built and booted successfully. Verified DIMM info in SMBIOS using `dmidecode`. > dmidecode -t 17 ``` Getting SMBIOS data from sysfs. SMBIOS 3.0 present. Handle 0x000B, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-0-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-0-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ... ... Handle 0x0012, DMI type 17, 40 bytes Memory Device Array Handle: 0x000A Error Information Handle: Not Provided Total Width: 16 bits Data Width: 16 bits Size: 2 GB Form Factor: Row Of Chips Set: None Locator: Channel-3-DIMM-0 Bank Locator: BANK 0 Type: LPDDR5 Type Detail: Unknown Synchronous Speed: 6400 MT/s Manufacturer: Hynix Serial Number: 00000000 Asset Tag: Channel-3-DIMM-0-AssetTag Part Number: H58G56BK7BX068 Rank: 1 Configured Memory Speed: 6400 MT/s Minimum Voltage: 0.5 V Maximum Voltage: 0.5 V Configured Voltage: 0.5 V ``` Change-Id: I3b942610272de401589ee0463de9cd0985974774 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84903 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Kapil Porwal <kapilporwal(a)google.com> --- M src/soc/intel/pantherlake/romstage/romstage.c 1 file changed, 98 insertions(+), 1 deletion(-) Approvals: Kapil Porwal: Looks good to me, approved Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/intel/pantherlake/romstage/romstage.c b/src/soc/intel/pantherlake/romstage/romstage.c index a05adc4..46be7b9 100644 --- a/src/soc/intel/pantherlake/romstage/romstage.c +++ b/src/soc/intel/pantherlake/romstage/romstage.c @@ -18,10 +18,107 @@ #include <string.h> #include <timestamp.h> +#define FSP_SMBIOS_MEMORY_INFO_GUID \ +{ \ + 0xd4, 0x71, 0x20, 0x9b, 0x54, 0xb0, 0x0c, 0x4e, \ + 0x8d, 0x09, 0x11, 0xcf, 0x8b, 0x9f, 0x03, 0x23 \ +} + /* Save the DIMM information for SMBIOS table 17 */ static void save_dimm_info(void) { - /* Update after FSP is released externally released. */ + int node, channel, dimm, dimm_max, index; + size_t hob_size; + const CONTROLLER_INFO *ctrlr_info; + const CHANNEL_INFO *channel_info; + const DIMM_INFO *src_dimm; + struct dimm_info *dest_dimm; + struct memory_info *mem_info; + const MEMORY_INFO_DATA_HOB *meminfo_hob; + const uint8_t smbios_memory_info_guid[sizeof(EFI_GUID)] = FSP_SMBIOS_MEMORY_INFO_GUID; + const uint8_t *serial_num; + const char *dram_part_num = NULL; + size_t dram_part_num_len = 0; + + /* Locate the memory info HOB, presence validated by raminit */ + meminfo_hob = fsp_find_extension_hob_by_guid( + smbios_memory_info_guid, + &hob_size); + if (!meminfo_hob || hob_size == 0) { + printk(BIOS_ERR, "SMBIOS MEMORY_INFO_DATA_HOB not found\n"); + return; + } + + /* + * Allocate CBMEM area for DIMM information used to populate SMBIOS + * table 17 + */ + mem_info = cbmem_add(CBMEM_ID_MEMINFO, sizeof(*mem_info)); + if (!mem_info) { + printk(BIOS_ERR, "CBMEM entry for DIMM info missing\n"); + return; + } + memset(mem_info, 0, sizeof(*mem_info)); + + /* Allow mainboard to override DRAM part number. */ + dram_part_num = mainboard_get_dram_part_num(); + if (dram_part_num) + dram_part_num_len = strlen(dram_part_num); + + /* Save available DIMM information */ + index = 0; + dimm_max = ARRAY_SIZE(mem_info->dimm); + for (node = 0; node < MAX_NODE; node++) { + ctrlr_info = &meminfo_hob->Controller[node]; + for (channel = 0; channel < MAX_CH && index < dimm_max; channel++) { + channel_info = &ctrlr_info->ChannelInfo[channel]; + if (channel_info->Status != CHANNEL_PRESENT) + continue; + + for (dimm = 0; dimm < MAX_DIMM && index < dimm_max; dimm++) { + src_dimm = &channel_info->DimmInfo[dimm]; + dest_dimm = &mem_info->dimm[index]; + if (src_dimm->Status != DIMM_PRESENT) + continue; + + /* If there is no DRAM part number overridden by + * mainboard then use original one. */ + if (!dram_part_num) { + dram_part_num_len = sizeof(src_dimm->ModulePartNum); + dram_part_num = (const char *) + &src_dimm->ModulePartNum[0]; + } + + uint8_t memProfNum = meminfo_hob->MemoryProfile; + serial_num = src_dimm->SpdSave + SPD_SAVE_OFFSET_SERIAL; + + /* Populate the DIMM information */ + dimm_info_fill(dest_dimm, + src_dimm->DimmCapacity, + meminfo_hob->MemoryType, + meminfo_hob->ConfiguredMemoryClockSpeed, + src_dimm->RankInDimm, + channel_info->ChannelId, + src_dimm->DimmId, + dram_part_num, + dram_part_num_len, + serial_num, + meminfo_hob->DataWidth, + meminfo_hob->VddVoltage[memProfNum], + meminfo_hob->EccSupport, + src_dimm->MfgId, + src_dimm->SpdModuleType, + node, + meminfo_hob->MaximumMemoryClockSpeed); + index++; + } + } + } + mem_info->dimm_cnt = index; + if (mem_info->dimm_cnt == 0) + printk(BIOS_ERR, "No DIMMs found\n"); + else + printk(BIOS_DEBUG, "%d DIMMs found\n", mem_info->dimm_cnt); } void mainboard_romstage_entry(void) -- To view, visit https://review.coreboot.org/c/coreboot/+/84903?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I3b942610272de401589ee0463de9cd0985974774 Gerrit-Change-Number: 84903 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Add ACPI names for missing devices
by Subrata Banik (Code Review) 30 Oct '24

30 Oct '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84910?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Add ACPI names for missing devices ...................................................................... soc/intel/pantherlake: Add ACPI names for missing devices This patch adds ACPI names for the following devices: - THC0 (PCI: 00:10.0) - THC1 (PCI: 00:10.1) - SRAM (PCI: 00:14.2) - FSPI (PCI: 00:1f.5) TEST=Able to build and boot google/fatcat without any error. w/o this patch: [ERROR] Missing ACPI Name for PCI: 00:10.0 [ERROR] Missing ACPI Name for PCI: 00:10.1 [ERROR] Missing ACPI Name for PCI: 00:14.2 [ERROR] Missing ACPI Name for PCI: 00:1f.5 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84910 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> --- M src/soc/intel/pantherlake/chip.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/soc/intel/pantherlake/chip.c b/src/soc/intel/pantherlake/chip.c index 2d9f67a..2202878 100644 --- a/src/soc/intel/pantherlake/chip.c +++ b/src/soc/intel/pantherlake/chip.c @@ -80,10 +80,13 @@ case PCI_DEVFN_TBT1: return "TRP1"; case PCI_DEVFN_TBT2: return "TRP2"; case PCI_DEVFN_TBT3: return "TRP3"; + case PCI_DEVFN_THC0: return "THC0"; + case PCI_DEVFN_THC1: return "THC1"; case PCI_DEVFN_NPU: return "NPU"; case PCI_DEVFN_IPU: return "IPU"; case PCI_DEVFN_ISH: return "ISHB"; case PCI_DEVFN_XHCI: return "XHCI"; + case PCI_DEVFN_SRAM: return "SRAM"; case PCI_DEVFN_I2C0: return "I2C0"; case PCI_DEVFN_I2C1: return "I2C1"; case PCI_DEVFN_I2C2: return "I2C2"; @@ -111,6 +114,7 @@ case PCI_DEVFN_GSPI1: return "SPI1"; /* Keeping ACPI device name coherent with ec.asl */ case PCI_DEVFN_ESPI: return "LPCB"; + case PCI_DEVFN_SPI: return "FSPI"; case PCI_DEVFN_HDA: return "HDAS"; case PCI_DEVFN_SMBUS: return "SBUS"; case PCI_DEVFN_GBE: return "GLAN"; -- To view, visit https://review.coreboot.org/c/coreboot/+/84910?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I474089607522a4bd13375cc34b8f8645ca3663d9 Gerrit-Change-Number: 84910 Gerrit-PatchSet: 4 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0
by Subrata Banik (Code Review) 30 Oct '24

30 Oct '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84909?usp=email ) ( 1 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0 ...................................................................... soc/intel/pantherlake: Set SMBUS device ACPI min sleep state as D0 This change sets the SMBUS device to min sleep state D0 in the ACPI sleep state table. TEST=Able to build and boot google/fatcat. w/o this patch: [WARN ] Unknown min d_state for PCI: 00:1f.4 w/ this patch: No Error or Warning. Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84909 Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/soc/intel/pantherlake/acpi.c 1 file changed, 1 insertion(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve Pranava Y N: Looks good to me, approved diff --git a/src/soc/intel/pantherlake/acpi.c b/src/soc/intel/pantherlake/acpi.c index fd17ef5..c49555b 100644 --- a/src/soc/intel/pantherlake/acpi.c +++ b/src/soc/intel/pantherlake/acpi.c @@ -225,6 +225,7 @@ { PCI_DEVFN_ESPI, ACPI_DEVICE_SLEEP_D0 }, { PCH_DEVFN_PMC, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_HDA, ACPI_DEVICE_SLEEP_D0 }, + { PCI_DEVFN_SMBUS, ACPI_DEVICE_SLEEP_D0 }, { PCI_DEVFN_SPI, ACPI_DEVICE_SLEEP_D3 }, { PCI_DEVFN_GBE, ACPI_DEVICE_SLEEP_D3 }, }; -- To view, visit https://review.coreboot.org/c/coreboot/+/84909?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If84d2ee8abfef34f6411e01e6c37d4e2008a3666 Gerrit-Change-Number: 84909 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Define EC_SYNC_IRQ and GPIO_PCH_WP for variants
by Subrata Banik (Code Review) 30 Oct '24

30 Oct '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84900?usp=email ) Change subject: mb/google/fatcat: Define EC_SYNC_IRQ and GPIO_PCH_WP for variants ...................................................................... mb/google/fatcat: Define EC_SYNC_IRQ and GPIO_PCH_WP for variants This commit defines the EC_SYNC_IRQ and GPIO_PCH_WP macros for different Fatcat variants. The EC_SYNC_IRQ macro is used for tight timestamps and wake support, while the GPIO_PCH_WP macro is used for the WP signal to the PCH. These macros were previously undefined or incorrectly defined for some variants. This commit fixes these issues and ensures that the macros are defined correctly for all variants. Specifically, this commit: - Defines EC_SYNC_IRQ and GPIO_PCH_WP for Fatcat Nuvo and Fatcat ITE. - Defines EC_SYNC_IRQ as 0 (not connected) for Fatcat. - Defines GPIO_PCH_WP as GPP_D02 for Fatcat. - Leaves EC_SYNC_IRQ and GPIO_PCH_WP as 0 (TODO) for Francka. TEST=Able to build and boot google/fatcat. w/o this patch: ``` cros_ec_lpcs GOOG0004:00: couldn't retrieve IRQ number (-22) cros_ec_lpcs GOOG0004:00: probe with driver cros_ec_lpcs failed with error -22 ``` w/ this patch: ``` cros_ec_lpcs GOOG0004:00: Chrome EC device registered ``` Change-Id: I9bd248496f08869c08cf6daafeed6584d0b166b7 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84900 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h M src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h 2 files changed, 18 insertions(+), 7 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h index b9b4689..c354e8b 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/ec.h @@ -75,8 +75,10 @@ /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE -#define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ -#define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ +#if !CONFIG(BOARD_GOOGLE_FATCAT) + #define EC_ENABLE_SYNC_IRQ /* Enable tight timestamp / wake support */ + #define EC_SYNC_IRQ_WAKE_CAPABLE /* Let the OS know ec_sync is wake capable */ +#endif #define SIO_EC_ENABLE_PS2K /* Enable PS/2 Keyboard */ #define SIO_EC_HOST_ENABLE /* EC Host Interface Resources */ diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h index 5a77e4e..3f94c03 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/include/baseboard/gpio.h @@ -6,12 +6,21 @@ #include <soc/gpe.h> #include <soc/gpio.h> -/* FIXME: update below code as per board schematics */ /* eSPI virtual wire reporting */ #define EC_SCI_GPI GPE0_ESPI -/* GPIO IRQ for tight timestamps / wake support */ -#define EC_SYNC_IRQ 0 -/* WP signal to PCH */ -#define GPIO_PCH_WP 0 +/* + * EC_SYNC_IRQ - GPIO IRQ for tight timestamps / wake support + * GPIO_PCH_WP - WP signal to PCH + */ +#if CONFIG(BOARD_GOOGLE_FATCATNUVO) || CONFIG(BOARD_GOOGLE_FATCATITE) + #define EC_SYNC_IRQ GPP_E07_IRQ + #define GPIO_PCH_WP GPP_D02 +#elif CONFIG(BOARD_GOOGLE_FATCAT) + #define EC_SYNC_IRQ 0 /* Not Connected */ + #define GPIO_PCH_WP GPP_D02 +#elif CONFIG(BOARD_GOOGLE_FRANCKA) + #define EC_SYNC_IRQ 0 /* TODO */ + #define GPIO_PCH_WP 0 /* TODO */ +#endif #endif /* __BASEBOARD_GPIO_H__ */ -- To view, visit https://review.coreboot.org/c/coreboot/+/84900?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9bd248496f08869c08cf6daafeed6584d0b166b7 Gerrit-Change-Number: 84900 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[S] Change in coreboot[main]: mb/google/fatcat: Ensure RW_SECTION_B at 16MB boundary for debug FMD
by Subrata Banik (Code Review) 30 Oct '24

30 Oct '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84899?usp=email ) Change subject: mb/google/fatcat: Ensure RW_SECTION_B at 16MB boundary for debug FMD ...................................................................... mb/google/fatcat: Ensure RW_SECTION_B at 16MB boundary for debug FMD This patch updates the flash map layout to guarantee that the RW_SECTION_B section starts at the 16MB boundary. Additionally, fix typo in flash descriptor comment, where comment incorrectly referred to "MTL" instead of "PTL". TEST=Successfully builds google/fatcat. Change-Id: Ia6dba611fba50f9694a75670d954a4630cde4d70 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84899 Reviewed-by: Pranava Y N <pranavayn(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/fatcat/chromeos-debug-fsp.fmd 1 file changed, 9 insertions(+), 9 deletions(-) Approvals: build bot (Jenkins): Verified Pranava Y N: Looks good to me, approved diff --git a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd index f34e495..8d41977 100644 --- a/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd +++ b/src/mainboard/google/fatcat/chromeos-debug-fsp.fmd @@ -9,6 +9,15 @@ FW_MAIN_A(CBFS) RW_FWID_A 64 } + # This section starts at the 16M boundary in SPI flash. + # PTL does not support a region crossing this boundary, + # because the SPI flash is memory-mapped into two non- + # contiguous windows. + RW_SECTION_B 7680K { + VBLOCK_B 8K + FW_MAIN_B(CBFS) + RW_FWID_B 64 + } RW_MISC 1M { UNIFIED_MRC_CACHE(PRESERVE) 128K { RECOVERY_MRC_CACHE 64K @@ -22,15 +31,6 @@ RW_VPD(PRESERVE) 8K RW_NVRAM(PRESERVE) 24K } - # This section starts at the 16M boundary in SPI flash. - # MTL does not support a region crossing this boundary, - # because the SPI flash is memory-mapped into two non- - # contiguous windows. - RW_SECTION_B 7680K { - VBLOCK_B 8K - FW_MAIN_B(CBFS) - RW_FWID_B 64 - } RW_LEGACY(CBFS) 1M RW_UNUSED 2M # Make WP_RO region align with SPI vendor -- To view, visit https://review.coreboot.org/c/coreboot/+/84899?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia6dba611fba50f9694a75670d954a4630cde4d70 Gerrit-Change-Number: 84899 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>

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[XS] Change in coreboot[main]: mb/google/fatcat: Adjust EC host command range for microchip EC
by Pranava Y N (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Paul Menzel, Subrata Banik. Pranava Y N has posted comments on this change by Subrata Banik. ( https://review.coreboot.org/c/coreboot/+/84919?usp=email ) Change subject: mb/google/fatcat: Adjust EC host command range for microchip EC ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84919?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951 Gerrit-Change-Number: 84919 Gerrit-PatchSet: 2 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Wed, 30 Oct 2024 07:16:54 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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