coreboot-gerrit October 2024

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[XS] Change in coreboot[main]: soc/intel/alderlake: Do lazy reset after disabling UFS
by Subrata Banik (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Karthik Ramasubramanian, Nick Vaccaro. Subrata Banik has posted comments on this change by Karthik Ramasubramanian. ( https://review.coreboot.org/c/coreboot/+/84935?usp=email ) Change subject: soc/intel/alderlake: Do lazy reset after disabling UFS ...................................................................... Patch Set 1: (1 comment) File src/soc/intel/alderlake/include/soc/romstage.h: https://review.coreboot.org/c/coreboot/+/84935/comment/5109dcd6_89cc96a1?us… : PS1, Line 23: mainboard_expects_another_reset Maybe a comment section would be helpful to understand when to override this function from the main board. I guess you are latching on below factors 1. During the cold boot cycle, don't need reset post disabling UFS because global reset will take care of it ? Therefore, you don't need to issue an immediate reset 2. During warm boot cycle, you don't need to issue resets because PMC FW won't be loaded further hence, if UFS has been disabled in last boot then PMC FW won't sample the new state ? -- To view, visit https://review.coreboot.org/c/coreboot/+/84935?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99 Gerrit-Change-Number: 84935 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 31 Oct 2024 03:53:21 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

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[XS] Change in coreboot[main]: mb/google/fatcat: Adjust EC host command range for microchip EC
by Subrata Banik (Code Review) 31 Oct '24

31 Oct '24

Subrata Banik has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84919?usp=email ) Change subject: mb/google/fatcat: Adjust EC host command range for microchip EC ...................................................................... mb/google/fatcat: Adjust EC host command range for microchip EC This commit adjusts the EC host command range for the Fatcat board to 0x800-0x807 & 0x200-0x20f. This change is necessary because the microchip EC used on the Fatcat board has a smaller host command range than the ITE/Nuvoton ECs used on other Fatcat variants. The `gen1_dec` register in the devicetree is updated to reflect this change. As per boot log, the `gen1_dec` aka offset 0x84, base address is 800 and size is 8 bytes. AP FW Boot log: [SPEW] PCI: 00:00:1f.0 resource base 800 size 8 align 0 gran 0 limit 0 flags c0000100 index 84 BUG=b:376207365 TEST=Able to build and boot google/fatcat w/o any error. without this patch: [SPEW ] LPC: Trying to open IO window from 800 size 8 [ERROR] LPC: Cannot open IO window: 800 size 8 [ERROR] No more IO windows with this patch: [SPEW ] LPC: Trying to open IO window from 800 size 8 Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951 Signed-off-by: Subrata Banik <subratabanik(a)google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/84919 Reviewed-by: Anil Kumar K <anil.kumar.k(a)intel.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Pranava Y N <pranavayn(a)google.com> Reviewed-by: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> --- M src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb 1 file changed, 5 insertions(+), 2 deletions(-) Approvals: Anil Kumar K: Looks good to me, but someone else must approve Vijay P Hiremath: Looks good to me, but someone else must approve Pranava Y N: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb index d794925..1b1fc73 100644 --- a/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb +++ b/src/mainboard/google/fatcat/variants/baseboard/fatcat/devicetree.cb @@ -4,8 +4,11 @@ register "pmc_gpe0_dw1" = "GPP_D" register "pmc_gpe0_dw2" = "GPP_E" - # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f - register "gen1_dec" = "0x00fc0801" + # For Fatcat (with microchip EC): + # EC host command ranges are in 0x800-0x807 & 0x200-0x20f + # For other Fatcat variants (with ITE/Nuvoton EC): + # EC host command ranges are in 0x800-0x8ff & 0x200-0x20f + register "gen1_dec" = "CONFIG(BOARD_GOOGLE_FATCAT) ? 0x00040801 : 0x00fc0801" register "gen2_dec" = "0x000c0201" # EC memory map range is 0x900-0x9ff register "gen3_dec" = "0x00fc0901" -- To view, visit https://review.coreboot.org/c/coreboot/+/84919?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifcee533341fa583d841a4b564f25831c6d04e951 Gerrit-Change-Number: 84919 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Anil Kumar K <anil.kumar.k(a)intel.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Pranava Y N <pranavayn(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bernardo Perez Priego <bernardo.perez.priego(a)intel.com>

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[M] Change in coreboot[main]: mb/google/nissa/var/teliks: Match VBT with SSFC
by Qinghong Zeng (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Dinesh Gehlot, Jayvik Desai, Kapil Porwal, Nick Vaccaro, Qinghong Zeng, Weimin Wu. Hello Dinesh Gehlot, Eric Lai, Jayvik Desai, Jianeng Ceng, Kapil Porwal, Nick Vaccaro, Paul Menzel, Subrata Banik, Weimin Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84871?usp=email to look at the new patch set (#16). Change subject: mb/google/nissa/var/teliks: Match VBT with SSFC ...................................................................... mb/google/nissa/var/teliks: Match VBT with SSFC We want to configure different VBT timings for panels of different sizes and distinguish them through SSFC. We select the reserved bit 6 of SSFC as the flag bit. When using a 12-inch panel, set this bit to 0; when using an 11-inch panel, set this bit to 1. Without splitting, the platform_BootPerf test will fail. BUG=b:374428465 TEST= 1. can match VBT with SSFC -When SSFC is set to 0x40: $ cat /sys/firmware/log | grep vbt Bit 6 of SSFC is 1, use vbt-teliks_panel_11_inch.bin CBFS: Found 'vbt-teliks_panel_11_inch.bin' @0x1c6140 size 0x50f in mcache @0x76adda14 -When SSFC is set to 0x0: $ cat /sys/firmware/log | grep vbt Bit 6 of SSFC is 0, use vbt-teliks.bin CBFS: Found 'vbt-teliks.bin' @0x1c5bc0 size 0x50e in mcache @0x76add9b0 2. can pass platform_BootPerf test The platform_BootPerf time measured for all SKUs is less than 1.55s. Change-Id: Ia8fb45aede5ead4826d983760506c366a70643ee Signed-off-by: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/brya/variants/teliks/variant.c 1 file changed, 58 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/71/84871/16 -- To view, visit https://review.coreboot.org/c/coreboot/+/84871?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia8fb45aede5ead4826d983760506c366a70643ee Gerrit-Change-Number: 84871 Gerrit-PatchSet: 16 Gerrit-Owner: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jayvik Desai <jayvik(a)google.com> Gerrit-Reviewer: Jianeng Ceng <cengjianeng(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Derek Huang <derekhuang(a)google.com> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-CC: Edward Dai <edwarddai(a)google.com> Gerrit-CC: Ricky Chang <rickytlchang(a)google.com> Gerrit-Attention: Jayvik Desai <jayvik(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Qinghong Zeng <zengqinghong(a)huaqin.corp-partner.google.com>

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Modify parameters of touchpad I2C
by Eric Lai (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Paul Menzel, hualin wei. Eric Lai has posted comments on this change by hualin wei. ( https://review.coreboot.org/c/coreboot/+/84898?usp=email ) Change subject: mb/google/dedede/var/awasuki: Modify parameters of touchpad I2C ...................................................................... Patch Set 6: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d Gerrit-Change-Number: 84898 Gerrit-PatchSet: 6 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 31 Oct 2024 02:52:52 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[XS] Change in coreboot[main]: mb/google/dedede/var/awasuki: Modify parameters of touchpad I2C
by hualin wei (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Eric Lai, Paul Menzel, hualin wei. Hello Eric Lai, Felix Held, Paul Menzel, Subrata Banik, Weimin Wu, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/84898?usp=email to look at the new patch set (#6). Change subject: mb/google/dedede/var/awasuki: Modify parameters of touchpad I2C ...................................................................... mb/google/dedede/var/awasuki: Modify parameters of touchpad I2C 1. Modify the I2C frequency of the touchpad between 380 Khz and 400 Khz to meet the spec. 2. Increase clk the time of high(TH) to greater than 600ns. Before: I2C0 - 420KHz TH - 557ns After: I2C0 - 398Khz TH - 630ns BUG=b:351968527 TEST=Check that the wave form meets the spec. Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d Signed-off-by: Wei Hualin <weihualin(a)huaqin.corp-partner.google.com> --- M src/mainboard/google/dedede/variants/awasuki/overridetree.cb 1 file changed, 6 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/98/84898/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/84898?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5ccaa3a669e18319311de14833966410c7adf40d Gerrit-Change-Number: 84898 Gerrit-PatchSet: 6 Gerrit-Owner: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: hualin wei <weihualin(a)huaqin.corp-partner.google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org>

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[S] Change in coreboot[main]: mb/google/rauru: Add new board variant Hylia
by Yidi Lin (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Hung-Te Lin, Xinxiong Xu, Yang Wu. Yidi Lin has posted comments on this change by Yang Wu. ( https://review.coreboot.org/c/coreboot/+/84924?usp=email ) Change subject: mb/google/rauru: Add new board variant Hylia ...................................................................... Patch Set 3: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84924?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I79c4525347fd7b1ecea6df05e1a6b726b78e946f Gerrit-Change-Number: 84924 Gerrit-PatchSet: 3 Gerrit-Owner: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Attention: Xinxiong Xu <xuxinxiong(a)huaqin.corp-partner.google.com> Gerrit-Attention: Yang Wu <wuyang5(a)huaqin.corp-partner.google.com> Gerrit-Comment-Date: Thu, 31 Oct 2024 02:11:26 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

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[M] Change in coreboot[main]: mb/google/brox: Hint romstage init about upcoming reset
by Karthik Ramasubramanian (Code Review) 31 Oct '24

31 Oct '24

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84937?usp=email ) Change subject: mb/google/brox: Hint romstage init about upcoming reset ...................................................................... mb/google/brox: Hint romstage init about upcoming reset Add support for the mainboard to check for any potential firmware component update and hence the assosicated reset. This indication can be used to avoid any redundant resets during the boot flow. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Ensure that the hints are provided correctly and any redundant resets are filtered out. Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk A src/mainboard/google/brox/variants/baseboard/brox/romstage.c M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h M src/mainboard/google/brox/variants/brox/Makefile.mk M src/mainboard/google/brox/variants/brox/variant.c M src/mainboard/google/brox/variants/jubilant/Makefile.mk M src/mainboard/google/brox/variants/jubilant/variant.c M src/mainboard/google/brox/variants/lotso/Makefile.mk M src/mainboard/google/brox/variants/lotso/variant.c 9 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/84937/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk b/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk index 3a66958..b3149ba 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk +++ b/src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += memory.c romstage-y += gpio.c +romstage-y += romstage.c romstage-$(CONFIG_MAINBOARD_USE_EARLY_LIBGFXINIT) += gma-mainboard.ads ramstage-y += gpio.c diff --git a/src/mainboard/google/brox/variants/baseboard/brox/romstage.c b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c new file mode 100644 index 0000000..f493f34 --- /dev/null +++ b/src/mainboard/google/brox/variants/baseboard/brox/romstage.c @@ -0,0 +1,58 @@ +#include <baseboard/variants.h> +#include <cbfs.h> +#include <ec/google/chromeec/ec.h> +#include <security/vboot/vboot_common.h> +#include <security/vboot/misc.h> +#include <soc/romstage.h> + +#define FWVER_SIZE 3 +#define FWVER_TO_INT(MAJOR, MINOR, PATCH) \ + (uint32_t)(((MAJOR) & 0xFF) << 16 | ((MINOR) & 0xFF) << 8 | ((PATCH) & 0xFF)) + +static bool check_auxfw_ver_mismatch(void) +{ + uint8_t *exp_fwver; + size_t exp_fwver_size; + unsigned int num_ports = 0; + struct ec_response_pd_chip_info pd_chip_r = {0}; + const char *fwver_fname = variant_get_auxfw_version_file(); + bool mismatch = false; + int ret; + + ret = google_chromeec_get_num_pd_ports(&num_ports); + if (ret < 0 || !num_ports) { + printk(BIOS_INFO, "%s: Cannot resolve # of USB PD ports\n", __func__); + return mismatch; + } + + ret = google_chromeec_get_pd_chip_infoi(0, 0, &pd_chip_r); + if (ret < 0) { + printk(BIOS_INFO, "%s: Cannot get PD port info\n", __func__); + return mismatch; + } + + /* find bundled fw hash */ + exp_fwver = cbfs_map(fwver_fname, &exp_fwver_size); + if (exp_fwver == NULL || exp_fwver_size != FWVER_SIZE) + return mismatch; + + if (pd_chip_r.fw_version_number != + FWVER_TO_INT(exp_fwver[0], exp_fwver[1], exp_fwver[2])) { + printk(BIOS_INFO, "%s: Expecting Aux FW update and hence a reset\n", __func__); + mismatch = true; + } + + return mismatch; +} + +bool mainboard_expects_another_reset(void) +{ + if (vboot_recovery_mode_enabled()) + return false; + + if (vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_EC_SOFTWARE_SYNC) && + vboot_is_gbb_flag_set(VB2_GBB_FLAG_DISABLE_AUXFW_SOFTWARE_SYNC)) + return false; + + return check_auxfw_ver_mismatch(); +} diff --git a/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h b/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h index a1fbe01..070b2f8 100644 --- a/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h +++ b/src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h @@ -60,4 +60,5 @@ void variant_init(void); void variant_finalize(void); +const char *variant_get_auxfw_version_file(void); #endif /*__BASEBOARD_VARIANTS_H__ */ diff --git a/src/mainboard/google/brox/variants/brox/Makefile.mk b/src/mainboard/google/brox/variants/brox/Makefile.mk index 4a7ff71..19eb924 100644 --- a/src/mainboard/google/brox/variants/brox/Makefile.mk +++ b/src/mainboard/google/brox/variants/brox/Makefile.mk @@ -2,6 +2,7 @@ bootblock-y += gpio.c romstage-y += gpio.c +romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += gpio.c diff --git a/src/mainboard/google/brox/variants/brox/variant.c b/src/mainboard/google/brox/variants/brox/variant.c index 332d152..7ef4973 100644 --- a/src/mainboard/google/brox/variants/brox/variant.c +++ b/src/mainboard/google/brox/variants/brox/variant.c @@ -25,3 +25,12 @@ { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); } + +const char *variant_get_auxfw_version_file(void) +{ + if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_BYPASS))) + return "rts5453_retimer_bypass.hash"; + else if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_JHL8040))) + return "rts5453_retimer_jhl8040.hash"; + return NULL; +} diff --git a/src/mainboard/google/brox/variants/jubilant/Makefile.mk b/src/mainboard/google/brox/variants/jubilant/Makefile.mk index 503ef8f..bb7543b 100644 --- a/src/mainboard/google/brox/variants/jubilant/Makefile.mk +++ b/src/mainboard/google/brox/variants/jubilant/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += gpio.c romstage-y += memory.c +romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += fw_config.c ramstage-$(CONFIG_FW_CONFIG) += variant.c diff --git a/src/mainboard/google/brox/variants/jubilant/variant.c b/src/mainboard/google/brox/variants/jubilant/variant.c index 5b75380..26140cd 100644 --- a/src/mainboard/google/brox/variants/jubilant/variant.c +++ b/src/mainboard/google/brox/variants/jubilant/variant.c @@ -31,6 +31,15 @@ return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); } +const char *variant_get_auxfw_version_file(void) +{ + if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_BYPASS))) + return "rts5453_retimer_bypass.hash"; + else if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_JHL8040))) + return "rts5453_retimer_jhl8040.hash"; + return NULL; +} + static void wwan_out_of_reset(void *unused) { if (fw_config_probe(FW_CONFIG(DB_USB, DB_1A_LTE))) { diff --git a/src/mainboard/google/brox/variants/lotso/Makefile.mk b/src/mainboard/google/brox/variants/lotso/Makefile.mk index a1059a5..dde5215 100644 --- a/src/mainboard/google/brox/variants/lotso/Makefile.mk +++ b/src/mainboard/google/brox/variants/lotso/Makefile.mk @@ -4,6 +4,7 @@ romstage-y += memory.c romstage-y += gpio.c ramstage-y += gpio.c +romstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-$(CONFIG_FW_CONFIG) += variant.c ramstage-y += ramstage.c smm-y += smihandler.c diff --git a/src/mainboard/google/brox/variants/lotso/variant.c b/src/mainboard/google/brox/variants/lotso/variant.c index 066acb2..baf8ee4 100644 --- a/src/mainboard/google/brox/variants/lotso/variant.c +++ b/src/mainboard/google/brox/variants/lotso/variant.c @@ -19,3 +19,12 @@ { return get_wifi_sar_fw_config_filename(FW_CONFIG_FIELD(WIFI_BT)); } + +const char *variant_get_auxfw_version_file(void) +{ + if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_BYPASS))) + return "rts5453_retimer_bypass.hash"; + else if (fw_config_probe(FW_CONFIG(RETIMER, RETIMER_JHL8040))) + return "rts5453_retimer_jhl8040.hash"; + return NULL; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/84937?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1 Gerrit-Change-Number: 84937 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>

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[S] Change in coreboot[main]: ec/google/chromeec: Add API to get PD Chip info
by Karthik Ramasubramanian (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Caveh Jalali, Forest Mittelberg. Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84936?usp=email ) Change subject: ec/google/chromeec: Add API to get PD Chip info ...................................................................... ec/google/chromeec: Add API to get PD Chip info Add API to get Power Delivery (PD) Chip info which includes vendor ID, product ID and firmware version(if any). BUG=None TEST=Build Brox BIOS image and boot to OS. Change-Id: I4cc4493ac64d44076877fee633488c95cd09807e Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/ec/google/chromeec/ec.c M src/ec/google/chromeec/ec.h 2 files changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/84936/1 diff --git a/src/ec/google/chromeec/ec.c b/src/ec/google/chromeec/ec.c index 088f2fe..b47750e 100644 --- a/src/ec/google/chromeec/ec.c +++ b/src/ec/google/chromeec/ec.c @@ -1170,6 +1170,17 @@ return 0; } +int google_chromeec_get_pd_chip_infoi(int port, int renew, + struct ec_response_pd_chip_info *r) +{ + const struct ec_params_pd_chip_info p = { + .port = port, + .live = renew, + }; + + return ec_cmd_pd_chip_info(PLAT_EC, &p, r); +} + int google_chromeec_get_pd_port_caps(int port, struct usb_pd_port_caps *port_caps) { diff --git a/src/ec/google/chromeec/ec.h b/src/ec/google/chromeec/ec.h index 0062df6..929e392 100644 --- a/src/ec/google/chromeec/ec.h +++ b/src/ec/google/chromeec/ec.h @@ -337,6 +337,18 @@ */ int google_chromeec_get_num_pd_ports(unsigned int *num_ports); +/** + * Return a port's PD chip information. + * + * @param port The desired port number + * @param renew Refresh cached value + * @param r Result buffer for chip info + * + * @return 0 if ok, -1 on error + */ +int google_chromeec_get_pd_chip_infoi(int port, int renew, + struct ec_response_pd_chip_info *r); + /* Structure representing the capabilities of a USB-PD port */ struct usb_pd_port_caps { enum ec_pd_power_role_caps power_role_cap; -- To view, visit https://review.coreboot.org/c/coreboot/+/84936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4cc4493ac64d44076877fee633488c95cd09807e Gerrit-Change-Number: 84936 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Caveh Jalali <caveh(a)chromium.org> Gerrit-Reviewer: Forest Mittelberg <bmbm(a)google.com> Gerrit-Attention: Caveh Jalali <caveh(a)chromium.org> Gerrit-Attention: Forest Mittelberg <bmbm(a)google.com>

1 0

[XS] Change in coreboot[main]: soc/intel/alderlake: Do lazy reset after disabling UFS
by Karthik Ramasubramanian (Code Review) 31 Oct '24

31 Oct '24

Karthik Ramasubramanian has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/84935?usp=email ) Change subject: soc/intel/alderlake: Do lazy reset after disabling UFS ...................................................................... soc/intel/alderlake: Do lazy reset after disabling UFS If the mainboard expects upcoming reset, then skip the reset after disabling UFS. This will reduce the number of resets during firmware update. BUG=b:375444631 TEST=Build Brox BIOS image and boot to OS. Perform a firmware update and confirm that the number of reset is reduced. Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99 Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com> --- M src/soc/intel/alderlake/include/soc/romstage.h M src/soc/intel/alderlake/romstage/romstage.c 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/35/84935/1 diff --git a/src/soc/intel/alderlake/include/soc/romstage.h b/src/soc/intel/alderlake/include/soc/romstage.h index 679d538..49c3032 100644 --- a/src/soc/intel/alderlake/include/soc/romstage.h +++ b/src/soc/intel/alderlake/include/soc/romstage.h @@ -20,4 +20,5 @@ BOARD_TYPE_SERVER = 8 }; +bool mainboard_expects_another_reset(void); #endif /* _SOC_ROMSTAGE_H_ */ diff --git a/src/soc/intel/alderlake/romstage/romstage.c b/src/soc/intel/alderlake/romstage/romstage.c index ff600db..2f50cd2 100644 --- a/src/soc/intel/alderlake/romstage/romstage.c +++ b/src/soc/intel/alderlake/romstage/romstage.c @@ -32,6 +32,11 @@ #define PCR_PSFX_T0_SHDW_PCIEN 0x1C #define PCR_PSFX_T0_SHDW_PCIEN_FUNDIS (1 << 8) +bool __weak mainboard_expects_another_reset(void) +{ + return false; +} + static void disable_ufs(void) { /* disable USF0 */ @@ -185,7 +190,7 @@ (CONFIG(USE_UNIFIED_AP_FIRMWARE_FOR_UFS_AND_NON_UFS))) { printk(BIOS_INFO, "Disabling UFS controllers\n"); disable_ufs(); - if (ps->prev_sleep_state == ACPI_S5) { + if (ps->prev_sleep_state == ACPI_S5 && !mainboard_expects_another_reset()) { printk(BIOS_INFO, "Warm Reset after disabling UFS controllers\n"); system_reset(); } -- To view, visit https://review.coreboot.org/c/coreboot/+/84935?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newchange Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4399555302ec23a76f89f406f437f311eea0ef99 Gerrit-Change-Number: 84935 Gerrit-PatchSet: 1 Gerrit-Owner: Karthik Ramasubramanian <kramasub(a)google.com>

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[M] Change in coreboot[main]: util/amdfwtool: Add binaries
by Felix Held (Code Review) 30 Oct '24

30 Oct '24

Attention is currently required from: Anand Vaikar, Bao Zheng, Maximilian Brune. Felix Held has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84373?usp=email ) Change subject: util/amdfwtool: Add binaries ...................................................................... Patch Set 5: (1 comment) File util/amdfwtool/data_parse.c: https://review.coreboot.org/c/coreboot/+/84373/comment/517b99ae_d3aaebeb?us… : PS4, Line 649: fw_type = AMD_BIOS_NV_ST; > I can only say that it is a fairly big file (~300K), I don't know its actual contents. oh, i've mixed up PSP_BDT_BIOS_NV_ST with AMD_FW_PSP_NVRAM and AMD_RPMC_NVRAM. checked the corresponding doc #55758 and it's not what i initially though it is. currently it might not be required, but again, not really sure about that one -- To view, visit https://review.coreboot.org/c/coreboot/+/84373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78d7a9dba71de557e0a9a885d8561eea1f4191ef Gerrit-Change-Number: 84373 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Comment-Date: Wed, 30 Oct 2024 22:46:04 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

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