coreboot-gerrit October 2024

coreboot-gerrit@coreboot.org

1 participants
2622 discussions

[S] Change in coreboot[main]: soc/amd/common/psp_smi_flash: factor out get_flash_device
by Matt DeVillier (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk. Matt DeVillier has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84905?usp=email ) Change subject: soc/amd/common/psp_smi_flash: factor out get_flash_device ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/84905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia99d3454df2c1c4182c193da7de1bbb4eef18313 Gerrit-Change-Number: 84905 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 31 Oct 2024 15:27:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/amd/glinda: Adding SPI controller to ACPI
by Paul Menzel (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Ana Carolina Cabral. Paul Menzel has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84643?usp=email ) Change subject: soc/amd/glinda: Adding SPI controller to ACPI ...................................................................... Patch Set 3: Code-Review+1 (2 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/84643/comment/b459dcea_83f177ee?us… : PS3, Line 7: Adding Imperative mood: Add https://review.coreboot.org/c/coreboot/+/84643/comment/87464307_f67889ff?us… : PS3, Line 10: How did you verify your change? Please add a TEST= line. -- To view, visit https://review.coreboot.org/c/coreboot/+/84643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d9a2b54602ef963f4753a4b62211969151a9412 Gerrit-Change-Number: 84643 Gerrit-PatchSet: 3 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Ana Carolina Cabral Gerrit-Comment-Date: Thu, 31 Oct 2024 14:25:24 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: soc/amd/glinda: Adding SPI controller to ACPI
by Ana Carolina Cabral (Code Review) 31 Oct '24

31 Oct '24

Ana Carolina Cabral has posted comments on this change by Ana Carolina Cabral. ( https://review.coreboot.org/c/coreboot/+/84643?usp=email ) Change subject: soc/amd/glinda: Adding SPI controller to ACPI ...................................................................... Patch Set 3: (7 comments) This change is ready for review. Commit Message: https://review.coreboot.org/c/coreboot/+/84643/comment/968baf1a_438d109d?us… : PS2, Line 7: soc/amd/glinda: SPI DEV entries missing in coreboot and UEFI BIOS > Please make the statement about the action of the change and not an issue description. Done https://review.coreboot.org/c/coreboot/+/84643/comment/af718a88_4b43aa11?us… : PS2, Line 8: > Please describe the problem, and then the fix. Done File src/soc/amd/glinda/acpi/soc.asl: https://review.coreboot.org/c/coreboot/+/84643/comment/5f98285d_9dedafc7?us… : PS2, Line 22: #include "spi.asl" > since the spi controller is an mmio device, i'd probably include the corresponding file from the soc […] Done File src/soc/amd/glinda/acpi/spi.asl: PS2: > only had a very brief look, but this should probably end up in the common amd soc code Done https://review.coreboot.org/c/coreboot/+/84643/comment/b321240e_68f38bf3?us… : PS2, Line 19: 0xFEC10000 > this is SPI_BASE_ADDRESS from soc/iomap. […] Done https://review.coreboot.org/c/coreboot/+/84643/comment/9204ade2_d2a6bfc5?us… : PS2, Line 23: 0x22 > SPI100_SPEED_CONFIG; would probably require some preprocessor magic to only include the parts of the […] Done https://review.coreboot.org/c/coreboot/+/84643/comment/1385ce21_4cebcc15?us… : PS2, Line 25: 0xFC > SPI_MISC_CNTRL; would probably require some preprocessor magic to only include the parts of the head […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/84643?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2d9a2b54602ef963f4753a4b62211969151a9412 Gerrit-Change-Number: 84643 Gerrit-PatchSet: 3 Gerrit-Owner: Ana Carolina Cabral Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Comment-Date: Thu, 31 Oct 2024 14:09:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de>

1 0

[S] Change in coreboot[main]: soc/amd/common/psp_smi_flash: factor out get_flash_device
by Ana Carolina Cabral (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Felix Held, Fred Reitberger, Jason Glenesk, Matt DeVillier. Ana Carolina Cabral has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84905?usp=email ) Change subject: soc/amd/common/psp_smi_flash: factor out get_flash_device ...................................................................... Patch Set 1: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84905?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ia99d3454df2c1c4182c193da7de1bbb4eef18313 Gerrit-Change-Number: 84905 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 31 Oct 2024 13:58:22 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[XS] Change in coreboot[main]: drivers/spi/spi_flash: make 'do_spi_flash_cmd' available to other files
by Ana Carolina Cabral (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Felix Held. Ana Carolina Cabral has posted comments on this change by Felix Held. ( https://review.coreboot.org/c/coreboot/+/84789?usp=email ) Change subject: drivers/spi/spi_flash: make 'do_spi_flash_cmd' available to other files ...................................................................... Patch Set 4: Code-Review+1 -- To view, visit https://review.coreboot.org/c/coreboot/+/84789?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I1f3872463249240c0a32e2825e4302894e856b2e Gerrit-Change-Number: 84789 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Ana Carolina Cabral Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 31 Oct 2024 13:56:41 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes

1 0

[M] Change in coreboot[main]: util/amdfwtool: Add binaries
by Ana Carolina Cabral (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Anand Vaikar, Bao Zheng, Maximilian Brune. Ana Carolina Cabral has posted comments on this change by Maximilian Brune. ( https://review.coreboot.org/c/coreboot/+/84373?usp=email ) Change subject: util/amdfwtool: Add binaries ...................................................................... Patch Set 5: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/84373/comment/eba22a73_4ef115fe?us… : PS5, Line 7: util/amdfwtool: Add binaries Please detail -- To view, visit https://review.coreboot.org/c/coreboot/+/84373?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I78d7a9dba71de557e0a9a885d8561eea1f4191ef Gerrit-Change-Number: 84373 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Ana Carolina Cabral Gerrit-Attention: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Comment-Date: Thu, 31 Oct 2024 13:53:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No

1 0

[XS] Change in coreboot[main]: mb/google/rauru: Pre-initialize PCIe at the bootblock stage
by Yu-Ping Wu (Code Review) 31 Oct '24

31 Oct '24

Yu-Ping Wu has submitted this change. ( https://review.coreboot.org/c/coreboot/+/84699?usp=email ) Change subject: mb/google/rauru: Pre-initialize PCIe at the bootblock stage ...................................................................... mb/google/rauru: Pre-initialize PCIe at the bootblock stage According to the PCIe CEM specification, the deassertion of PERST# should occur at least 100ms after the assertion. Right now we simply wait for 100ms in ramstage for that. To speed up the boot time, pre-initialize PCIe by asserting PERST# earlier in the bootblock stage. The pre-initialization time is stored in the early init data region, so that the PCIe initialization in ramstage could make sure the required 100ms delay is still reached. This pre-initialization will speed up the boot time by 100ms on rauru. TEST=Build pass, show pcie init pass log: mtk_pcie_domain_enable: PCIe link up success (1) BUG=b:317009620 Signed-off-by: Jianjun Wang <jianjun.wang(a)mediatek.com> Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484 Reviewed-on: https://review.coreboot.org/c/coreboot/+/84699 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yidi Lin <yidilin(a)google.com> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/rauru/bootblock.c 1 file changed, 4 insertions(+), 0 deletions(-) Approvals: build bot (Jenkins): Verified Yidi Lin: Looks good to me, approved Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/rauru/bootblock.c b/src/mainboard/google/rauru/bootblock.c index b1f9863..e0717aa 100644 --- a/src/mainboard/google/rauru/bootblock.c +++ b/src/mainboard/google/rauru/bootblock.c @@ -2,6 +2,7 @@ #include <bootblock_common.h> #include <gpio.h> +#include <soc/pcie.h> #include <soc/spi.h> #include "gpio.h" @@ -13,6 +14,9 @@ void bootblock_mainboard_init(void) { + if (CONFIG(PCI)) + mtk_pcie_pre_init(); + mtk_snfc_init(); usb3_hub_reset(); setup_chromeos_gpios(); -- To view, visit https://review.coreboot.org/c/coreboot/+/84699?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: merged Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2b84c25ae3ea9069fd38fa6b20b8235a7fc3a484 Gerrit-Change-Number: 84699 Gerrit-PatchSet: 13 Gerrit-Owner: Jarried Lin <jarried.lin(a)mediatek.com> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Kiwi Liu <kiwi.liu(a)mediatek.corp-partner.google.com> Gerrit-Reviewer: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Jianjun Wang <jianjun.wang(a)mediatek.com>

1 0

[XS] Change in coreboot[main]: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
by Keith Hui (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Fabian Groffen, Keith Hui, Paul Menzel. Keith Hui has posted comments on this change by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM ...................................................................... Patch Set 8: (2 comments) Patchset: PS8: I have edited the commit message right on gerrit (so there's no new code being pushed). Hopefully this clears things up while keeping all key info intact. Thanks all. Commit Message: https://review.coreboot.org/c/coreboot/+/75137/comment/ec60035c_d3bdc1eb?us… : PS6, Line 7: Remove settings to replicate OEM > Remove 3 global settings to fix serial port 1 Done -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: comment Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 8 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Comment-Date: Thu, 31 Oct 2024 13:26:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org>

1 0

[XS] Change in coreboot[main]: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM
by Keith Hui (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Fabian Groffen, Keith Hui, Keith Hui, Paul Menzel. Keith Hui has uploaded a new patch set (#8) to the change originally created by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM ...................................................................... mb/asus/p8z77-m: Revert SIO IRQ settings carried from OEM Revert super I/O IRQ polarity settings replicated from OEM firmware back to its power-on defaults. With OEM settings COM 1/UART A/serial port 1 gets blocked right after the kernel boots. It no longer works or responds, which actually means the Linux boot process gets stuck forever when configured to write to ttyS0. Also revised the comment on another SIO setting to say it's being set for PECI. TEST=Not using these settings, I have not found any downside. Serial keeps working, sensors still work, S3 suspend/resume works correctly. Reported-by: Fabian Confirmed-by: Keith Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> Signed-off-by: Keith Hui <buurin(a)gmail.com> Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/75137/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 8 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Fabian Groffen <grobian(a)gentoo.org>

1 0

[XS] Change in coreboot[main]: mb/asus/p8z77-m: Remove settings to replicate OEM
by Keith Hui (Code Review) 31 Oct '24

31 Oct '24

Attention is currently required from: Keith Hui, Keith Hui, Paul Menzel. Keith Hui has uploaded a new patch set (#7) to the change originally created by Fabian Groffen. ( https://review.coreboot.org/c/coreboot/+/75137?usp=email ) Change subject: mb/asus/p8z77-m: Remove settings to replicate OEM ...................................................................... mb/asus/p8z77-m: Remove settings to replicate OEM Revert super I/O IRQ polarity settings replicated from OEM firmware back to its power-on defaults. With OEM settings COM 1/UART A/serial port 1 gets blocked right after the kernel boots. It no longer works or responds, which actually means the Linux boot process gets stuck forever when configured to write to ttyS0. Also revised the comment on another SIO setting to say it's being set for PECI. TEST=Not using these settings, I have not found any downside. Serial keeps working, sensors still work, S3 suspend/resume works correctly. Reported-by: Fabian Confirmed-by: Keith Signed-off-by: Fabian Groffen <grobian(a)gentoo.org> Signed-off-by: Keith Hui <buurin(a)gmail.com> Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c --- M src/mainboard/asus/p8x7x-series/variants/p8z77-m/overridetree.cb 1 file changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/75137/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/75137?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings?usp=email Gerrit-MessageType: newpatchset Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iae526762e79e9e2d46d06e12c338f375e5555e8c Gerrit-Change-Number: 75137 Gerrit-PatchSet: 7 Gerrit-Owner: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Fabian Groffen <grobian(a)gentoo.org> Gerrit-Reviewer: Keith Hui <buurin(a)gmail.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: coreboot org <coreboot.org(a)gmail.com> Gerrit-Attention: Keith Hui <buurin(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Keith Hui <buurin(a)gmail.com>

1 0

← Newer
1
2
3
4
5
6
7
...
263
Older →

Jump to page:

2024

2023

2022

2021

2020

2019

2018

2017

2016

2015

2014

2013

coreboot-gerrit October 2024