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Change subject: payloads/Kconfig: Disable compression for UPL FIT
......................................................................
Patch Set 1: Code-Review+1
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Change subject: lib/fit_payload.c: Support loading UPL FITs
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Patch Set 2: Code-Review+1
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Change subject: payloads/libpayload: Implement support for UPL handoff
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Patch Set 2: Code-Review+1
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Change subject: Add UPL FDT handoff
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Patch Set 24: Code-Review+1
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Change subject: soc/intel/common/gpio: add function to lock GPIO configuration
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Patch Set 3:
(1 comment)
File src/soc/intel/common/block/gpio/gpio.c:
https://review.coreboot.org/c/coreboot/+/84901/comment/6e85fa9b_10e25677?us… :
PS3, Line 485: /* Clear lock for the exception PADs */
> > The thing is that we don't enable lock in our MB gpio.c and fw_config. […]
Hi Subrata, This is a TODO to a TODO. This GPIO locking proposal was Cliff's solution to task#9 in 357011633#comment16. For JTAG in particular you need to go the route of disabling in mfit - see 302226565.
However, having common code to lock all GPIO configs in Coreboot seems to be a solution that people can use if needed, especially for security reasons.
Maybe this locking can be turned off for debug builds because it will prevent someone who wants to tune a config value.
The reason for adding exception list for locking is because we have seen one case where config was changed from asl before sleep and switched back on wake.
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
https://review.coreboot.org/c/coreboot/+/84937?usp=email
to look at the new patch set (#4).
Change subject: mb/google/brox: Hint romstage init about upcoming reset
......................................................................
mb/google/brox: Hint romstage init about upcoming reset
Add support for the mainboard to check for any potential firmware
component update and hence the assosicated reset. This indication can be
used to avoid any redundant resets during the boot flow.
BUG=b:375444631
TEST=Build Brox BIOS image and boot to OS. Ensure that the hints are
provided correctly and 2 redundant resets are filtered out.
Change-Id: Ieed3f9013dee9aa501a3f0403f3a28722a3878f1
Signed-off-by: Karthikeyan Ramasubramanian <kramasub(a)google.com>
---
M src/mainboard/google/brox/variants/baseboard/brox/Makefile.mk
A src/mainboard/google/brox/variants/baseboard/brox/romstage.c
M src/mainboard/google/brox/variants/baseboard/include/baseboard/variants.h
M src/mainboard/google/brox/variants/brox/Makefile.mk
M src/mainboard/google/brox/variants/brox/variant.c
M src/mainboard/google/brox/variants/jubilant/Makefile.mk
M src/mainboard/google/brox/variants/jubilant/variant.c
M src/mainboard/google/brox/variants/lotso/Makefile.mk
M src/mainboard/google/brox/variants/lotso/variant.c
9 files changed, 89 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/84937/4
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Change subject: lib/fit.c: Add support for UPL style FITs
......................................................................
Patch Set 1: Code-Review+1
(2 comments)
File src/lib/fit.c:
https://review.coreboot.org/c/coreboot/+/84796/comment/4fe2a416_26212ca6?us… :
PS1, Line 397: "No FDT for supporting \"compat\" feature!\n");
maybe reword this to more closely match the comment above?
"FDT 'compatible' property not found in config; extracting from FDT itself"
https://review.coreboot.org/c/coreboot/+/84796/comment/1096ba54_d932a45a?us… :
PS1, Line 489: printk(BIOS_WARNING, "config %s has no FDT!\n",
curious why you downgraded this msg from ERR to WARN
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Change subject: mb/google/brox: Hint romstage init about upcoming reset
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84937/comment/b41b6207_4f2d90ac?us… :
PS2, Line 9: firmware
: component update
> Which firmware exactly?
In Brox mainboard - Embedded Controller (EC), Power Delivery Controller (PDC) have updateable firmware.
https://review.coreboot.org/c/coreboot/+/84937/comment/6366afe0_42c65a47?us… :
PS2, Line 14: Build Brox BIOS image and boot to OS. Ensure that the hints are
: provided correctly and any redundant resets are filtered out.
> Excuse my ignorance, but it’d be great if you gave an example for the behavior and number of resets […]
Done
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Change subject: soc/intel/alderlake: Do lazy reset after disabling UFS
......................................................................
Patch Set 3:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/84935/comment/94dd9474_9145bbeb?us… :
PS2, Line 10: This will reduce the number of resets during firmware
: update.
:
> Reduce by one reset?
Done. Added it in the TEST message. 2 resets got suppressed.
https://review.coreboot.org/c/coreboot/+/84935/comment/c4e47641_4ad08e1f?us… :
PS2, Line 15: reset is reduced
> It’d be great if you added explicit numbers.
Done
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