Tony Huang has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80153?usp=email )
Change subject: mb/google/rex/variants/deku: update USB-C port configuration
......................................................................
mb/google/rex/variants/deku: update USB-C port configuration
This CL update setting according to schematic v0.4.
BUG=b:320201111
BRANCH=firmware-rex-15709.B
TEST=Built FW image correctly.
Change-Id: I2c1e1cbd71d451d5c909561e8bcb09f954fecad9
Signed-off-by: Tony Huang <tony-huang(a)quanta.corp-partner.google.com>
---
M src/mainboard/google/rex/variants/deku/overridetree.cb
1 file changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/53/80153/1
diff --git a/src/mainboard/google/rex/variants/deku/overridetree.cb b/src/mainboard/google/rex/variants/deku/overridetree.cb
index 9c35338..711d3b6 100644
--- a/src/mainboard/google/rex/variants/deku/overridetree.cb
+++ b/src/mainboard/google/rex/variants/deku/overridetree.cb
@@ -117,21 +117,21 @@
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, RIGHT, ACPI_PLD_GROUP(2, 1))"
- device ref tcss_usb3_port1 on end
+ device ref tcss_usb3_port2 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C2""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(BACK, CENTER, ACPI_PLD_GROUP(3, 1))"
- device ref tcss_usb3_port2 on end
+ device ref tcss_usb3_port1 on end
end
chip drivers/usb/acpi
register "desc" = ""USB3 Type-C Port C3""
register "type" = "UPC_TYPE_C_USB2_SS_SWITCH"
register "use_custom_pld" = "true"
register "custom_pld" = "ACPI_PLD_TYPE_C(FRONT, LEFT, ACPI_PLD_GROUP(4, 1))"
- device ref tcss_usb3_port2 on end
+ device ref tcss_usb3_port3 on end
end
end
end
@@ -156,7 +156,7 @@
end
chip drivers/intel/usb4/retimer
register "dfp[1].power_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B22)"
- use tcss_usb3_port3 as dfp[0].typec_port
+ use tcss_usb3_port3 as dfp[1].typec_port
device generic 0 on end
end
end
@@ -298,7 +298,7 @@
chip drivers/intel/pmc_mux/conn
#USB2_C3
use usb2_port5 as usb2_port
- use tcss_usb3_port1 as usb3_port
+ use tcss_usb3_port3 as usb3_port
device generic 3 alias conn3 on end
end
end
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Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Patch Set 6:
(4 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80170/comment/8f29c4d7_ec63253f :
PS5, Line 17:
> Why is this ChromeOS specific, that means, you change things under `vendorcode/`?
The functionality is being added specifically for Chromebooks and ChromeOS. It is similar in many ways to the functionality in sar.c and wrdd.c in the same directory.
https://review.coreboot.org/c/coreboot/+/80170/comment/f7697be1_f90825a1 :
PS5, Line 27:
> Where is the format of the file defined?
I did define the format in the comment for get_wifi_mtcl in mtcl.c starting on line 9, but it is a little hand-wavy. I'd accept suggestions to make it better.
Patchset:
PS5:
> Welcome to coreboot! […]
Thanks!
You'll need at least https://lore.kernel.org/all/20240116024857.9071-3-mingyen.hsieh@mediatek.co… and https://lore.kernel.org/all/20240111061856.16370-1-mingyen.hsieh@mediatek.c… on top of upstream. There were quite a few patches recently that helped implement this functionality, and I'm not sure that all of them are quite upstream yet, unfortunately.
File src/drivers/wifi/generic/Kconfig:
https://review.coreboot.org/c/coreboot/+/80170/comment/c3e20e53_61c65afd :
PS5, Line 69: When enabled, adds the MTCL function for MediaTek
: WiFi chipsets. This function supplies country list information
: used to enable or disable operation on 5.9GHz and 6GHz
: bands.
> Please reflow. Then it should fit in three lines? […]
Done.
The file is just a binary file that has data in the format specified in get_wifi_mtcl. I generated test files with a small c program that just writes bytes to disk, but any way you know how to get bytes in a file with do.
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Hello Cliff Huang, Lance Zhao, Subrata Banik, Tim Wawrzynczak, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Verified+1 by build bot (Jenkins)
Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Add MTCL function to ACPI SSDT tables
The MTCL function provides a country list to the Linux kernel via an
ACPI function in SSDT tables for MediaTek chipsets that are capable of
operating on the 6GHz band. The country list is used to selectively
disable 6GHz and 5.9GHz operation based on the country the device is
operating in.
The function needs to read a binary file and send it as a package via
the MTCL method in SSDT for PCIe WiFi chips for MediaTek chipsets.
BUG=b:295544553
TEST=Add Kconfig entry USE_MTCL for pujjo
TEST=Add wifi_mtcl_defaults.hex blob to cbfs
TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage`
TEST=Verify that MTCL defined in the file is present:
TEST=`acpidump -b`
TEST=`iasl ssdt.dat`
TEST=`less ssdt.dsl`
TEST=Search for MTCL
Signed-off-by: David Ruth <druth(a)chromium.org>
Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350
---
M src/acpi/acpigen.c
M src/drivers/wifi/generic/Kconfig
M src/drivers/wifi/generic/Makefile.inc
M src/drivers/wifi/generic/acpi.c
M src/include/acpi/acpigen.h
M src/include/device/pci_ids.h
A src/include/mtcl.h
M src/vendorcode/google/chromeos/Makefile.inc
A src/vendorcode/google/chromeos/mtcl.c
9 files changed, 222 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/6
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Change subject: vc/amd/opensil/genoa_poc/mpio: rename mpio_config to configure_mpio
......................................................................
Patch Set 1: Code-Review+2
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Change subject: mb/google/dedede/var/metaknight:Add fw_config probe for multi codec and amplifier
......................................................................
Patch Set 5: Code-Review+2
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Change subject: mb/google/brya/var/*: Use name 'LCD0' for internal panel output
......................................................................
Patch Set 2: Code-Review+1
(1 comment)
Patchset:
PS2:
@Won Chung, please check.
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