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Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Welcome to coreboot!
What Linux patch is needed to use this?
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Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Patch Set 5:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/80170/comment/1178ba67_500d86b2 :
PS5, Line 17:
Why is this ChromeOS specific, that means, you change things under `vendorcode/`?
https://review.coreboot.org/c/coreboot/+/80170/comment/f9f319b3_6a04fe79 :
PS5, Line 27:
Where is the format of the file defined?
File src/drivers/wifi/generic/Kconfig:
https://review.coreboot.org/c/coreboot/+/80170/comment/385884ab_504991a2 :
PS5, Line 69: When enabled, adds the MTCL function for MediaTek
: WiFi chipsets. This function supplies country list information
: used to enable or disable operation on 5.9GHz and 6GHz
: bands.
Please reflow. Then it should fit in three lines?
How can the file be created?
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Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Patch Set 5:
(4 comments)
File src/include/device/pci_ids.h:
https://review.coreboot.org/c/coreboot/+/80170/comment/a200e2c1_7bb1c757 :
PS3, Line 4788:
> nit: tab may be
It looks like it's usually 2 tabs, so I went with that.
File src/include/mtcl.h:
https://review.coreboot.org/c/coreboot/+/80170/comment/fc7b2727_cb9b259c :
PS3, Line 1: #ifndef _MTCL_H_
> nit: keep this as header for the new file […]
Done
File src/vendorcode/google/chromeos/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/80170/comment/2cf968fb_beec27e6 :
PS3, Line 11: ramstage-$(CONFIG_USE_MTCL) += mtcl.c
> nit: before line 10
Done
File src/vendorcode/google/chromeos/mtcl.c:
https://review.coreboot.org/c/coreboot/+/80170/comment/a8140ef0_43f2e507 :
PS3, Line 1: #include <cbfs.h>
> keep this as the first line\ […]
Done
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Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Add MTCL function to ACPI SSDT tables
The MTCL function provides a country list to the Linux kernel via an
ACPI function in SSDT tables for MediaTek chipsets that are capable of
operating on the 6GHz band. The country list is used to selectively
disable 6GHz and 5.9GHz operation based on the country the device is
operating in.
The function needs to read a binary file and send it as a package via
the MTCL method in SSDT for PCIe WiFi chips for MediaTek chipsets.
BUG=b:295544553
TEST=Add Kconfig entry USE_MTCL for pujjo
TEST=Add wifi_mtcl_defaults.hex blob to cbfs
TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage`
TEST=Verify that MTCL defined in the file is present:
TEST=`acpidump -b`
TEST=`iasl ssdt.dat`
TEST=`less ssdt.dsl`
TEST=Search for MTCL
Signed-off-by: David Ruth <druth(a)chromium.org>
Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350
---
M src/acpi/acpigen.c
M src/drivers/wifi/generic/Kconfig
M src/drivers/wifi/generic/Makefile.inc
M src/drivers/wifi/generic/acpi.c
M src/include/acpi/acpigen.h
M src/include/device/pci_ids.h
A src/include/mtcl.h
M src/vendorcode/google/chromeos/Makefile.inc
A src/vendorcode/google/chromeos/mtcl.c
9 files changed, 223 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/5
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Verified+1 by build bot (Jenkins)
Change subject: Add MTCL function to ACPI SSDT tables
......................................................................
Add MTCL function to ACPI SSDT tables
The MTCL function provides a country list to the Linux kernel via an
ACPI function in SSDT tables for MediaTek chipsets that are capable of
operating on the 6GHz band. The country list is used to selectively
disable 6GHz and 5.9GHz operation based on the country the device is
operating in.
The function needs to read a binary file and send it as a package via
the MTCL method in SSDT for PCIe WiFi chips for MediaTek chipsets.
BUG=b:295544553
TEST=Add Kconfig entry USE_MTCL for pujjo
TEST=Add wifi_mtcl_defaults.hex blob to cbfs
TEST=Build coreboot for pujjo `emerge-nissa coreboot chromeos-bootimage`
TEST=Verify that MTCL defined in the file is present:
TEST=`acpidump -b`
TEST=`iasl ssdt.dat`
TEST=`less ssdt.dsl`
TEST=Search for MTCL
Signed-off-by: David Ruth <druth(a)chromium.org>
Change-Id: I9b5e7312a44e114270e664b983626faa6cfee350
---
M src/acpi/acpigen.c
M src/drivers/wifi/generic/Kconfig
M src/drivers/wifi/generic/Makefile.inc
M src/drivers/wifi/generic/acpi.c
M src/include/acpi/acpigen.h
M src/include/device/pci_ids.h
A src/include/mtcl.h
M src/vendorcode/google/chromeos/Makefile.inc
A src/vendorcode/google/chromeos/mtcl.c
9 files changed, 221 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/70/80170/4
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Hello build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/generic/gfx: Generate Intel ACPI backlight controls for LCD device
......................................................................
drivers/generic/gfx: Generate Intel ACPI backlight controls for LCD device
Normally this would be done by the Intel GMA driver, but we can't have
two copies of the _DOD method, so generate the LCD backlight controls
here to allow use of this driver instead of the default GMA panel
definition.
TEST=build/boot Win11 on google/byra (redrix), ensure ACPI brightness
controls functional.
Change-Id: Ic8fbaf7550405f8c6f36012c8efadb8c36b968c2
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/drivers/gfx/generic/generic.c
1 file changed, 36 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/61/80061/4
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Matt DeVillier has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/80175?usp=email )
Change subject: mb/google/drallion: Use name 'LCD0' for internal panel output
......................................................................
mb/google/drallion: Use name 'LCD0' for internal panel output
The GMA driver generates the brightness controls expecting the name
LCD0, so we need to use it here as well so that the DSDT and SSDT parts
match.
TEST=build/boot Win11 on google/drallion, verify brightness controls are
functional.
Change-Id: I6fbdd0c5606ec8f2c497e85bf46d388957f15fa5
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/drallion/variants/drallion/devicetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/80175/2
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Change subject: mb/google/brya/var/*: Use name 'LCD0' for internal panel output
......................................................................
mb/google/brya/var/*: Use name 'LCD0' for internal panel output
The GMA driver generates the brightness controls expecting the name
LCD0, so we need to use it here as well so that the DSDT and SSDT
parts match.
TEST=build/boot Win11 on google/brya (redrix), verify brightness controls are
functional.
Change-Id: I389553b2ddc5b09d165229e2d8066cacf852b82c
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/brya/variants/anahera/overridetree.cb
M src/mainboard/google/brya/variants/anahera4es/overridetree.cb
M src/mainboard/google/brya/variants/anraggar/overridetree.cb
M src/mainboard/google/brya/variants/banshee/overridetree.cb
M src/mainboard/google/brya/variants/brya0/overridetree.cb
M src/mainboard/google/brya/variants/crota/overridetree.cb
M src/mainboard/google/brya/variants/dochi/overridetree.cb
M src/mainboard/google/brya/variants/felwinter/overridetree.cb
M src/mainboard/google/brya/variants/gimble/overridetree.cb
M src/mainboard/google/brya/variants/gimble4es/overridetree.cb
M src/mainboard/google/brya/variants/kano/overridetree.cb
M src/mainboard/google/brya/variants/marasov/overridetree.cb
M src/mainboard/google/brya/variants/mithrax/overridetree.cb
M src/mainboard/google/brya/variants/omnigul/overridetree.cb
M src/mainboard/google/brya/variants/osiris/overridetree.cb
M src/mainboard/google/brya/variants/primus/overridetree.cb
M src/mainboard/google/brya/variants/redrix/overridetree.cb
M src/mainboard/google/brya/variants/redrix4es/overridetree.cb
M src/mainboard/google/brya/variants/skolas/overridetree.cb
M src/mainboard/google/brya/variants/skolas4es/overridetree.cb
M src/mainboard/google/brya/variants/taeko/overridetree.cb
M src/mainboard/google/brya/variants/taeko4es/overridetree.cb
M src/mainboard/google/brya/variants/taniks/overridetree.cb
M src/mainboard/google/brya/variants/vell/overridetree.cb
M src/mainboard/google/brya/variants/volmar/overridetree.cb
25 files changed, 29 insertions(+), 29 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/80174/2
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80178?usp=email )
Change subject: mb/google/hatch/var/jinlon: Ensure LCD backlight controls generated
......................................................................
mb/google/hatch/var/jinlon: Ensure LCD backlight controls generated
Jinlon disables the eps device if no privacy screen is present, so add
a second generic gfx device 'no_eps' to handle that case, so that ACPI
backlight controls are generated either way. Add logic to ensure only
one of the two devices is active.
TEST=build/boot Win11 on google/hatch (jinlon), ensure LCD backlight
controls present and functional on device both with and without a
privacy screen.
Change-Id: Icf20de97d26c8be76c84e87d5dc6ed1a4b6dbfbc
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/hatch/variants/jinlon/mainboard.c
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
2 files changed, 9 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/80178/1
diff --git a/src/mainboard/google/hatch/variants/jinlon/mainboard.c b/src/mainboard/google/hatch/variants/jinlon/mainboard.c
index 51ef346..009a6ad 100644
--- a/src/mainboard/google/hatch/variants/jinlon/mainboard.c
+++ b/src/mainboard/google/hatch/variants/jinlon/mainboard.c
@@ -21,9 +21,11 @@
static void check_for_eps(uint32_t sku_id)
{
struct device *eps_dev = DEV_PTR(eps);
+ struct device *no_eps_dev = DEV_PTR(no_eps);
if (eps_sku(sku_id)) {
printk(BIOS_INFO, "SKU ID %u has EPS\n", sku_id);
+ no_eps_dev->enabled = 0;
return;
}
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index 82694a0..a4c29ca 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -70,7 +70,6 @@
device domain 0 on
device ref igpu on
- register "gfx" = "GMA_DEFAULT_PANEL(0)"
chip drivers/gfx/generic
register "device_count" = "1"
register "device[0].name" = ""LCD0""
@@ -82,6 +81,13 @@
register "device[0].privacy.gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_E0)"
device generic 0 alias eps on end
end
+ chip drivers/gfx/generic
+ register "device_count" = "1"
+ register "device[0].name" = ""LCD0""
+ # Internal panel on the first port of the graphics chip
+ register "device[0].addr" = "0x80010400"
+ device generic 1 alias no_eps on end
+ end
end
device ref xhci on
chip drivers/usb/acpi
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Matt DeVillier has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80177?usp=email )
Change subject: mb/google/hatch/var/jinlon: Use name 'LCD0' for internal panel output
......................................................................
mb/google/hatch/var/jinlon: Use name 'LCD0' for internal panel output
The GMA driver generates the brightness controls expecting the name
LCD0, so we need to use it here as well so that the DSDT and SSDT parts
match.
TEST=build/boot Win11 on google/hatch (jinlon), verify LCD brightness
controls are functional.
Change-Id: I4204a518876bed38584260f7566d4d6c9aaa042f
Signed-off-by: Matt DeVillier <matt.devillier(a)gmail.com>
---
M src/mainboard/google/hatch/variants/jinlon/overridetree.cb
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/80177/1
diff --git a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
index 61ebf24..82694a0 100644
--- a/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
+++ b/src/mainboard/google/hatch/variants/jinlon/overridetree.cb
@@ -73,7 +73,7 @@
register "gfx" = "GMA_DEFAULT_PANEL(0)"
chip drivers/gfx/generic
register "device_count" = "1"
- register "device[0].name" = ""LCD""
+ register "device[0].name" = ""LCD0""
# Use ChromeOS privacy screen HID
register "device[0].hid" = ""GOOG0010""
# Internal panel on the first port of the graphics chip
--
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Gerrit-Project: coreboot
Gerrit-Branch: main
Gerrit-Change-Id: I4204a518876bed38584260f7566d4d6c9aaa042f
Gerrit-Change-Number: 80177
Gerrit-PatchSet: 1
Gerrit-Owner: Matt DeVillier <matt.devillier(a)gmail.com>
Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Subrata Banik <subratabanik(a)google.com>
Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org>
Gerrit-MessageType: newchange