coreboot-gerrit January 2024

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[XS] Change in coreboot[main]: cpu/x86/smi_trigger: use enum cb_err as apm_control return type
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79835?usp=email ) Change subject: cpu/x86/smi_trigger: use enum cb_err as apm_control return type ...................................................................... cpu/x86/smi_trigger: use enum cb_err as apm_control return type Even though the return value from apm_control isn't checked at any of its call sites, using the cb_err enum instead of an integer as return type makes it clearer what the returned value means. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: I07ced74cae915df52a9d439835b84237d51fdd11 Reviewed-on: https://review.coreboot.org/c/coreboot/+/79835 Reviewed-by: Jérémy Compostella <jeremy.compostella(a)intel.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> --- M src/cpu/x86/smi_trigger.c M src/include/cpu/x86/smm.h 2 files changed, 4 insertions(+), 4 deletions(-) Approvals: Matt DeVillier: Looks good to me, approved build bot (Jenkins): Verified Eric Lai: Looks good to me, approved Jérémy Compostella: Looks good to me, but someone else must approve diff --git a/src/cpu/x86/smi_trigger.c b/src/cpu/x86/smi_trigger.c index 9781642..5c63b9e 100644 --- a/src/cpu/x86/smi_trigger.c +++ b/src/cpu/x86/smi_trigger.c @@ -29,11 +29,11 @@ } } -int apm_control(u8 cmd) +enum cb_err apm_control(u8 cmd) { /* Never proceed inside SMI handler or without one. */ if (ENV_SMM || !CONFIG(HAVE_SMI_HANDLER)) - return -1; + return CB_ERR; apmc_log(__func__, cmd); @@ -41,7 +41,7 @@ outb(cmd, pm_acpi_smi_cmd_port()); printk(BIOS_DEBUG, "APMC done.\n"); - return 0; + return CB_SUCCESS; } u8 apm_get_apmc(void) diff --git a/src/include/cpu/x86/smm.h b/src/include/cpu/x86/smm.h index a240ac2..dfb27cd 100644 --- a/src/include/cpu/x86/smm.h +++ b/src/include/cpu/x86/smm.h @@ -43,7 +43,7 @@ #endif /* Send cmd to APM_CNT with HAVE_SMI_HANDLER checking. */ -int apm_control(u8 cmd); +enum cb_err apm_control(u8 cmd); u8 apm_get_apmc(void); void io_trap_handler(int smif); -- To view, visit https://review.coreboot.org/c/coreboot/+/79835?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I07ced74cae915df52a9d439835b84237d51fdd11 Gerrit-Change-Number: 79835 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[NoOp] Change in coreboot[main]: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP
by Lean Sheng Tan (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Angel Pons, Christian Walter, Matt DeVillier, Paul Menzel. Lean Sheng Tan has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79020?usp=email ) Change subject: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP ...................................................................... Patch Set 3: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79020/comment/43b1d812_d9e238b8 : PS2, Line 9: but update it : based on ADL-P MR5 FSP > it's essentially the VBT version, as reported by intelvbtool or DisCon. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 Gerrit-Change-Number: 79020 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Comment-Date: Wed, 10 Jan 2024 14:39:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Matt DeVillier <matt.devillier(a)gmail.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: comment

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[NoOp] Change in coreboot[main]: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP
by Lean Sheng Tan (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Angel Pons, Christian Walter, Lean Sheng Tan, Paul Menzel. Hello Angel Pons, Christian Walter, Matt DeVillier, Maximilian Brune, Paul Menzel, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79020?usp=email to look at the new patch set (#3). Change subject: mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP ...................................................................... mb/prodrive/atlas: Update the VBT blob for ADL-P MR5 FSP Update the VBT version from 249 to 251. It is the same VBT settings as the previous one, but update it based on ADL-P MR5 FSP so it will work with MR5 GOP driver to fix the error "no graphic HOB found". Signed-off-by: Lean Sheng Tan <sheng.tan(a)9elements.com> Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 --- M src/mainboard/prodrive/atlas/data.vbt 1 file changed, 0 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/79020/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79020?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I64229da1cb438de826e54dfc97d47d145fb4f0c9 Gerrit-Change-Number: 79020 Gerrit-PatchSet: 3 Gerrit-Owner: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Lean Sheng Tan <sheng.tan(a)9elements.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Fred Reitberger, Jason Glenesk, Matt DeVillier. Hello Fred Reitberger, Jason Glenesk, Matt DeVillier, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79862?usp=email to look at the new patch set (#3). Change subject: soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h ...................................................................... soc/amd: move IOMMU_IOAPIC_IDX define to amdblocks/ioapic.h Move the IOMMU_IOAPIC_IDX define from amdblocks/data_fabric.h to amdblocks/ioapic.h which is both a more logical place for it to be and this is also a preparation to use the common AMD MADT code for the Stoneyridge SoC. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4 --- M src/soc/amd/common/block/acpi/ivrs.c M src/soc/amd/common/block/acpi/madt.c M src/soc/amd/common/block/include/amdblocks/data_fabric.h M src/soc/amd/common/block/include/amdblocks/ioapic.h M src/soc/amd/genoa_poc/domain.c M src/soc/amd/genoa_poc/root_complex.c 6 files changed, 6 insertions(+), 6 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/79862/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79862?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaa20e802cf5ed93f0d05842abb1aea0d43b1cac4 Gerrit-Change-Number: 79862 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodes
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Arthur Heymans, Martin L Roth, Matt DeVillier, Michał Żygowski, Piotr Król. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79852?usp=email ) Change subject: mb/pcengines/apu2/BiosCallOuts: don't have binaryPI clear LPC decodes ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > Can the OS find the serial port too? Otherwise just flipping HUDSON_LEGACY_FREE to 'no' might be a s […] setting HUDSON_LEGACY_FREE to n will also set the FADT bit that says that there's a 8042 keyboard controller in the system, but the SIO doesn't have a keyboard controller. i get a serial console on the apu2 under linux, but i probably have some kernel command line for that -- To view, visit https://review.coreboot.org/c/coreboot/+/79852?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I91ef4423bd7bf6c1d7a175336f0f89479f2cde02 Gerrit-Change-Number: 79852 Gerrit-PatchSet: 3 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krystian Hebel <krystian.hebel(a)3mdeb.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Wed, 10 Jan 2024 14:29:07 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: comment

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[M] Change in coreboot[main]: mb/google/cherry: Use common mtk_display_init()
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79778?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/cherry: Use common mtk_display_init() ...................................................................... mb/google/cherry: Use common mtk_display_init() TEST=check FW screen on dojo Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79778 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> --- M src/mainboard/google/cherry/mainboard.c M src/soc/mediatek/common/display.c M src/soc/mediatek/mt8195/Makefile.inc M src/soc/mediatek/mt8195/ddp.c M src/soc/mediatek/mt8195/include/soc/ddp.h A src/soc/mediatek/mt8195/include/soc/dsi.h 6 files changed, 30 insertions(+), 44 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/cherry/mainboard.c b/src/mainboard/google/cherry/mainboard.c index c1593ca..0e78f62 100644 --- a/src/mainboard/google/cherry/mainboard.c +++ b/src/mainboard/google/cherry/mainboard.c @@ -7,13 +7,10 @@ #include <device/device.h> #include <device/mmio.h> #include <ec/google/chromeec/ec.h> -#include <edid.h> -#include <framebuffer_info.h> #include <gpio.h> #include <soc/bl31.h> -#include <soc/ddp.h> +#include <soc/display.h> #include <soc/dpm.h> -#include <soc/dptx.h> #include <soc/i2c.h> #include <soc/msdc.h> #include <soc/mtcmos.h> @@ -58,7 +55,7 @@ } /* Set up backlight control pins as output pin and power-off by default */ -static void configure_panel_backlight(void) +static void configure_backlight(void) { gpio_output(GPIO_AP_EDP_BKLTEN, 0); gpio_output(GPIO_BL_PWM_1V8, 0); @@ -72,41 +69,16 @@ gpio_output(GPIO_EN_PP3300_DISP_X, 1); } -static bool configure_display(void) +static struct panel_description panel = { + .configure_backlight = configure_backlight, + .power_on = power_on_panel, + .disp_path = DISP_PATH_EDP, + .orientation = LB_FB_ORIENTATION_NORMAL, +}; + +struct panel_description *get_active_panel(void) { - struct edid edid; - struct fb_info *info; - const char *name; - - printk(BIOS_INFO, "%s: Starting display initialization\n", __func__); - - mtcmos_display_power_on(); - mtcmos_protect_display_bus(); - configure_panel_backlight(); - power_on_panel(); - - mtk_ddp_init(); - mdelay(200); - - if (mtk_edp_init(&edid) < 0) { - printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__); - return false; - } - name = edid.ascii_string; - if (name[0] == '\0') - name = "unknown name"; - printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, - edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, - edid.mode.refresh); - - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - - mtk_ddp_mode_set(&edid); - info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); - if (info) - fb_set_orientation(info, LB_FB_ORIENTATION_NORMAL); - - return true; + return &panel; } static void configure_i2s(void) @@ -133,7 +105,7 @@ static void mainboard_init(struct device *dev) { if (display_init_required()) - configure_display(); + mtk_display_init(); else printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index d51151e..a5b0e6b 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -43,6 +43,13 @@ return -1; } +__weak int mtk_dsi_init(u32 mode_flags, u32 format, u32 lanes, + const struct edid *edid, const u8 *init_commands) +{ + printk(BIOS_WARNING, "%s: Not supported\n", __func__); + return -1; +} + int mtk_display_init(void) { struct edid edid; diff --git a/src/soc/mediatek/mt8195/Makefile.inc b/src/soc/mediatek/mt8195/Makefile.inc index 73ea6fa..56a10bc 100644 --- a/src/soc/mediatek/mt8195/Makefile.inc +++ b/src/soc/mediatek/mt8195/Makefile.inc @@ -45,6 +45,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/display.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c diff --git a/src/soc/mediatek/mt8195/ddp.c b/src/soc/mediatek/mt8195/ddp.c index 6277fa4..2bd95a2 100644 --- a/src/soc/mediatek/mt8195/ddp.c +++ b/src/soc/mediatek/mt8195/ddp.c @@ -150,7 +150,7 @@ write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); } -void mtk_ddp_mode_set(const struct edid *edid) +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) { u32 fmt = OVL_INFMT_RGBA8888; u32 bpp = edid->framebuffer_bits_per_pixel / 8; diff --git a/src/soc/mediatek/mt8195/include/soc/ddp.h b/src/soc/mediatek/mt8195/include/soc/ddp.h index 3394490..52bf9ae 100644 --- a/src/soc/mediatek/mt8195/include/soc/ddp.h +++ b/src/soc/mediatek/mt8195/include/soc/ddp.h @@ -5,6 +5,7 @@ #include <soc/addressmap.h> #include <soc/ddp_common.h> +#include <soc/display.h> #include <types.h> #define MAIN_PATH_OVL_NR 2 @@ -366,7 +367,4 @@ SMI_LARB_PORT_L0_OVL_RDMA0 = 0x388, }; -void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid); - #endif diff --git a/src/soc/mediatek/mt8195/include/soc/dsi.h b/src/soc/mediatek/mt8195/include/soc/dsi.h new file mode 100644 index 0000000..0fd65b9 --- /dev/null +++ b/src/soc/mediatek/mt8195/include/soc/dsi.h @@ -0,0 +1,8 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef SOC_MEDIATEK_MT8195_DSI_H +#define SOC_MEDIATEK_MT8195_DSI_H + +#include <soc/dsi_common.h> + +#endif -- To view, visit https://review.coreboot.org/c/coreboot/+/79778?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie870899226588ac2a2e80f77e434455f4913d387 Gerrit-Change-Number: 79778 Gerrit-PatchSet: 8 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: mb/google/corsola: Use common mtk_display_init()
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79777?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: mb/google/corsola: Use common mtk_display_init() ...................................................................... mb/google/corsola: Use common mtk_display_init() TEST=check FW screen on Steelix, Tentacruel and Starmie Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79777 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/corsola/Makefile.inc M src/mainboard/google/corsola/boardid.c D src/mainboard/google/corsola/display.c D src/mainboard/google/corsola/display.h M src/mainboard/google/corsola/mainboard.c A src/mainboard/google/corsola/panel.c A src/mainboard/google/corsola/panel.h M src/mainboard/google/corsola/panel_anx7625.c M src/mainboard/google/corsola/panel_ps8640.c M src/mainboard/google/corsola/panel_starmie.c M src/soc/mediatek/common/display.c M src/soc/mediatek/mt8186/Makefile.inc M src/soc/mediatek/mt8186/ddp.c M src/soc/mediatek/mt8186/include/soc/ddp.h 14 files changed, 135 insertions(+), 205 deletions(-) Approvals: Yu-Ping Wu: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/google/corsola/Makefile.inc b/src/mainboard/google/corsola/Makefile.inc index dce226f..5483167 100644 --- a/src/mainboard/google/corsola/Makefile.inc +++ b/src/mainboard/google/corsola/Makefile.inc @@ -19,8 +19,8 @@ ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-y += chromeos.c -ramstage-y += display.c ramstage-y += mainboard.c +ramstage-y += panel.c ramstage-y += panel_anx7625.c ramstage-y += panel_ps8640.c ramstage-y += regulator.c diff --git a/src/mainboard/google/corsola/boardid.c b/src/mainboard/google/corsola/boardid.c index 59c9f5c..443c3d1 100644 --- a/src/mainboard/google/corsola/boardid.c +++ b/src/mainboard/google/corsola/boardid.c @@ -6,7 +6,7 @@ #include <ec/google/chromeec/ec.h> #include <soc/auxadc.h> -#include "display.h" +#include "panel.h" /* board_id is provided by ec/google/chromeec/ec_boardid.c */ diff --git a/src/mainboard/google/corsola/display.c b/src/mainboard/google/corsola/display.c deleted file mode 100644 index c7a6578..0000000 --- a/src/mainboard/google/corsola/display.c +++ /dev/null @@ -1,131 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <boardid.h> -#include <cbfs.h> -#include <console/console.h> -#include <device/i2c_simple.h> -#include <edid.h> -#include <gpio.h> -#include <soc/ddp.h> -#include <soc/dsi.h> -#include <soc/gpio_common.h> -#include <soc/mtcmos.h> - -#include "display.h" -#include "gpio.h" - -void aw37503_init(unsigned int bus) -{ - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x00, 0x14, 0x1F, 0); - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x01, 0x14, 0x1F, 0); - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x4C, 0xFF, 0); - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x03, 0x43, 0xFF, 0); - i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x00, 0xFF, 0); -} - -bool is_pmic_aw37503(unsigned int bus) -{ - u8 vendor_id; - return (!i2c_read_field(bus, PMIC_AW37503_SLAVE, - 0x04, &vendor_id, 0x0F, 0) && vendor_id == 0x01); -} - -static void backlight_control(void) -{ - /* Disable backlight before turning on bridge */ - gpio_output(GPIO_AP_EDP_BKLTEN, 0); - gpio_output(GPIO_BL_PWM_1V8, 0); - /* For staryu variants, GPIO_EN_PP3300_DISP_X is controlled in - mipi_panel_power_on() */ - if (!CONFIG(BOARD_GOOGLE_STARYU_COMMON)) - gpio_output(GPIO_EN_PP3300_DISP_X, 1); -} - -struct panel_description *get_panel_from_cbfs(struct panel_description *desc) -{ - char cbfs_name[64]; - static union { - u8 raw[4 * 1024]; - struct panel_serializable_data s; - } buffer; - - if (!desc->name) - return NULL; - - snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); - if (cbfs_load(cbfs_name, buffer.raw, sizeof(buffer))) - desc->s = &buffer.s; - else - printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); - - return desc->s ? desc : NULL; -} - -static struct panel_description *get_active_panel(void) -{ - /* Board-specific exceptions */ - if (CONFIG(BOARD_GOOGLE_STEELIX) && board_id() < 2) /* Early builds use PS8640 */ - return get_ps8640_description(); - - if (CONFIG(DRIVER_ANALOGIX_ANX7625)) - return get_anx7625_description(); - - if (CONFIG(DRIVER_PARADE_PS8640)) - return get_ps8640_description(); - - /* MIPI panels */ - return get_panel_description(); -} - -int configure_display(void) -{ - /* Set up backlight control pins as output pin and power-off by default */ - backlight_control(); - - const struct panel_description *panel = get_active_panel(); - - if (!panel) - return -1; - - printk(BIOS_INFO, "%s: Starting display init\n", __func__); - - if (panel->power_on) - panel->power_on(); - - struct edid edid = panel->s->edid; - const char *name = edid.ascii_string; - if (name[0] == '\0') - name = "unknown name"; - printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, - edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, - edid.mode.refresh); - - mtcmos_display_power_on(); - mtcmos_protect_display_bus(); - - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - mtk_ddp_init(); - u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM | - MIPI_DSI_MODE_EOT_PACKET); - - if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, - panel->s->init) < 0) { - printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); - return -1; - } - - if (panel->post_power_on && panel->post_power_on(BRIDGE_I2C, &edid) < 0) { - printk(BIOS_ERR, "%s: Failed to post power on bridge\n", __func__); - return -1; - } - - mtk_ddp_mode_set(&edid); - struct fb_info *info = fb_new_framebuffer_info_from_edid(&edid, - (uintptr_t)0); - if (info) - fb_set_orientation(info, panel->orientation); - - return 0; -} diff --git a/src/mainboard/google/corsola/display.h b/src/mainboard/google/corsola/display.h deleted file mode 100644 index 7631bb9..0000000 --- a/src/mainboard/google/corsola/display.h +++ /dev/null @@ -1,39 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ -#define __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ - -#include <edid.h> -#include <mipi/panel.h> -#include <soc/i2c.h> - -#define BRIDGE_I2C I2C0 -#define PMIC_AW37503_SLAVE 0x3E -#define PMIC_I2C_BUS I2C6 - -struct panel_description { - void (*power_on)(void); /* Callback to turn on panel */ - int (*post_power_on)(u8 i2c_bus, struct edid *edid); - const char *name; /* Panel name in CBFS */ - struct panel_serializable_data *s; - enum lb_fb_orientation orientation; -}; - -void aw37503_init(unsigned int bus); -bool is_pmic_aw37503(unsigned int bus); -int configure_display(void); -uint32_t panel_id(void); - -/* Return the mipi panel description from given panel id */ -struct panel_description *get_panel_description(void); - -/* Return the ANX7625 bridge description */ -struct panel_description *get_anx7625_description(void); - -/* Return the PS8640 bridge description */ -struct panel_description *get_ps8640_description(void); - -/* Load panel serializable data from CBFS */ -struct panel_description *get_panel_from_cbfs(struct panel_description *desc); - -#endif diff --git a/src/mainboard/google/corsola/mainboard.c b/src/mainboard/google/corsola/mainboard.c index 37f3a70..a1ba5f9 100644 --- a/src/mainboard/google/corsola/mainboard.c +++ b/src/mainboard/google/corsola/mainboard.c @@ -6,13 +6,14 @@ #include <fw_config.h> #include <gpio.h> #include <soc/bl31.h> +#include <soc/display.h> #include <soc/i2c.h> #include <soc/msdc.h> #include <soc/spm.h> #include <soc/usb.h> -#include "display.h" #include "gpio.h" +#include "panel.h" static void configure_alc1019(void) { @@ -65,7 +66,7 @@ register_reset_to_bl31(GPIO_RESET.id, true); if (display_init_required()) { - if (configure_display() < 0) + if (mtk_display_init() < 0) printk(BIOS_ERR, "%s: Failed to init display\n", __func__); } else { if (CONFIG(BOARD_GOOGLE_STARYU_COMMON)) { diff --git a/src/mainboard/google/corsola/panel.c b/src/mainboard/google/corsola/panel.c new file mode 100644 index 0000000..0eb9420 --- /dev/null +++ b/src/mainboard/google/corsola/panel.c @@ -0,0 +1,54 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <boardid.h> +#include <cbfs.h> +#include <console/console.h> +#include <device/i2c_simple.h> +#include <edid.h> +#include <gpio.h> +#include <soc/ddp.h> +#include <soc/dsi.h> +#include <soc/gpio_common.h> +#include <soc/mtcmos.h> + +#include "gpio.h" +#include "panel.h" + +void aw37503_init(unsigned int bus) +{ + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x00, 0x14, 0x1F, 0); + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x01, 0x14, 0x1F, 0); + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x4C, 0xFF, 0); + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x03, 0x43, 0xFF, 0); + i2c_write_field(bus, PMIC_AW37503_SLAVE, 0x21, 0x00, 0xFF, 0); +} + +bool is_pmic_aw37503(unsigned int bus) +{ + u8 vendor_id; + return (!i2c_read_field(bus, PMIC_AW37503_SLAVE, + 0x04, &vendor_id, 0x0F, 0) && vendor_id == 0x01); +} + +void backlight_control(void) +{ + /* Set up backlight control pins as output pin and power-off by default */ + gpio_output(GPIO_AP_EDP_BKLTEN, 0); + gpio_output(GPIO_BL_PWM_1V8, 0); +} + +struct panel_description *get_active_panel(void) +{ + /* Board-specific exceptions */ + if (CONFIG(BOARD_GOOGLE_STEELIX) && board_id() < 2) /* Early builds use PS8640 */ + return get_ps8640_description(); + + if (CONFIG(DRIVER_ANALOGIX_ANX7625)) + return get_anx7625_description(); + + if (CONFIG(DRIVER_PARADE_PS8640)) + return get_ps8640_description(); + + /* MIPI panels */ + return get_panel_description(); +} diff --git a/src/mainboard/google/corsola/panel.h b/src/mainboard/google/corsola/panel.h new file mode 100644 index 0000000..a4198f3 --- /dev/null +++ b/src/mainboard/google/corsola/panel.h @@ -0,0 +1,27 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ +#define __MAINBOARD_GOOGLE_CORSOLA_DISPLAY_H__ + +#include <soc/display.h> +#include <soc/i2c.h> + +#define BRIDGE_I2C I2C0 +#define PMIC_AW37503_SLAVE 0x3E +#define PMIC_I2C_BUS I2C6 + +void aw37503_init(unsigned int bus); +bool is_pmic_aw37503(unsigned int bus); +uint32_t panel_id(void); +void backlight_control(void); + +/* Return the mipi panel description from given panel id */ +struct panel_description *get_panel_description(void); + +/* Return the ANX7625 bridge description */ +struct panel_description *get_anx7625_description(void); + +/* Return the PS8640 bridge description */ +struct panel_description *get_ps8640_description(void); + +#endif diff --git a/src/mainboard/google/corsola/panel_anx7625.c b/src/mainboard/google/corsola/panel_anx7625.c index 7b50e47..193a501 100644 --- a/src/mainboard/google/corsola/panel_anx7625.c +++ b/src/mainboard/google/corsola/panel_anx7625.c @@ -7,8 +7,8 @@ #include <gpio.h> #include <soc/i2c.h> -#include "display.h" #include "gpio.h" +#include "panel.h" static void bridge_anx7625_power_on(void) { @@ -23,39 +23,42 @@ gpio_output(GPIO_EDPBRDG_RST_L, 1); } -static int bridge_anx7625_get_edid(u8 i2c_bus, struct edid *edid) +static int bridge_anx7625_get_edid(struct edid *edid) { - if (anx7625_init(i2c_bus) < 0) { + if (anx7625_init(BRIDGE_I2C) < 0) { printk(BIOS_ERR, "%s: Can't init ANX7625 bridge\n", __func__); return -1; } - if (anx7625_dp_get_edid(i2c_bus, edid) < 0) { + if (anx7625_dp_get_edid(BRIDGE_I2C, edid) < 0) { printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); return -1; } return 0; } -static int bridge_anx7625_post_power_on(u8 i2c_bus, struct edid *edid) +static int bridge_anx7625_post_power_on(const struct edid *edid) { - return anx7625_dp_start(i2c_bus, edid); + return anx7625_dp_start(BRIDGE_I2C, edid); } -static struct panel_serializable_data anx7625_data; +static void panel_power_on(void) +{ + /* Turn on the panel */ + gpio_output(GPIO_EN_PP3300_DISP_X, 1); + bridge_anx7625_power_on(); +} static struct panel_description anx7625_bridge = { - .s = &anx7625_data, + .configure_backlight = backlight_control, + .power_on = panel_power_on, + .get_edid = bridge_anx7625_get_edid, .post_power_on = bridge_anx7625_post_power_on, + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_NORMAL, }; struct panel_description *get_anx7625_description(void) { mtk_i2c_bus_init(BRIDGE_I2C, I2C_SPEED_FAST); - bridge_anx7625_power_on(); - if (bridge_anx7625_get_edid(BRIDGE_I2C, &anx7625_bridge.s->edid) < 0) { - printk(BIOS_ERR, "Can't get panel's edid\n"); - return NULL; - } return &anx7625_bridge; } diff --git a/src/mainboard/google/corsola/panel_ps8640.c b/src/mainboard/google/corsola/panel_ps8640.c index bb1e4eb..94bf47d 100644 --- a/src/mainboard/google/corsola/panel_ps8640.c +++ b/src/mainboard/google/corsola/panel_ps8640.c @@ -8,8 +8,8 @@ #include <soc/i2c.h> #include <soc/regulator.h> -#include "display.h" #include "gpio.h" +#include "panel.h" static void bridge_ps8640_power_on(void) { @@ -45,35 +45,38 @@ gpio_output(GPIO_EDPBRDG_RST_L, 1); } -static int bridge_ps8640_get_edid(u8 i2c_bus, struct edid *edid) +static void panel_power_on(void) +{ + /* Turn on the panel */ + gpio_output(GPIO_EN_PP3300_DISP_X, 1); + bridge_ps8640_power_on(); +} + +static int bridge_ps8640_get_edid(struct edid *edid) { const u8 chip = 0x8; - if (ps8640_init(i2c_bus, chip) < 0) { + if (ps8640_init(BRIDGE_I2C, chip) < 0) { printk(BIOS_ERR, "%s: Can't init PS8640 bridge\n", __func__); return -1; } - if (ps8640_get_edid(i2c_bus, chip, edid) < 0) { + if (ps8640_get_edid(BRIDGE_I2C, chip, edid) < 0) { printk(BIOS_ERR, "%s: Can't get panel's edid\n", __func__); return -1; } return 0; } -static struct panel_serializable_data ps8640_data; - static struct panel_description ps8640_bridge = { - .s = &ps8640_data, + .configure_backlight = backlight_control, + .power_on = panel_power_on, + .get_edid = bridge_ps8640_get_edid, + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_NORMAL, }; struct panel_description *get_ps8640_description(void) { mtk_i2c_bus_init(BRIDGE_I2C, I2C_SPEED_FAST); - bridge_ps8640_power_on(); - if (bridge_ps8640_get_edid(BRIDGE_I2C, &ps8640_bridge.s->edid) < 0) { - printk(BIOS_ERR, "Can't get panel's edid\n"); - return NULL; - } return &ps8640_bridge; } diff --git a/src/mainboard/google/corsola/panel_starmie.c b/src/mainboard/google/corsola/panel_starmie.c index 55e9dbf..1de2c61 100644 --- a/src/mainboard/google/corsola/panel_starmie.c +++ b/src/mainboard/google/corsola/panel_starmie.c @@ -6,8 +6,8 @@ #include <soc/regulator.h> #include <soc/tps65132s.h> -#include "display.h" #include "gpio.h" +#include "panel.h" static void mipi_panel_power_on(void) { @@ -51,20 +51,26 @@ /* K&D panel vendor and ILI9882T chip, K&D and STA panel are identical except manufacturer_name. */ [6] = { + .configure_backlight = backlight_control, .power_on = mipi_panel_power_on, .name = "STA_ILI9882T", + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_LEFT_UP, }, /* STA panel vendor and ILI9882T chip */ [9] = { + .configure_backlight = backlight_control, .power_on = mipi_panel_power_on, .name = "STA_ILI9882T", + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_LEFT_UP, }, /* STA panel vendor and HIMAX83102_J02 chip */ [10] = { + .configure_backlight = backlight_control, .power_on = mipi_panel_power_on, .name = "STA_HIMAX83102_J02", + .disp_path = DISP_PATH_MIPI, .orientation = LB_FB_ORIENTATION_LEFT_UP, }, }; @@ -75,5 +81,5 @@ if (id >= ARRAY_SIZE(starmie_panels)) return NULL; - return get_panel_from_cbfs(&starmie_panels[id]); + return &starmie_panels[id]; } diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c index 72b7fe0..d51151e 100644 --- a/src/soc/mediatek/common/display.c +++ b/src/soc/mediatek/common/display.c @@ -37,6 +37,12 @@ return NULL; } +__weak int mtk_edp_init(struct edid *edid) +{ + printk(BIOS_WARNING, "%s: Not supported\n", __func__); + return -1; +} + int mtk_display_init(void) { struct edid edid; diff --git a/src/soc/mediatek/mt8186/Makefile.inc b/src/soc/mediatek/mt8186/Makefile.inc index 8fe923f..3a3cc07 100644 --- a/src/soc/mediatek/mt8186/Makefile.inc +++ b/src/soc/mediatek/mt8186/Makefile.inc @@ -38,6 +38,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/display.c ramstage-y += ../common/dsi.c ../common/mtk_mipi_dphy.c ramstage-y += ../common/emi.c ramstage-y += ../common/mcu.c @@ -53,6 +54,7 @@ ramstage-y += ../common/usb.c usb.c CPPFLAGS_common += -Isrc/soc/mediatek/mt8186/include +CPPFLAGS_common += -Isrc/soc/mediatek/common/dp/include CPPFLAGS_common += -Isrc/soc/mediatek/common/include BL31_MAKEARGS += PLAT=mt8186 diff --git a/src/soc/mediatek/mt8186/ddp.c b/src/soc/mediatek/mt8186/ddp.c index 6706ed7..5a5f544 100644 --- a/src/soc/mediatek/mt8186/ddp.c +++ b/src/soc/mediatek/mt8186/ddp.c @@ -141,7 +141,7 @@ write32((void *)(SMI_LARB0 + SMI_LARB_PORT_L0_OVL_RDMA0), 0); } -void mtk_ddp_mode_set(const struct edid *edid) +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path) { u32 fmt = OVL_INFMT_RGBA8888; u32 bpp = edid->framebuffer_bits_per_pixel / 8; diff --git a/src/soc/mediatek/mt8186/include/soc/ddp.h b/src/soc/mediatek/mt8186/include/soc/ddp.h index e66563d..f6e690a 100644 --- a/src/soc/mediatek/mt8186/include/soc/ddp.h +++ b/src/soc/mediatek/mt8186/include/soc/ddp.h @@ -11,6 +11,7 @@ #include <device/mmio.h> #include <soc/addressmap.h> #include <soc/ddp_common.h> +#include <soc/display.h> #include <types.h> #define SMI_LARB_PORT_L0_OVL_RDMA0 0x388 @@ -254,7 +255,4 @@ static struct disp_postmask_regs *const disp_postmask = (void *)DISP_POSTMASK0_BASE; static struct disp_dither_regs *const disp_dither = (void *)DISP_DITHER0_BASE; -void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid); - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/79777?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I429218d59389a6ab86b522dd597c07fa5b8ea821 Gerrit-Change-Number: 79777 Gerrit-PatchSet: 8 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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[L] Change in coreboot[main]: soc/mediatek: Add common implementation to configure display
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79776?usp=email ) Change subject: soc/mediatek: Add common implementation to configure display ...................................................................... soc/mediatek: Add common implementation to configure display The sequences of configure_display() are similar on MediaTek platforms. The sequences usually involve following steps: 1. Setup mtcmos for display hardware block. - mtcmos_display_power_on() - mtcmos_protect_display_bus() 2. Configure backlight pins 3. Power on the panel - It also powers on the bridge in MIPI DSI to eDP case. 4. General initialization for DDP(display data path) 5. Initialize eDP/MIPI DSI accordingly, - For eDP path, it calls mtk_edp_init() to get edid from the panel and initializes eDP driver. - For MIPI DSI path, the edid is retrieved either from the bridge or from CBFS (the serializable data), and then initializes DSI driver. 6. Set framebuffer bits per pixel 7. Setup DDP mode 8. Setup panel orientation This patch extracts geralt/display.c to mediatek/common/display.c and refactors `struct panel_description` to generalize the display init sequences. configure_display() is also renamed to mtk_display_init(). TEST=check FW screen on geralt. Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Signed-off-by: Yidi Lin <yidilin(a)chromium.org> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79776 Reviewed-by: Yu-Ping Wu <yupingso(a)google.com> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/geralt/Makefile.inc D src/mainboard/google/geralt/display.c D src/mainboard/google/geralt/display.h M src/mainboard/google/geralt/mainboard.c M src/mainboard/google/geralt/panel.c M src/mainboard/google/geralt/panel.h M src/mainboard/google/geralt/panel_geralt.c A src/soc/mediatek/common/display.c A src/soc/mediatek/common/include/soc/display.h M src/soc/mediatek/mt8188/Makefile.inc M src/soc/mediatek/mt8188/include/soc/ddp.h 11 files changed, 156 insertions(+), 159 deletions(-) Approvals: build bot (Jenkins): Verified Yu-Ping Wu: Looks good to me, approved diff --git a/src/mainboard/google/geralt/Makefile.inc b/src/mainboard/google/geralt/Makefile.inc index 2b1f313..e954309 100644 --- a/src/mainboard/google/geralt/Makefile.inc +++ b/src/mainboard/google/geralt/Makefile.inc @@ -20,7 +20,6 @@ ramstage-y += memlayout.ld ramstage-y += boardid.c ramstage-y += chromeos.c -ramstage-y += display.c ramstage-y += mainboard.c ramstage-y += panel.c ramstage-y += regulator.c diff --git a/src/mainboard/google/geralt/display.c b/src/mainboard/google/geralt/display.c deleted file mode 100644 index 68a0a22..0000000 --- a/src/mainboard/google/geralt/display.c +++ /dev/null @@ -1,74 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#include <console/console.h> -#include <delay.h> -#include <edid.h> -#include <framebuffer_info.h> -#include <gpio.h> -#include <soc/ddp.h> -#include <soc/dptx.h> -#include <soc/dsi.h> -#include <soc/gpio_common.h> -#include <soc/mtcmos.h> - -#include "display.h" -#include "gpio.h" -#include "panel.h" - -int configure_display(void) -{ - struct edid edid; - struct fb_info *info; - const char *name; - struct panel_description *panel = get_active_panel(); - if (!panel) - return -1; - - printk(BIOS_INFO, "%s: Starting display initialization\n", __func__); - - mtcmos_display_power_on(); - mtcmos_protect_display_bus(); - - panel->configure_panel_backlight(); - panel->power_on(); - - mtk_ddp_init(); - - if (panel->disp_path == DISP_PATH_EDP) { - mdelay(200); - if (mtk_edp_init(&edid) < 0) { - printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__); - return -1; - } - - } else { - u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | - MIPI_DSI_MODE_VIDEO_SYNC_PULSE | - MIPI_DSI_MODE_LPM | - MIPI_DSI_MODE_EOT_PACKET); - - edid = panel->s->edid; - - if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, - panel->s->init) < 0) { - printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); - return -1; - } - } - - name = edid.ascii_string; - if (name[0] == '\0') - name = "unknown name"; - printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, - edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, - edid.mode.refresh); - - edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); - - mtk_ddp_mode_set(&edid, panel->disp_path); - info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); - if (info) - fb_set_orientation(info, LB_FB_ORIENTATION_BOTTOM_UP); - - return 0; -} diff --git a/src/mainboard/google/geralt/display.h b/src/mainboard/google/geralt/display.h deleted file mode 100644 index 29153b3..0000000 --- a/src/mainboard/google/geralt/display.h +++ /dev/null @@ -1,8 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0-only */ - -#ifndef __MAINBOARD_GOOGLE_GERALT_DISPLAY_H__ -#define __MAINBOARD_GOOGLE_GERALT_DISPLAY_H__ - -int configure_display(void); - -#endif diff --git a/src/mainboard/google/geralt/mainboard.c b/src/mainboard/google/geralt/mainboard.c index 6bb8380..3f9ab5d 100644 --- a/src/mainboard/google/geralt/mainboard.c +++ b/src/mainboard/google/geralt/mainboard.c @@ -3,13 +3,13 @@ #include <bootmode.h> #include <device/device.h> #include <soc/bl31.h> +#include <soc/display.h> #include <soc/i2c.h> #include <soc/msdc.h> #include <soc/mt6359p.h> #include <soc/mtcmos.h> #include <soc/usb.h> -#include "display.h" #include "gpio.h" #define AFE_SE_SECURE_CON (AUDIO_BASE + 0x17a8) @@ -44,7 +44,7 @@ mt6359p_init_pmif_arb(); if (display_init_required()) { - if (configure_display() < 0) + if (mtk_display_init() < 0) printk(BIOS_ERR, "%s: Failed to init display\n", __func__); } else { printk(BIOS_INFO, "%s: Skipped display initialization\n", __func__); diff --git a/src/mainboard/google/geralt/panel.c b/src/mainboard/google/geralt/panel.c index e25b5cb..202eda7 100644 --- a/src/mainboard/google/geralt/panel.c +++ b/src/mainboard/google/geralt/panel.c @@ -12,30 +12,6 @@ #include "gpio.h" #include "panel.h" -static void get_mipi_cmd_from_cbfs(struct panel_description *desc) -{ - /* - * The CBFS file name is panel-{MANUFACTURER}-${PANEL_NAME}, where MANUFACTURER is 3 - * characters and PANEL_NAME is usually 13 characters. - */ - char cbfs_name[64]; - static union { - u8 raw[4 * 1024]; /* Most panels only need < 2K. */ - struct panel_serializable_data s; - } buffer; - - if (!desc->name) { - printk(BIOS_ERR, "Missing panel CBFS file name.\n"); - return; - } - - snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); - if (cbfs_load(cbfs_name, buffer.raw, sizeof(buffer))) - desc->s = &buffer.s; - else - printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); -} - struct panel_description __weak *get_panel_description(uint32_t panel_id) { printk(BIOS_WARNING, "%s: %s: the panel configuration is not ready\n", @@ -46,33 +22,7 @@ struct panel_description *get_active_panel(void) { uint32_t active_panel_id = panel_id(); - - struct panel_description *panel = get_panel_description(active_panel_id); - if (!panel || panel->disp_path == DISP_PATH_NONE) { - printk(BIOS_ERR, "%s: Panel %u is not supported.\n", __func__, active_panel_id); - return NULL; - } - - /* For eDP, we will get edid after eDP initialization is done, so we return directly. */ - if (panel->disp_path == DISP_PATH_EDP) { - printk(BIOS_INFO, "%s: Use eDP as the display\n", __func__); - return panel; - } - - /* We need to find init cmds for MIPI panel from CBFS */ - get_mipi_cmd_from_cbfs(panel); - if (!panel->s) - return NULL; - - const struct edid *edid = &panel->s->edid; - const char *name = edid->ascii_string; - if (name[0] == '\0') { - name = "unknown name"; - printk(BIOS_INFO, "%s: Found ID %u: '%s %s' %dx%d@%dHz\n", __func__, - active_panel_id, edid->manufacturer_name, name, edid->mode.ha, - edid->mode.va, edid->mode.refresh); - } - return panel; + return get_panel_description(active_panel_id); } void configure_mipi_pwm_backlight(void) diff --git a/src/mainboard/google/geralt/panel.h b/src/mainboard/google/geralt/panel.h index 71cecdf..3d0fafd 100644 --- a/src/mainboard/google/geralt/panel.h +++ b/src/mainboard/google/geralt/panel.h @@ -3,23 +3,11 @@ #ifndef __MAINBOARD_GOOGLE_GERALT_PANEL_H__ #define __MAINBOARD_GOOGLE_GERALT_PANEL_H__ -#include <boot/coreboot_tables.h> -#include <mipi/panel.h> -#include <soc/ddp.h> - -struct panel_description { - const char *name; - struct panel_serializable_data *s; - void (*power_on)(void); - void (*configure_panel_backlight)(void); - enum disp_path_sel disp_path; - bool pwm_ctrl_gpio; -}; +#include <soc/display.h> void configure_mipi_pwm_backlight(void); void fill_lp_backlight_gpios(struct lb_gpios *gpios); uint32_t panel_id(void); struct panel_description *get_panel_description(uint32_t panel_id); -struct panel_description *get_active_panel(void); #endif diff --git a/src/mainboard/google/geralt/panel_geralt.c b/src/mainboard/google/geralt/panel_geralt.c index 2ca95be..6eed3fb12 100644 --- a/src/mainboard/google/geralt/panel_geralt.c +++ b/src/mainboard/google/geralt/panel_geralt.c @@ -52,7 +52,8 @@ [1] = { .name = "BOE_TV110C9M_LL0", .power_on = power_on_mipi_boe_tv110c9m_ll0, - .configure_panel_backlight = configure_mipi_pwm_backlight, + .configure_backlight = configure_mipi_pwm_backlight, + .orientation = LB_FB_ORIENTATION_BOTTOM_UP, .disp_path = DISP_PATH_MIPI, .pwm_ctrl_gpio = true, }, diff --git a/src/soc/mediatek/common/display.c b/src/soc/mediatek/common/display.c new file mode 100644 index 0000000..72b7fe0 --- /dev/null +++ b/src/soc/mediatek/common/display.c @@ -0,0 +1,116 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <cbfs.h> +#include <console/console.h> +#include <delay.h> +#include <edid.h> +#include <framebuffer_info.h> +#include <soc/ddp.h> +#include <soc/display.h> +#include <soc/dptx.h> +#include <soc/dsi.h> +#include <soc/mtcmos.h> +#include <string.h> + +static struct panel_serializable_data *get_mipi_cmd_from_cbfs(struct panel_description *desc) +{ + /* + * The CBFS file name is panel-{MANUFACTURER}-${PANEL_NAME}, where MANUFACTURER is 3 + * characters and PANEL_NAME is usually 13 characters. + */ + char cbfs_name[64]; + static union { + u8 raw[4 * 1024]; /* Most panels only need < 2K. */ + struct panel_serializable_data s; + } buffer; + + if (!desc->name) { + printk(BIOS_ERR, "Missing panel CBFS file name.\n"); + return NULL; + } + + snprintf(cbfs_name, sizeof(cbfs_name), "panel-%s", desc->name); + if (cbfs_load(cbfs_name, buffer.raw, sizeof(buffer))) + return &buffer.s; + + printk(BIOS_ERR, "Missing %s in CBFS.\n", cbfs_name); + return NULL; +} + +int mtk_display_init(void) +{ + struct edid edid; + struct fb_info *info; + const char *name; + struct panel_description *panel = get_active_panel(); + + if (!panel || panel->disp_path == DISP_PATH_NONE) { + printk(BIOS_ERR, "%s: Failed to get the active panel\n", __func__); + return -1; + } + + printk(BIOS_INFO, "%s: Starting display initialization\n", __func__); + + mtcmos_display_power_on(); + mtcmos_protect_display_bus(); + + if (panel->configure_backlight) + panel->configure_backlight(); + if (panel->power_on) + panel->power_on(); + + mtk_ddp_init(); + + if (panel->disp_path == DISP_PATH_EDP) { + mdelay(200); + if (mtk_edp_init(&edid) < 0) { + printk(BIOS_ERR, "%s: Failed to initialize eDP\n", __func__); + return -1; + } + } else { + + struct panel_serializable_data *mipi_data = NULL; + + if (panel->get_edid) { + if (panel->get_edid(&edid) < 0) + return -1; + } else { + mipi_data = get_mipi_cmd_from_cbfs(panel); + if (!mipi_data) + return -1; + edid = mipi_data->edid; + } + + u32 mipi_dsi_flags = (MIPI_DSI_MODE_VIDEO | + MIPI_DSI_MODE_VIDEO_SYNC_PULSE | + MIPI_DSI_MODE_LPM | + MIPI_DSI_MODE_EOT_PACKET); + + if (mtk_dsi_init(mipi_dsi_flags, MIPI_DSI_FMT_RGB888, 4, &edid, + mipi_data ? mipi_data->init : NULL) < 0) { + printk(BIOS_ERR, "%s: Failed in DSI init\n", __func__); + return -1; + } + + if (panel->post_power_on && panel->post_power_on(&edid) < 0) { + printk(BIOS_ERR, "%s: Failed to post power on bridge\n", __func__); + return -1; + } + } + + name = edid.ascii_string; + if (name[0] == '\0') + name = "unknown name"; + printk(BIOS_INFO, "%s: '%s %s' %dx%d@%dHz\n", __func__, + edid.manufacturer_name, name, edid.mode.ha, edid.mode.va, + edid.mode.refresh); + + edid_set_framebuffer_bits_per_pixel(&edid, 32, 0); + + mtk_ddp_mode_set(&edid, panel->disp_path); + info = fb_new_framebuffer_info_from_edid(&edid, (uintptr_t)0); + if (info) + fb_set_orientation(info, panel->orientation); + + return 0; +} diff --git a/src/soc/mediatek/common/include/soc/display.h b/src/soc/mediatek/common/include/soc/display.h new file mode 100644 index 0000000..61bc21f --- /dev/null +++ b/src/soc/mediatek/common/include/soc/display.h @@ -0,0 +1,32 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef __SOC_MEDIATEK_COMMON_DISPLAY_H__ +#define __SOC_MEDIATEK_COMMON_DISPLAY_H__ + +#include <commonlib/coreboot_tables.h> +#include <mipi/panel.h> + +enum disp_path_sel { + DISP_PATH_NONE = 0, + DISP_PATH_EDP, + DISP_PATH_MIPI, +}; + +struct panel_description { + const char *name; + void (*configure_backlight)(void); + void (*power_on)(void); + int (*get_edid)(struct edid *edid); + int (*post_power_on)(const struct edid *edid); + enum lb_fb_orientation orientation; + enum disp_path_sel disp_path; + bool pwm_ctrl_gpio; +}; + +int mtk_display_init(void); +struct panel_description *get_active_panel(void); + +void mtk_ddp_init(void); +void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel path); + +#endif diff --git a/src/soc/mediatek/mt8188/Makefile.inc b/src/soc/mediatek/mt8188/Makefile.inc index 6a643b0..4731fab 100644 --- a/src/soc/mediatek/mt8188/Makefile.inc +++ b/src/soc/mediatek/mt8188/Makefile.inc @@ -37,6 +37,7 @@ ramstage-y += ../common/ddp.c ddp.c ramstage-y += ../common/devapc.c devapc.c ramstage-y += ../common/dfd.c +ramstage-y += ../common/display.c ramstage-y += ../common/dp/dp_intf.c ../common/dp/dptx.c ../common/dp/dptx_hal.c dp_intf.c ramstage-y += ../common/dpm.c ramstage-$(CONFIG_DPM_FOUR_CHANNEL) += ../common/dpm_4ch.c diff --git a/src/soc/mediatek/mt8188/include/soc/ddp.h b/src/soc/mediatek/mt8188/include/soc/ddp.h index da14a2c..94fdb81 100644 --- a/src/soc/mediatek/mt8188/include/soc/ddp.h +++ b/src/soc/mediatek/mt8188/include/soc/ddp.h @@ -5,6 +5,7 @@ #include <soc/addressmap.h> #include <soc/ddp_common.h> +#include <soc/display.h> #include <types.h> #define MAIN_PATH_OVL_NR 1 @@ -282,13 +283,4 @@ SMI_LARB_PORT_L0_OVL_RDMA0 = 0xF88, }; -enum disp_path_sel { - DISP_PATH_NONE = 0, - DISP_PATH_EDP, - DISP_PATH_MIPI, -}; - -void mtk_ddp_init(void); -void mtk_ddp_mode_set(const struct edid *edid, enum disp_path_sel); - #endif -- To view, visit https://review.coreboot.org/c/coreboot/+/79776?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I403bba8a826de5f3fb2ea96a5403725ff194164f Gerrit-Change-Number: 79776 Gerrit-PatchSet: 6 Gerrit-Owner: Yidi Lin <yidilin(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Hung-Te Lin <hungte(a)chromium.org> Gerrit-Reviewer: Yu-Ping Wu <yupingso(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/amd/glinda: Increase maximum CPU threads to 24
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79509?usp=email ) ( 6 is the latest approved patch-set. No files were changed between the latest approved patch-set and the submitted one. )Change subject: soc/amd/glinda: Increase maximum CPU threads to 24 ...................................................................... soc/amd/glinda: Increase maximum CPU threads to 24 glinda SOC has 24 maximum CPU threads as per PPR documentation(#57254). TEST=Boot logs print the CPU initialization happens for 24 threads. Change-Id: Id48a5c62d6156c046daffd2648aeebeee380bd88 Signed-off-by: Anand Vaikar <a.vaikar2021(a)gmail.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79509 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Felix Held <felix-coreboot(a)felixheld.de> --- M src/soc/amd/glinda/Kconfig M src/soc/amd/glinda/cpu.c 2 files changed, 2 insertions(+), 3 deletions(-) Approvals: Felix Held: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/soc/amd/glinda/Kconfig b/src/soc/amd/glinda/Kconfig index a3b0ea6..50cd88d 100644 --- a/src/soc/amd/glinda/Kconfig +++ b/src/soc/amd/glinda/Kconfig @@ -240,8 +240,7 @@ config MAX_CPUS int - default 8 if SOC_AMD_GLINDA - default 16 + default 24 help Maximum number of threads the platform can have. diff --git a/src/soc/amd/glinda/cpu.c b/src/soc/amd/glinda/cpu.c index 91f6a9f..06e62c5 100644 --- a/src/soc/amd/glinda/cpu.c +++ b/src/soc/amd/glinda/cpu.c @@ -9,7 +9,7 @@ #include <device/device.h> #include <soc/cpu.h> -_Static_assert(CONFIG_MAX_CPUS == 8, "Do not override MAX_CPUS. To reduce the number of " +_Static_assert(CONFIG_MAX_CPUS == 24, "Do not override MAX_CPUS. To reduce the number of " "available cores, use the downcore_mode and disable_smt devicetree settings instead."); static void zen_2_3_init(struct device *dev) -- To view, visit https://review.coreboot.org/c/coreboot/+/79509?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Id48a5c62d6156c046daffd2648aeebeee380bd88 Gerrit-Change-Number: 79509 Gerrit-PatchSet: 9 Gerrit-Owner: Anand Vaikar <a.vaikar2021(a)gmail.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ritul guru <ritul.bits(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: mb/intel/mtlrvp: define a new config for Chrome EC
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79824?usp=email ) Change subject: mb/intel/mtlrvp: define a new config for Chrome EC ...................................................................... mb/intel/mtlrvp: define a new config for Chrome EC Introduce new config MTL_CHROME_EC_SHARED_SPI, tailored for Chrome ECs utilizing an external shared SPI flash. BUG=b:289783489 TEST=emerge-rex coreboot chromeos-bootimage is successful Cq-Depend: chrome-internal:6691498 Cq-Depend: chrome-internal:6741356 Change-Id: I462c34c5adaefa37c652de293152243c58bad7c5 Signed-off-by: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79824 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/intel/mtlrvp/Kconfig 1 file changed, 7 insertions(+), 2 deletions(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig index c4478d1..4d59f9b 100644 --- a/src/mainboard/intel/mtlrvp/Kconfig +++ b/src/mainboard/intel/mtlrvp/Kconfig @@ -107,7 +107,8 @@ choice prompt "ON BOARD EC" default MTL_INTEL_EC if BOARD_INTEL_MTLRVP_P - default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP_P_MCHP || BOARD_INTEL_MTLRVP4ES_P_EXT_EC + default MTL_CHROME_EC if BOARD_INTEL_MTLRVP_P_EXT_EC || BOARD_INTEL_MTLRVP4ES_P_EXT_EC + default MTL_CHROME_EC_SHARED_SPI if BOARD_INTEL_MTLRVP_P_MCHP help This option allows you to select the on board EC to use. Select whether the board has Intel EC or/and Chrome EC @@ -115,6 +116,10 @@ config MTL_CHROME_EC bool "Chrome EC with Internal SPI flash" +config MTL_CHROME_EC_SHARED_SPI + bool "Chrome EC with External Shared SPI flash" + select MAINBOARD_USES_IFD_EC_REGION + config MTL_INTEL_EC bool "Intel EC" select EC_ACPI @@ -122,7 +127,7 @@ config VBOOT select VBOOT_LID_SWITCH - select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC + select EC_GOOGLE_CHROMEEC_SWITCHES if MTL_CHROME_EC || MTL_CHROME_EC_SHARED_SPI config UART_FOR_CONSOLE int -- To view, visit https://review.coreboot.org/c/coreboot/+/79824?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I462c34c5adaefa37c652de293152243c58bad7c5 Gerrit-Change-Number: 79824 Gerrit-PatchSet: 5 Gerrit-Owner: Deepti Deshatty <deepti.deshatty(a)intel.com> Gerrit-Reviewer: Balaji Manigandan <balaji.manigandan(a)intel.com> Gerrit-Reviewer: Deepti Deshatty <deepti.deshatty(a)intel.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Krishna P Bhat D <krishna.p.bhat.d(a)intel.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Vijay P Hiremath <vijay.p.hiremath(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: merged

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