coreboot-gerrit January 2024

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[M] Change in coreboot[main]: sb/intel/common: Get memory map from SPI controller
by Arthur Heymans (Code Review) 10 Jan '24

10 Jan '24

Arthur Heymans has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/79880?usp=email ) Change subject: sb/intel/common: Get memory map from SPI controller ...................................................................... sb/intel/common: Get memory map from SPI controller Instead of always assuming that the top of a flash matches the top of 4G use the real memory map that's configured in the IFD and is reflected in the SPI registers. One possible use case is to cleanly generate images for some hacks rather than having to apply some 'dd' trickery: e.g. on HP Sure Start a part of the flash is checked by EC. UNTESTED. This might break some hacks people use to work around SPI locked images by modifying the IFD when booted with a recovery strap pulled. Those would also need a specifically crafted FMAP. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 --- M src/southbridge/intel/common/Kconfig.common M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/rcba.h A src/southbridge/intel/common/spi_memmap.c 4 files changed, 86 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/79880/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 Gerrit-Change-Number: 79880 Gerrit-PatchSet: 2 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/acpi: use common AMD MADT code
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Matt DeVillier. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79885?usp=email ) Change subject: soc/amd/stoneyridge/acpi: use common AMD MADT code ...................................................................... Patch Set 4: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79885/comment/31866ccb_c334d435 : PS1, Line 13: TEST=TODO > still need to test this one, but expect it to work Done -- To view, visit https://review.coreboot.org/c/coreboot/+/79885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4ce71a47827e144c4d4991152101650904901f2 Gerrit-Change-Number: 79885 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Comment-Date: Wed, 10 Jan 2024 19:55:42 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/amd/stoneyridge/acpi: use common AMD MADT code
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Matt DeVillier. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79885?usp=email to look at the new patch set (#4). Change subject: soc/amd/stoneyridge/acpi: use common AMD MADT code ...................................................................... soc/amd/stoneyridge/acpi: use common AMD MADT code Now that Stoneyridge also reports the GNB IOAPIC on the domain and with the IOMMU_IOAPIC_IDX resource index the common AMD MADT code expects, we ca switch over to using this common code on Stoneyridge too. TEST=The resulting MADT doesn't change on Careena Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: If4ce71a47827e144c4d4991152101650904901f2 --- M src/soc/amd/stoneyridge/Kconfig M src/soc/amd/stoneyridge/acpi.c 2 files changed, 1 insertion(+), 7 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/85/79885/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79885?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If4ce71a47827e144c4d4991152101650904901f2 Gerrit-Change-Number: 79885 Gerrit-PatchSet: 4 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/hp/elitebook_820_g2: Add HP Sure Start workaround
by Arthur Heymans (Code Review) 10 Jan '24

10 Jan '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79881?usp=email ) Change subject: mb/hp/elitebook_820_g2: Add HP Sure Start workaround ...................................................................... mb/hp/elitebook_820_g2: Add HP Sure Start workaround To work around HP Sure Start the top of flash needs to contain a vendor provided image that the EC verifies before releasing the X86 from reset. Instead of using the wrong flash size and padding the image with dd, add an fmap layout and use cbfstool memory map arguments to achieve the same. UNTESTED. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I0e59d035ce9281062272aeef92f50f2bbf3a9c5f --- M Documentation/mainboard/hp/elitebook_820_g2.md M src/mainboard/hp/elitebook_820_g2/Kconfig M src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/board.fmd 4 files changed, 42 insertions(+), 5 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/79881/1 diff --git a/Documentation/mainboard/hp/elitebook_820_g2.md b/Documentation/mainboard/hp/elitebook_820_g2.md index 5d35c30..d136f4d 100644 --- a/Documentation/mainboard/hp/elitebook_820_g2.md +++ b/Documentation/mainboard/hp/elitebook_820_g2.md @@ -74,13 +74,12 @@ flashrom -p <programmer> --ifd -i fd -w factory-sys.rom.new -Then flash the coreboot image: +Then flash the coreboot image, while making sure CONFIG_HP_SURE_START_WORKAROUND_LAYOUT is set: - # first extend the 12M coreboot.rom to 16M - fallocate -l 16M build/coreboot.rom flashrom -p <programmer> --ifd -i bios -w build/coreboot.rom -After coreboot is installed, the coreboot firmware can be updated with internal flashing: +After coreboot is installed, the coreboot firmware can be updated with internal flashing by +by only flashing the BIOS region: flashrom -p internal --ifd -i bios --noverify-all -w build/coreboot.rom diff --git a/src/mainboard/hp/elitebook_820_g2/Kconfig b/src/mainboard/hp/elitebook_820_g2/Kconfig index 98aed5c..0bfec31 100644 --- a/src/mainboard/hp/elitebook_820_g2/Kconfig +++ b/src/mainboard/hp/elitebook_820_g2/Kconfig @@ -4,7 +4,7 @@ config BOARD_SPECIFIC_OPTIONS def_bool y - select BOARD_ROMSIZE_KB_12288 + select BOARD_ROMSIZE_KB_16384 select EC_HP_KBC1126 select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES @@ -28,4 +28,16 @@ config EC_HP_KBC1126_GPE default 0x6 +config HP_SURE_START_WORKAROUND_LAYOUT + bool "Use a FMAP designed to work around HP Sure Start" + default y + help + HP Sure start verifies the content of the flash against a signature. + If a modified IFD is used to put coreboot in a different location in + the flash the EC still hapilly verifies the vendor bootblock located + at the end of flash but executes a coreboot bootblock. + +config FMDFILE + default "src/mainboard/\$(CONFIG_MAINBOARD_DIR)/board.fmd" if HP_SURE_START_WORKAROUND_LAYOUT + endif diff --git a/src/mainboard/hp/elitebook_820_g2/Makefile.inc b/src/mainboard/hp/elitebook_820_g2/Makefile.inc index 774dbf1..105bb8d 100644 --- a/src/mainboard/hp/elitebook_820_g2/Makefile.inc +++ b/src/mainboard/hp/elitebook_820_g2/Makefile.inc @@ -4,3 +4,13 @@ romstage-y += pei_data.c ramstage-$(CONFIG_MAINBOARD_USE_LIBGFXINIT) += gma-mainboard.ads ramstage-y += pei_data.c + + +ifeq ($(CONFIG_HP_SURE_START_WORKAROUND_LAYOUT),y) +# Match this with board.fmd +BIOS_REGION_FLASH_BASE=0x600000 +BIOS_REGION_SIZE=0x600000 +BIOS_REGION_MMAP_BASE=$(call int-subtract, 0x100000000 $(BIOS_REGION_SIZE)) + +CBFSTOOL_ADD_CMD_OPTIONS += --mmap $(BIOS_REGION_FLASH_BASE):$(BIOS_REGION_MMAP_BASE):$(BIOS_REGION_SIZE) +endif diff --git a/src/mainboard/hp/elitebook_820_g2/board.fmd b/src/mainboard/hp/elitebook_820_g2/board.fmd new file mode 100644 index 0000000..86d66be --- /dev/null +++ b/src/mainboard/hp/elitebook_820_g2/board.fmd @@ -0,0 +1,16 @@ +FLASH 0x1000000 { + SI_ALL@0x0 0x600000 { + SI_DESC 0x1000 + SI_GBE 0x2000 + SI_ME + } + SI_BIOS@0x600000 0x600000 { + UNIFIED_MRC_CACHE 0x20000 { + RECOVERY_MRC_CACHE 0x10000 + RW_MRC_CACHE 0x10000 + } + FMAP 0x800 + COREBOOT(CBFS) + } + SI_PD@0xEB5000 0x14B000 +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e59d035ce9281062272aeef92f50f2bbf3a9c5f Gerrit-Change-Number: 79881 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: sb/intel/common: Get memory map from SPI controller
by Arthur Heymans (Code Review) 10 Jan '24

10 Jan '24

Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79880?usp=email ) Change subject: sb/intel/common: Get memory map from SPI controller ...................................................................... sb/intel/common: Get memory map from SPI controller Instead of always assuming that the top of a flash matches the top of 4G use the real memory map that's configured in the IFD and is reflected in the SPI registers. One possible use case is to cleanly generate images for some hacks rather than having to apply some 'dd' trickery: e.g. on HP Sure Start a part of the flash is checked by EC. UNTESTED. This might break some hacks people use to work around SPI locked images by modifying the IFD when booted with a recovery strap pulled. Those would also need a specifically crafted FMAP. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 --- M src/southbridge/intel/common/Kconfig.common M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/rcba.h A src/southbridge/intel/common/spi_memmap.c 4 files changed, 86 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/79880/1 diff --git a/src/southbridge/intel/common/Kconfig.common b/src/southbridge/intel/common/Kconfig.common index e138f5e..ede5c06 100644 --- a/src/southbridge/intel/common/Kconfig.common +++ b/src/southbridge/intel/common/Kconfig.common @@ -33,6 +33,12 @@ select SPI_FLASH select BOOT_DEVICE_SUPPORTS_WRITES +config SOUTHBRIDGE_INTEL_COMMON_SPI_IFD_MMAP + def_bool y + depends on SOUTHBRIDGE_INTEL_COMMON_SPI && (!SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 || !SOUTHBRIDGE_INTEL_COMMON_SPI_SILVERMONT) + select SPI_FLASH + select X86_CUSTOM_BOOTMEDIA + config SOUTHBRIDGE_INTEL_COMMON_SPI_ICH7 def_bool n select SOUTHBRIDGE_INTEL_COMMON_SPI diff --git a/src/southbridge/intel/common/Makefile.inc b/src/southbridge/intel/common/Makefile.inc index 2f4c777..2ad042d 100644 --- a/src/southbridge/intel/common/Makefile.inc +++ b/src/southbridge/intel/common/Makefile.inc @@ -53,3 +53,6 @@ smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_FINALIZE) += finalize.c all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_RTC) += rtc.c + +all-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_IFD_MMAP) += spi_memmap.c +smm-$(CONFIG_SOUTHBRIDGE_INTEL_COMMON_SPI_IFD_MMAP) += spi_memmap.c diff --git a/src/southbridge/intel/common/rcba.h b/src/southbridge/intel/common/rcba.h index 4a9847a..e079c43 100644 --- a/src/southbridge/intel/common/rcba.h +++ b/src/southbridge/intel/common/rcba.h @@ -9,6 +9,9 @@ #define RCBA 0xf0 #define RCBA_ENABLE 0x01 +/* RCBA registers */ +#define RCBA_GCS 0x4310 + #define RCBA8(x) (*((volatile u8 *)(DEFAULT_RCBA + (x)))) #define RCBA16(x) (*((volatile u16 *)(DEFAULT_RCBA + (x)))) #define RCBA32(x) (*((volatile u32 *)(DEFAULT_RCBA + (x)))) diff --git a/src/southbridge/intel/common/spi_memmap.c b/src/southbridge/intel/common/spi_memmap.c new file mode 100644 index 0000000..e29df27 --- /dev/null +++ b/src/southbridge/intel/common/spi_memmap.c @@ -0,0 +1,74 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#include <assert.h> +#include <boot_device.h> +#include <device/device.h> +#include <fmap_config.h> +#include <southbridge/intel/common/rcba.h> +#include <spi_flash.h> + +/* + * The ROM is memory mapped just below 4GiB. Form a pointer for the base. + * At most 16MB is mapped. + */ +#define rom_base ((void *)(uintptr_t)(0x100000000ULL-MIN(CONFIG_ROM_SIZE, 16 * MiB))) + +#define SPIBAR_BASE 0x3800 +#define BFPR 0x0 + +union bfpr { + uint32_t raw; + struct { + uint32_t prb : 13; + uint32_t _reserved : 3; + uint32_t prl : 13; + uint32_t _reserved2: 3; + }; +}; + +static uint32_t bios_flash_base; +static uint32_t bios_size; + +static void ich_boot_device_init(struct mem_region_device *boot_dev) +{ + const uint32_t gcs = RCBA32(RCBA_GCS); + + const bool spi_boot = ((gcs >> 10) & 3) == 3; + if (!spi_boot) + return; + + const union bfpr bfpr = { .raw = RCBA32(SPIBAR_BASE + BFPR) }; + bios_flash_base = bfpr.prb << 12; + + const uint32_t bios_flash_limit = (bfpr.prl << 12) + 0xfff; + bios_size = bios_flash_limit + 1 - bios_flash_base; + /* Do some basic validation of FMAP */ + assert(FMAP_SECTION_COREBOOT_START - FMAP_SECTION_FLASH_START + + FMAP_SECTION_COREBOOT_SIZE == bios_flash_limit + 1); + + struct mem_region_device spi_boot_dev = MEM_REGION_DEV_RO_INIT(UINT32_MAX - bios_size, + bios_size); + *boot_dev = spi_boot_dev; +} + +const struct region_device *boot_device_ro(void) +{ + /* Somehow cbfstool segfaults if this variable is in .data rather than .bss */ + static struct mem_region_device boot_dev; + /* Assume a default mapping based on ROM size only. */ + struct mem_region_device default_boot_dev = MEM_REGION_DEV_RO_INIT(rom_base, CONFIG_ROM_SIZE); + boot_dev = default_boot_dev; + + ich_boot_device_init(&boot_dev); + + return &boot_dev.rdev; +} + +uint32_t spi_flash_get_mmap_windows(struct flash_mmap_window *table) +{ + table->flash_base = bios_flash_base; + table->host_base = (uint32_t)(uintptr_t)UINT32_MAX - bios_size + 1; + table->size = CONFIG_ROM_SIZE; + + return 1; +} -- To view, visit https://review.coreboot.org/c/coreboot/+/79880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 Gerrit-Change-Number: 79880 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: mb/ibm/sbp1: Enable 2 PCI segments
by Patrick Rudolph (Code Review) 10 Jan '24

10 Jan '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79879?usp=email ) Change subject: mb/ibm/sbp1: Enable 2 PCI segments ...................................................................... mb/ibm/sbp1: Enable 2 PCI segments Untested. Change-Id: Ifd2f8b920d9901cbb8ee2fe7a2911af98ce8e20f Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/mainboard/ibm/sbp1/Kconfig M src/mainboard/ibm/sbp1/romstage.c 2 files changed, 5 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/79/79879/1 diff --git a/src/mainboard/ibm/sbp1/Kconfig b/src/mainboard/ibm/sbp1/Kconfig index 8d8b62e..6a5bc64 100644 --- a/src/mainboard/ibm/sbp1/Kconfig +++ b/src/mainboard/ibm/sbp1/Kconfig @@ -31,4 +31,7 @@ int default 480 +config ECAM_SEGMENT_COUNT + default 2 + endif diff --git a/src/mainboard/ibm/sbp1/romstage.c b/src/mainboard/ibm/sbp1/romstage.c index f5b081b..5f1e374 100644 --- a/src/mainboard/ibm/sbp1/romstage.c +++ b/src/mainboard/ibm/sbp1/romstage.c @@ -282,8 +282,8 @@ /* Set FSP debug message to Disable */ mupd->FspmConfig.serialDebugMsgLvl = 0x0; - /* Force 256MiB MMCONF (Segment0) only */ - mupd->FspmConfig.mmCfgSize = 0x2; + /* Force 512MiB MMCONF (Segment0 + Segment1) */ + mupd->FspmConfig.mmCfgSize = 0x3; mupd->FspmConfig.PcieHotPlugEnable = 1; /* -- To view, visit https://review.coreboot.org/c/coreboot/+/79879?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifd2f8b920d9901cbb8ee2fe7a2911af98ce8e20f Gerrit-Change-Number: 79879 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: soc/intel/xeon_sp: Support multiple PCI segments
by Patrick Rudolph (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Arthur Heymans, Christian Walter, Johnny Lin, Tim Chu. Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79878?usp=email ) Change subject: soc/intel/xeon_sp: Support multiple PCI segments ...................................................................... soc/intel/xeon_sp: Support multiple PCI segments Untested. Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/chip.c M src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h M src/soc/intel/xeon_sp/skx/include/soc/soc_util.h M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl M src/soc/intel/xeon_sp/spr/chip.c M src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h M src/soc/intel/xeon_sp/spr/include/soc/soc_util.h M src/soc/intel/xeon_sp/spr/ioat.c M src/soc/intel/xeon_sp/spr/soc_acpi.c M src/soc/intel/xeon_sp/spr/soc_smihandler_util.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/uncore_acpi.c M src/soc/intel/xeon_sp/util.c 20 files changed, 165 insertions(+), 70 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/78/79878/1 diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index c1b331b..8a5e98d 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -20,6 +20,16 @@ return &hob->PlatformData.IIO_resource[dn / MAX_LOGIC_IIO_STACK].StackRes[dn % MAX_LOGIC_IIO_STACK]; } +static int domain_to_pcie_segment(const struct device *dev) +{ + assert(dev->path.type == DEVICE_PATH_DOMAIN); + const unsigned int dn = dev->path.domain.domain; + + const IIO_UDS *hob = get_iio_uds(); + assert(hob != NULL); + return hob->PlatformData.CpuQpiInfo[dn / MAX_LOGIC_IIO_STACK].PcieSegment; +} + void iio_pci_domain_read_resources(struct device *dev) { struct resource *res; @@ -67,6 +77,7 @@ void iio_pci_domain_scan_bus(struct device *dev) { const STACK_RES *sr = domain_to_stack_res(dev); + const int seg = domain_to_pcie_segment(dev); if (!sr) return; @@ -80,9 +91,10 @@ bus->secondary = sr->BusBase; bus->subordinate = sr->BusBase; bus->max_subordinate = sr->BusLimit; + bus->segment = seg; - printk(BIOS_SPEW, "Scanning IIO stack %d: busses %x-%x\n", dev->path.domain.domain, - dev->link_list->secondary, dev->link_list->max_subordinate); + printk(BIOS_SPEW, "Scanning IIO stack %d: segment %x, busses %x-%x\n", dev->path.domain.domain, + dev->link_list->segment, dev->link_list->secondary, dev->link_list->max_subordinate); pci_host_bridge_scan_bus(dev); } diff --git a/src/soc/intel/xeon_sp/cpx/chip.c b/src/soc/intel/xeon_sp/cpx/chip.c index 39a7eba..1989f3d 100644 --- a/src/soc/intel/xeon_sp/cpx/chip.c +++ b/src/soc/intel/xeon_sp/cpx/chip.c @@ -71,6 +71,7 @@ static void iio_write_mask(u16 bus, u16 dev, u8 func) { + /* FIXME: Add segment support */ pci_devfn_t device = PCI_DEV(bus, dev, func); u32 val = pci_s_read_config32(device, IIO_XPUNCCERRMSK_REG); val |= (SENT_PCIE_UNSUPP_MASK | RCVD_PCIE_CA_STS_MASK | RCVD_PCIE_UR_STS_MASK); @@ -119,25 +120,26 @@ if (!soc_cpu_is_enabled(socket)) continue; uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + uint8_t seg = get_socket_pci_segment(socket); /* configure PCU_CR0_FUN csrs */ - const struct device *cr0_dev = PCU_DEV_CR0(bus); + const struct device *cr0_dev = PCU_DEV_CR0(seg, bus); pci_or_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); pci_or_config32(cr0_dev, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR); pci_or_config32(cr0_dev, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK); /* configure PCU_CR1_FUN csrs */ - const struct device *cr1_dev = PCU_DEV_CR1(bus); + const struct device *cr1_dev = PCU_DEV_CR1(seg, bus); pci_or_config32(cr1_dev, PCU_CR1_SAPMCTL, SAPMCTL_LOCK_MASK); /* configure PCU_CR2_FUN csrs */ - const struct device *cr2_dev = PCU_DEV_CR2(bus); + const struct device *cr2_dev = PCU_DEV_CR2(seg, bus); pci_or_config32(cr2_dev, PCU_CR2_DRAM_PLANE_POWER_LIMIT, PP_PWR_LIM_LOCK); pci_or_config32(cr2_dev, PCU_CR2_DRAM_POWER_INFO_UPR, DRAM_POWER_INFO_LOCK_UPR); /* configure PCU_CR3_FUN csrs */ - const struct device *cr3_dev = PCU_DEV_CR3(bus); + const struct device *cr3_dev = PCU_DEV_CR3(seg, bus); pci_or_config32(cr3_dev, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); pci_or_config32(cr3_dev, PCU_CR3_FLEX_RATIO, OC_LOCK); } diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h index 55268a7..46678ae 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/pci_devs.h @@ -15,16 +15,16 @@ #define SAD_ALL_PAM456_CSR 0x44 #if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) +#define _PCU_DEV(seg, bus, func) pcidev_path_on_segbus((seg), (bus), PCI_DEVFN(PCU_DEV, func)) #else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) +#define _PCU_DEV(seg, bus, func) PCI_DEV(((seg) << 8) | (bus), PCU_DEV, func) #endif #define PCU_IIO_STACK 1 #define PCU_DEV 30 #define PCU_CR0_FUN 0 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) +#define PCU_DEV_CR0(seg, bus) _PCU_DEV(seg, bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 #define TURBO_ACTIVATION_RATIO_LOCK BIT(31) @@ -37,7 +37,7 @@ #define PMAX_LOCK BIT(31) #define PCU_CR1_FUN 1 -#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) +#define PCU_DEV_CR1(seg, bus) _PCU_DEV(seg, bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c #define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 @@ -64,7 +64,7 @@ #define SAPMCTL_LOCK_MASK BIT(31) #define PCU_CR2_FUN 2 -#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) +#define PCU_DEV_CR2(seg, bus) _PCU_DEV(seg, bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) #define DRAM_POWER_INFO_LOCK_UPR BIT(31) @@ -72,7 +72,7 @@ #define PP_PWR_LIM_LOCK BIT(31) #define PCU_CR3_FUN 3 -#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) +#define PCU_DEV_CR3(seg, bus) _PCU_DEV(seg, bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0x60 #define TDP_LOCK BIT(31) #define PCU_CR3_FLEX_RATIO 0xa0 @@ -142,9 +142,9 @@ #define VTD_FUNC_NUM 0x0 #if !defined(__SIMPLE_DEVICE__) -#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) +#define VTD_DEV(seg, bus) pcidev_path_on_segbus((seg), (bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) #else -#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) +#define VTD_DEV(seg, bus) PCI_DEV(((seg) << 8) | (bus), VTD_DEV_NUM, VTD_FUNC_NUM) #endif #define APIC_DEV_NUM 0x05 diff --git a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h index 91919b8..ec4cf54 100644 --- a/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/cpx/include/soc/soc_util.h @@ -26,6 +26,7 @@ uint8_t get_stack_busno(const uint8_t stack); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); +uint8_t get_socket_pci_segment(uint32_t socket); uint32_t get_socket_ubox_busno(uint32_t socket); uint8_t get_cxl_node_count(void); diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index e277752..30eab8b 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -41,7 +41,8 @@ printk(BIOS_ERR, "%s: Stack %u does not exist!\n", __func__, stack); return 0; } - const pci_devfn_t dev = PCI_DEV(UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC); + const uint8_t seg = get_socket_pci_segment(0); + const pci_devfn_t dev = PCI_DEV((seg << 8) | UBOX_DECS_BUS, UBOX_DECS_DEV, UBOX_DECS_FUNC); const uint16_t offset = stack / 4 ? UBOX_DECS_CPUBUSNO1_CSR : UBOX_DECS_CPUBUSNO_CSR; return pci_io_read_config32(dev, offset) >> (8 * (stack % 4)) & 0xff; } @@ -55,6 +56,19 @@ return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; } +uint8_t get_socket_pci_segment(uint32_t socket) +{ + const IIO_UDS *hob = get_iio_uds(); + uint8_t seg; + + assert(socket < MAX_SOCKET); + + seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + assert(seg < CONFIG_ECAM_SEGMENT_COUNT); + + return seg; +} + uint32_t get_socket_ubox_busno(uint32_t socket) { if (socket == 0) diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index e73143f..c35b5ab 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -12,8 +12,8 @@ void smm_region(uintptr_t *start, size_t *size) { - uintptr_t tseg_base = pci_read_config32(VTD_DEV(0), VTD_TSEG_BASE_CSR); - uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0), VTD_TSEG_LIMIT_CSR); + uintptr_t tseg_base = pci_read_config32(VTD_DEV(0, 0), VTD_TSEG_BASE_CSR); + uintptr_t tseg_limit = pci_read_config32(VTD_DEV(0, 0), VTD_TSEG_LIMIT_CSR); tseg_base = ALIGN_DOWN(tseg_base, 1 * MiB); tseg_limit = ALIGN_DOWN(tseg_limit, 1 * MiB); @@ -55,7 +55,7 @@ { const IIO_UDS *hob = get_iio_uds(); union dpr_register dpr; - struct device *dev = VTD_DEV(0); + struct device *dev = VTD_DEV(0, 0); dpr.raw = 0; @@ -77,7 +77,8 @@ if (!stack_needs_resource_alloc(ri)) continue; uint8_t bus = ri->BusBase; - dev = VTD_DEV(bus); + uint8_t segment = get_socket_pci_segment(socket); + dev = VTD_DEV(segment, bus); if (!dev) { printk(BIOS_ERR, "BUS %x: Unable to find VTD PCI dev\n", bus); diff --git a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h index 3d518fa..a4f65ab 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/pci_devs.h @@ -28,9 +28,9 @@ #define SAD_ALL_PAM456_CSR 0x44 #if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) +#define _PCU_DEV(seg, bus, func) pcidev_path_on_segbus((seg), (bus), PCI_DEVFN(PCU_DEV, func)) #else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) +#define _PCU_DEV(seg, bus, func) PCI_DEV(((seg) << 8) | (bus), PCU_DEV, func) #endif #define PCU_IIO_STACK 1 @@ -38,7 +38,7 @@ #define PCU_CR1_FUN 1 #define PCU_CR0_FUN 0 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) +#define PCU_DEV_CR0(seg, bus) _PCU_DEV(seg, bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_P_STATE_LIMITS 0xd8 #define P_STATE_LIMITS_LOCK_SHIFT 31 @@ -140,9 +140,9 @@ #define VTD_FUNC_NUM 0x0 #if !defined(__SIMPLE_DEVICE__) -#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) +#define VTD_DEV(seg, bus) pcidev_path_on_segbus((seg), (bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) #else -#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) +#define VTD_DEV(seg, bus) PCI_DEV(((seg) << 8) | (bus), VTD_DEV_NUM, VTD_FUNC_NUM) #endif #define CBDMA_DEV_NUM 0x04 diff --git a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h index 379cdc8..489ad18 100644 --- a/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/skx/include/soc/soc_util.h @@ -12,6 +12,7 @@ uint8_t get_stack_busno(const uint8_t stack); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); +uint8_t get_socket_pci_segment(uint32_t socket); uint32_t get_socket_ubox_busno(uint32_t socket); int soc_get_stack_for_port(int port); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index d61d074..74cb7f7 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -85,6 +85,19 @@ return hob->PlatformData.CpuQpiInfo[socket].StackBus[stack]; } +uint8_t get_socket_pci_segment(uint32_t socket) +{ + const IIO_UDS *hob = get_iio_uds(); + uint8_t seg; + + assert(socket < MAX_SOCKET); + + seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + assert(seg < CONFIG_ECAM_SEGMENT_COUNT); + + return seg; +} + uint32_t get_socket_ubox_busno(uint32_t socket) { if (socket == 0) @@ -99,9 +112,10 @@ for (uint32_t socket = 0; socket < MAX_SOCKET; ++socket) { uint32_t bus = get_socket_stack_busno(socket, PCU_IIO_STACK); + uint8_t seg = get_socket_pci_segment(socket); /* configure PCU_CR0_FUN csrs */ - pci_devfn_t cr0_dev = PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN); + pci_devfn_t cr0_dev = PCI_DEV((seg << 8) | bus, PCU_DEV, PCU_CR0_FUN); data = pci_s_read_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS); data |= P_STATE_LIMITS_LOCK; pci_s_write_config32(cr0_dev, PCU_CR0_P_STATE_LIMITS, data); @@ -115,7 +129,7 @@ plat_info, max_min_turbo_limit_ratio); /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr1_dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + pci_devfn_t cr1_dev = PCI_DEV((seg << 8) | bus, PCU_DEV, PCU_CR1_FUN); data = pci_s_read_config32(cr1_dev, PCU_CR1_SAPMCTL); /* clear bits 27:31 - FSP sets this with 0x7 which needs to be cleared */ @@ -124,7 +138,7 @@ pci_s_write_config32(cr1_dev, PCU_CR1_SAPMCTL, data); /* configure PCU_CR1_FUN csrs */ - pci_devfn_t cr2_dev = PCI_DEV(bus, PCU_DEV, PCU_CR2_FUN); + pci_devfn_t cr2_dev = PCI_DEV((seg << 8) | bus, PCU_DEV, PCU_CR2_FUN); data = PCIE_IN_PKGCSTATE_L1_MASK; pci_s_write_config32(cr2_dev, PCU_CR2_PKG_CST_ENTRY_CRITERIA_MASK, data); diff --git a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl index 3644e87..4e34d8e 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl @@ -8,6 +8,9 @@ #define _IIO_DEVICE_UID(str, skt, stk) STR(str##skt##stk) #define IIO_DEVICE_UID(str, skt, stk) _IIO_DEVICE_UID(str, skt, stk) +#define _SEG_NAME(str, skt) str##skt +#define SEG_NAME(str, skt) _SEG_NAME(str, skt) + Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET, STACK)) { Name (_HID, "ACPI0017") /* CXL */ @@ -18,6 +21,10 @@ }) Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) External (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) + + External (\_SB.SEG_NAME(SEG, SOCKET)) + Name (_SEG, \_SB.SEG_NAME(SEG, SOCKET)) + Method (_STA, 0, NotSerialized) // _STA: Status { Return (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) diff --git a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl index a369b11..945632b 100644 --- a/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl +++ b/src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl @@ -8,11 +8,18 @@ #define _IIO_DEVICE_UID(str, skt, stk) STR(str##skt##stk) #define IIO_DEVICE_UID(str, skt, stk) _IIO_DEVICE_UID(str, skt, stk) +#define _SEG_NAME(str, skt) str##skt +#define SEG_NAME(str, skt) _SEG_NAME(str, skt) + Device (IIO_DEVICE_NAME(DEVPREFIX, SOCKET, STACK)) { Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) Name (_UID, IIO_DEVICE_UID(DEVPREFIX, SOCKET, STACK)) + + External (\_SB.SEG_NAME(SEG, SOCKET)) + Name (_SEG, \_SB.SEG_NAME(SEG, SOCKET)) + External (\_SB.IIO_DEVICE_NAME(STPREFIX, SOCKET, STACK)) Method (_STA, 0, NotSerialized) { diff --git a/src/soc/intel/xeon_sp/spr/chip.c b/src/soc/intel/xeon_sp/spr/chip.c index 3b3c65e..add6cd3 100644 --- a/src/soc/intel/xeon_sp/spr/chip.c +++ b/src/soc/intel/xeon_sp/spr/chip.c @@ -80,10 +80,10 @@ } } -static void pcu_pci_or_config32(u8 bus, u8 func, u32 reg, u32 orval) +static void pcu_pci_or_config32(u8 seg, u8 bus, u8 func, u32 reg, u32 orval) { u32 data; - const uint32_t pcie_offset = PCI_DEV(bus, PCU_DEV, func); + const uint32_t pcie_offset = PCI_DEV((seg << 8) | bus, PCU_DEV, func); data = pci_s_read_config32(pcie_offset, reg); data |= orval; @@ -96,28 +96,29 @@ if (!soc_cpu_is_enabled(socket)) continue; const uint32_t bus = get_ubox_busno(socket, UNCORE_BUS_1); + const uint8_t seg = get_socket_pci_segment(socket); /* configure PCU_CR0_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_P_STATE_LIMITS, + pcu_pci_or_config32(seg, bus, PCU_CR0_FUN, PCU_CR0_P_STATE_LIMITS, P_STATE_LIMITS_LOCK); - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, + pcu_pci_or_config32(seg, bus, PCU_CR0_FUN, PCU_CR0_PACKAGE_RAPL_LIMIT_UPR, PKG_PWR_LIM_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR0_FUN, PCU_CR0_TURBO_ACTIVATION_RATIO, + pcu_pci_or_config32(seg, bus, PCU_CR0_FUN, PCU_CR0_TURBO_ACTIVATION_RATIO, TURBO_ACTIVATION_RATIO_LOCK); /* configure PCU_CR2_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_POWER_INFO_UPR, + pcu_pci_or_config32(seg, bus, PCU_CR2_FUN, PCU_CR2_DRAM_POWER_INFO_UPR, DRAM_POWER_INFO_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR2_FUN, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, + pcu_pci_or_config32(seg, bus, PCU_CR2_FUN, PCU_CR2_DRAM_PLANE_POWER_LIMIT_UPR, PP_PWR_LIM_LOCK_UPR); /* configure PCU_CR3_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR3_FUN, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); + pcu_pci_or_config32(seg, bus, PCU_CR3_FUN, PCU_CR3_CONFIG_TDP_CONTROL, TDP_LOCK); /* configure PCU_CR6_FUN csrs */ - pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, + pcu_pci_or_config32(seg, bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR, PLT_PWR_LIM_LOCK_UPR); - pcu_pci_or_config32(bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, + pcu_pci_or_config32(seg, bus, PCU_CR6_FUN, PCU_CR6_PLATFORM_POWER_INFO_CFG_UPR, PLT_PWR_INFO_LOCK_UPR); } } diff --git a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h index 06ec16c..5219298 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/pci_devs.h @@ -38,9 +38,9 @@ #define SAD_ALL_PAM456_CSR 0x84 #if !defined(__SIMPLE_DEVICE__) -#define _PCU_DEV(bus, func) pcidev_path_on_bus(bus, PCI_DEVFN(PCU_DEV, func)) +#define _PCU_DEV(seg, bus, func) pcidev_path_on_segbus((seg), (bus), PCI_DEVFN(PCU_DEV, func)) #else -#define _PCU_DEV(bus, func) PCI_DEV(bus, PCU_DEV, func) +#define _PCU_DEV(seg, bus, func) PCI_DEV(((seg) << 8) | (bus), PCU_DEV, func) #endif /* PCU [B:31, D:30, F:0->F:6] */ @@ -48,7 +48,7 @@ #define PCU_DEV 30 #define PCU_CR0_FUN 0 -#define PCU_DEV_CR0(bus) _PCU_DEV(bus, PCU_CR0_FUN) +#define PCU_DEV_CR0(seg, bus) _PCU_DEV(seg, bus, PCU_CR0_FUN) #define PCU_CR0_PLATFORM_INFO 0xa8 #define PCU_CR0_TURBO_ACTIVATION_RATIO 0xb0 #define TURBO_ACTIVATION_RATIO_LOCK BIT(31) @@ -63,7 +63,7 @@ #define VR_CURRENT_CONFIG_LOCK BIT(31) #define PCU_CR1_FUN 1 -#define PCU_DEV_CR1(bus) _PCU_DEV(bus, PCU_CR1_FUN) +#define PCU_DEV_CR1(seg, bus) _PCU_DEV(seg, bus, PCU_CR1_FUN) #define PCU_CR1_BIOS_MB_DATA_REG 0x8c #define PCU_CR1_BIOS_MB_INTERFACE_REG 0x90 @@ -87,7 +87,7 @@ #define PCU_CR1_DESIRED_CORES_CFG2_REG_LOCK_MASK BIT(31) #define PCU_CR2_FUN 2 -#define PCU_DEV_CR2(bus) _PCU_DEV(bus, PCU_CR2_FUN) +#define PCU_DEV_CR2(seg, bus) _PCU_DEV(seg, bus, PCU_CR2_FUN) #define PCU_CR2_DRAM_POWER_INFO_LWR 0xa8 #define PCU_CR2_DRAM_POWER_INFO_UPR (PCU_CR2_DRAM_POWER_INFO_LWR + 4) #define DRAM_POWER_INFO_LOCK_UPR BIT(31) @@ -99,7 +99,7 @@ #define PCU_CR3_FUN 3 #define PCU_CR3_CAPID4 0x94 #define ERR_SPOOFING_DIS 1 -#define PCU_DEV_CR3(bus) _PCU_DEV(bus, PCU_CR3_FUN) +#define PCU_DEV_CR3(seg, bus) _PCU_DEV(seg, bus, PCU_CR3_FUN) #define PCU_CR3_CONFIG_TDP_CONTROL 0xd8 #define TDP_LOCK BIT(31) #define PCU_CR3_FLEX_RATIO 0xa0 @@ -113,7 +113,7 @@ #define PCU_EMCA_MODE (1 << 2) #define PCU_CR6_FUN 6 -#define PCU_DEV_CR6(bus) _PCU_DEV(bus, PCU_CR6_FUN) +#define PCU_DEV_CR6(seg, bus) _PCU_DEV(seg, bus, PCU_CR6_FUN) #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR 0xa8 #define PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_UPR (PCU_CR6_PLATFORM_RAPL_LIMIT_CFG_LWR + 4) #define PLT_PWR_LIM_LOCK_UPR BIT(31) @@ -148,9 +148,9 @@ #define VTD_FUNC_NUM 0x0 #if !defined(__SIMPLE_DEVICE__) -#define VTD_DEV(bus) pcidev_path_on_bus((bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) +#define VTD_DEV(seg, bus) pcidev_path_on_segbus((seg), (bus), PCI_DEVFN(VTD_DEV_NUM, VTD_FUNC_NUM)) #else -#define VTD_DEV(bus) PCI_DEV((bus), VTD_DEV_NUM, VTD_FUNC_NUM) +#define VTD_DEV(seg, bus) PCI_DEV(((seg) << 8) | (bus), VTD_DEV_NUM, VTD_FUNC_NUM) #endif /* Root port Registers */ diff --git a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h index 997cdb4..6f8ac18 100644 --- a/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h +++ b/src/soc/intel/xeon_sp/spr/include/soc/soc_util.h @@ -32,6 +32,7 @@ const struct SystemMemoryMapElement *get_system_memory_map_elment(uint8_t *num); uint32_t get_socket_stack_busno(uint32_t socket, uint32_t stack); +uint8_t get_socket_pci_segment(uint32_t socket); bool is_iio_cxl_stack_res(const STACK_RES *res); diff --git a/src/soc/intel/xeon_sp/spr/ioat.c b/src/soc/intel/xeon_sp/spr/ioat.c index 8cc22c6..b4a2a7e 100644 --- a/src/soc/intel/xeon_sp/spr/ioat.c +++ b/src/soc/intel/xeon_sp/spr/ioat.c @@ -48,6 +48,7 @@ bus->secondary = bus_base; bus->subordinate = bus->secondary; bus->max_subordinate = bus_limit; + bus->segment = upstream->segment; unsigned int index = 0; diff --git a/src/soc/intel/xeon_sp/spr/soc_acpi.c b/src/soc/intel/xeon_sp/spr/soc_acpi.c index aab6e1f..69d370e 100644 --- a/src/soc/intel/xeon_sp/spr/soc_acpi.c +++ b/src/soc/intel/xeon_sp/spr/soc_acpi.c @@ -338,6 +338,18 @@ acpigen_write_name_integer(stack_sta, ACPI_STATUS_DEVICE_ALL_ON); } +/* + * Add a DSDT ACPI PCI segment. + * This is retrieved by the device _SEG defined in iiostack.asl + */ +static void create_dsdt_seg(uint8_t socket) +{ + char stack_seg[8]; + snprintf(stack_seg, sizeof(stack_seg), "SEG%d", socket); + + acpigen_write_name_integer(stack_seg, get_socket_pci_segment(socket)); +} + void uncore_inject_dsdt(const struct device *device) { bool stack_enabled; @@ -368,6 +380,7 @@ const IIO_UDS *hob = get_iio_uds(); /* Iterate over CONFIG_MAX_SOCKET to keep ASL templates and DSDT injection in sync */ for (uint8_t socket = 0; socket < CONFIG_MAX_SOCKET; ++socket) { + create_dsdt_seg(socket); for (int stack = 0; stack < MAX_LOGIC_IIO_STACK; ++stack) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; diff --git a/src/soc/intel/xeon_sp/spr/soc_smihandler_util.c b/src/soc/intel/xeon_sp/spr/soc_smihandler_util.c index b2700d5..e235cb5 100644 --- a/src/soc/intel/xeon_sp/spr/soc_smihandler_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_smihandler_util.c @@ -15,5 +15,6 @@ else return 0; + /* FIXME: Segment handling? */ return PCI_DEV(bus, UBOX_DECS_DEV, UBOX_URACU_FUNC); } diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index 86fe803..57bd904 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -139,6 +139,19 @@ return hob->PlatformData.IIO_resource[socket].StackRes[stack].BusBase; } +uint8_t get_socket_pci_segment(uint32_t socket) +{ + const IIO_UDS *hob = get_iio_uds(); + uint8_t seg; + + assert(socket < MAX_SOCKET); + + seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + assert(seg < CONFIG_ECAM_SEGMENT_COUNT); + + return seg; +} + uint32_t get_ubox_busno(uint32_t socket, uint8_t offset) { const IIO_UDS *hob = get_iio_uds(); diff --git a/src/soc/intel/xeon_sp/uncore_acpi.c b/src/soc/intel/xeon_sp/uncore_acpi.c index e2b47329..8376d52f 100644 --- a/src/soc/intel/xeon_sp/uncore_acpi.c +++ b/src/soc/intel/xeon_sp/uncore_acpi.c @@ -222,10 +222,10 @@ */ static unsigned long acpi_create_dmar_ds_pci_br_for_port(unsigned long current, const struct device *bridge_dev, - uint32_t pcie_seg, bool is_atsr, bool *first) { - const uint32_t bus = bridge_dev->bus->secondary; + const uint8_t bus = bridge_dev->bus->secondary; + const uint8_t seg = bridge_dev->bus->segment; const uint32_t dev = PCI_SLOT(bridge_dev->path.pci.devfn); const uint32_t func = PCI_FUNC(bridge_dev->path.pci.devfn); @@ -236,14 +236,14 @@ unsigned long pci_br_size = 0; if (is_atsr == true && first && *first == true) { printk(BIOS_DEBUG, "[Root Port ATS Capability] Flags: 0x%x, " - "PCI Segment Number: 0x%x\n", 0, pcie_seg); - atsr_size = acpi_create_dmar_atsr(current, 0, pcie_seg); + "PCI Segment Number: 0x%x\n", 0, seg); + atsr_size = acpi_create_dmar_atsr(current, 0, seg); *first = false; } printk(BIOS_DEBUG, " [PCI Bridge Device] Enumeration ID: 0x%x, " "PCI Bus Number: 0x%x, PCI Path: 0x%x, 0x%x\n", - 0, bus, dev, func); + 0, bus, dev, func); pci_br_size = acpi_create_dmar_ds_pci_br(current + atsr_size, bus, dev, func); return (atsr_size + pci_br_size); @@ -255,7 +255,7 @@ unsigned long tmp = current; const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; const uint32_t bus = ri->BusBase; - const uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + const uint8_t pcie_seg = get_socket_pci_segment(socket); const uint32_t reg_base = ri->VtdBarAddress; printk(BIOS_SPEW, "%s socket: %d, stack: %d, bus: 0x%x, pcie_seg: 0x%x, reg_base: 0x%x\n", __func__, socket, stack, bus, pcie_seg, reg_base); @@ -312,12 +312,12 @@ // Add PCIe Ports if (socket != 0 || stack != IioStack0) { - struct device *dev = pcidev_path_on_bus(bus, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_path_on_segbus(pcie_seg, bus, PCI_DEVFN(0, 0)); while (dev) { if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) current += acpi_create_dmar_ds_pci_br_for_port( - current, dev, pcie_seg, false, NULL); + current, dev, false, NULL); dev = dev->sibling; } @@ -339,7 +339,7 @@ // Add DINO End Points (with memory resources. We don't report every End Point device.) if (ri->Personality == TYPE_DINO) { for (int b = ri->BusBase; b <= ri->BusLimit; ++b) { - struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_path_on_segbus(pcie_seg, b, PCI_DEVFN(0, 0)); while (dev) { /* This may also require a check for IORESOURCE_PREFETCH, * but that would not include the FPU (4942/0) */ @@ -389,7 +389,7 @@ continue; iio++; - uint32_t pcie_seg = hob->PlatformData.CpuQpiInfo[socket].PcieSegment; + const uint8_t pcie_seg = get_socket_pci_segment(socket); unsigned long tmp = current; bool first = true; IIO_RESOURCE_INSTANCE iio_resource = @@ -414,12 +414,12 @@ if (bus == 0) continue; - struct device *dev = pcidev_path_on_bus(bus, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_path_on_segbus(pcie_seg, bus, PCI_DEVFN(0, 0)); while (dev) { if ((dev->hdr_type & 0x7f) == PCI_HEADER_TYPE_BRIDGE) current += acpi_create_dmar_ds_pci_br_for_port( - current, dev, pcie_seg, true, &first); + current, dev, true, &first); dev = dev->sibling; } @@ -490,10 +490,12 @@ /* Skylake-SP doesn't have DINO but not sure how to verify this on CPX */ #if CONFIG(SOC_INTEL_SAPPHIRERAPIDS_SP) || CONFIG(SOC_INTEL_COOPERLAKE_SP) -static unsigned long xeonsp_create_satc_dino(unsigned long current, const STACK_RES *ri) +static unsigned long xeonsp_create_satc_dino(int socket, unsigned long current, const STACK_RES *ri) { + const uint8_t pcie_seg = get_socket_pci_segment(socket); + for (int b = ri->BusBase; b <= ri->BusLimit; ++b) { - struct device *dev = pcidev_path_on_bus(b, PCI_DEVFN(0, 0)); + struct device *dev = pcidev_path_on_segbus(pcie_seg, b, PCI_DEVFN(0, 0)); while (dev) { if (pciexp_find_extended_cap(dev, PCIE_EXT_CAP_ID_ATS, 0)) { const uint32_t d = PCI_SLOT(dev->path.pci.devfn); @@ -525,7 +527,7 @@ const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; // Add the DINO ATS devices to the SATC if (ri->Personality == TYPE_DINO) - current = xeonsp_create_satc_dino(current, ri); + current = xeonsp_create_satc_dino(socket, current, ri); } } diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index c9f4c55..61ff409 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -23,8 +23,9 @@ /* section 16.3.19 of Intel doc. #612246 */ uint32_t pam0123_lock = 0x33333331; uint32_t bus1 = get_socket_ubox_busno(0); + const uint8_t seg = get_socket_pci_segment(0); - pci_s_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + pci_s_write_config32(PCI_DEV((seg << 8) | bus1, SAD_ALL_DEV, SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR, pam0123_lock); } @@ -33,15 +34,16 @@ uint32_t pam0123_unlock_dram = 0x33333330; uint32_t pam456_unlock_dram = 0x00333333; uint32_t bus1 = get_socket_ubox_busno(0); + const uint8_t seg = get_socket_pci_segment(0); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + pci_io_write_config32(PCI_DEV((seg << 8) | bus1, SAD_ALL_DEV, SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR, pam0123_unlock_dram); - pci_io_write_config32(PCI_DEV(bus1, SAD_ALL_DEV, SAD_ALL_FUNC), + pci_io_write_config32(PCI_DEV((seg << 8) | bus1, SAD_ALL_DEV, SAD_ALL_FUNC), SAD_ALL_PAM456_CSR, pam456_unlock_dram); - uint32_t reg1 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + uint32_t reg1 = pci_io_read_config32(PCI_DEV((seg << 8) | bus1, SAD_ALL_DEV, SAD_ALL_FUNC), SAD_ALL_PAM0123_CSR); - uint32_t reg2 = pci_io_read_config32(PCI_DEV(bus1, SAD_ALL_DEV, + uint32_t reg2 = pci_io_read_config32(PCI_DEV((seg << 8) | bus1, SAD_ALL_DEV, SAD_ALL_FUNC), SAD_ALL_PAM456_CSR); printk(BIOS_DEBUG, "%s:%s pam0123_csr: 0x%x, pam456_csr: 0x%x\n", __FILE__, __func__, reg1, reg2); @@ -188,7 +190,8 @@ uint32_t pcode_init_mask, uint32_t val) { const uint32_t bus = get_socket_ubox_busno(socket); - const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + const uint8_t seg = get_socket_pci_segment(socket); + const pci_devfn_t dev = PCI_DEV((seg << 8) | bus, PCU_DEV, PCU_CR1_FUN); uint32_t reg = pci_s_read_config32(dev, PCU_CR1_BIOS_RESET_CPL_REG); reg &= (uint32_t)~rst_cpl_mask; @@ -207,7 +210,8 @@ uint32_t data; bool timedout; const uint32_t bus = get_socket_ubox_busno(socket); - const pci_devfn_t dev = PCI_DEV(bus, PCU_DEV, PCU_CR1_FUN); + const uint8_t seg = get_socket_pci_segment(socket); + const pci_devfn_t dev = PCI_DEV((seg << 8) | bus, PCU_DEV, PCU_CR1_FUN); /* read PCU config */ timedout = write_bios_mailbox_cmd(dev, BIOS_CMD_READ_PCU_MISC_CFG, 0); @@ -233,9 +237,9 @@ die("BIOS RESET CPL3 timed out.\n"); /* Set PMAX_LOCK - must be set before RESET CPL4 */ - data = pci_s_read_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX); + data = pci_s_read_config32(PCI_DEV((seg << 8) | bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX); data |= PMAX_LOCK; - pci_s_write_config32(PCI_DEV(bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX, data); + pci_s_write_config32(PCI_DEV((seg << 8) | bus, PCU_DEV, PCU_CR0_FUN), PCU_CR0_PMAX, data); /* update RST_CPL4, PCODE_INIT_DONE4 */ timedout = set_bios_reset_cpl_for_package(socket, RST_CPL4_MASK, -- To view, visit https://review.coreboot.org/c/coreboot/+/79878?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0ba5e426123234979d746d3bdfc1ddfbd71c3447 Gerrit-Change-Number: 79878 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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[M] Change in coreboot[main]: device: Add support for multiple PCI segments
by Patrick Rudolph (Code Review) 10 Jan '24

10 Jan '24

Patrick Rudolph has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79877?usp=email ) Change subject: device: Add support for multiple PCI segments ...................................................................... device: Add support for multiple PCI segments Add initial support for multiple PCI segments. Since all platforms currently only use segment 0 this is not a functional change. Change-Id: Iab2c97a71a650e1ceadce4f985147ce05d4e8c86 Signed-off-by: Patrick Rudolph <patrick.rudolph(a)9elements.com> --- M src/acpi/acpi.c M src/device/Kconfig M src/device/device.c M src/device/device_const.c M src/device/device_util.c M src/device/pci_device.c M src/include/device/device.h M src/include/device/pci_def.h M src/include/device/pci_ops.h M src/lib/smbios.c M src/soc/amd/common/block/data_fabric/domain.c 11 files changed, 56 insertions(+), 18 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/77/79877/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index beba5fd..d8e0f11 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -150,9 +150,14 @@ static unsigned long acpi_fill_mcfg(unsigned long current) { - current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0, + for (int i = 0; i < CONFIG_ECAM_SEGMENT_COUNT; i++) { + current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, + CONFIG_ECAM_MMCONF_BASE_ADDRESS + + i * CONFIG_ECAM_MMCONF_LENGTH, i, + i * CONFIG_ECAM_MMCONF_BUS_NUMBER, CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); + } + return current; } @@ -695,6 +700,7 @@ if (device->path.type == DEVICE_PATH_PCI) { spmi->pci_device_flag = ACPI_IPMI_PCI_DEVICE_FLAG; + spmi->pci_segment_group = device->bus->segment; spmi->pci_bus = device->bus->secondary; spmi->pci_device = device->path.pci.devfn >> 3; spmi->pci_function = device->path.pci.devfn & 0x7; diff --git a/src/device/Kconfig b/src/device/Kconfig index 8085bbd..501a0f0 100644 --- a/src/device/Kconfig +++ b/src/device/Kconfig @@ -556,6 +556,16 @@ Access mechanism (ECAM) method for accessing PCI config address space. +config ECAM_SEGMENT_COUNT + int + depends on ECAM_MMCONF_SUPPORT + default 1 + help + Count of MMCONF segments. On mobile/desktop platforms this is + usually 1. On multi-socket server platforms this can be greater 1 + if more than 256 PCI buses are supported. The segments are same + sized and continous in physical memory. + config PCIX_PLUGIN_SUPPORT bool default y diff --git a/src/device/device.c b/src/device/device.c index a635e73..f379de1 100644 --- a/src/device/device.c +++ b/src/device/device.c @@ -152,8 +152,8 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s %s bus %d link: %d\n", dev_path(bus->dev), - __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s segment %d bus %d link: %d\n", dev_path(bus->dev), + __func__, bus->segment, bus->secondary, bus->link_num); /* Walk through all devices and find which resources they need. */ for (curdev = bus->children; curdev; curdev = curdev->sibling) { @@ -176,8 +176,8 @@ read_resources(link); } post_log_clear(); - printk(BIOS_SPEW, "%s %s bus %d link: %d done\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s segment %d bus %d link: %d done\n", + dev_path(bus->dev), __func__, bus->segment, bus->secondary, bus->link_num); } struct device *vga_pri = NULL; @@ -266,8 +266,8 @@ { struct device *curdev; - printk(BIOS_SPEW, "%s %s, bus %d link: %d\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, segment %d bus %d link: %d\n", + dev_path(bus->dev), __func__, bus->segment, bus->secondary, bus->link_num); for (curdev = bus->children; curdev; curdev = curdev->sibling) { if (!curdev->enabled || !curdev->resource_list) @@ -282,8 +282,8 @@ curdev->ops->set_resources(curdev); } post_log_clear(); - printk(BIOS_SPEW, "%s %s, bus %d link: %d done\n", - dev_path(bus->dev), __func__, bus->secondary, bus->link_num); + printk(BIOS_SPEW, "%s %s, segment %d bus %d link: %d done\n", + dev_path(bus->dev), __func__, bus->segment, bus->secondary, bus->link_num); } /** diff --git a/src/device/device_const.c b/src/device/device_const.c index a63a629..b7516b1 100644 --- a/src/device/device_const.c +++ b/src/device/device_const.c @@ -35,6 +35,7 @@ for (dev = all_devices; dev; dev = dev->next) { if ((dev->path.type == DEVICE_PATH_PCI) && (dev->bus->secondary == bus) && + (dev->bus->segment == 0) && (dev->path.pci.devfn == devfn)) { result = dev; break; @@ -224,8 +225,16 @@ DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t devfn) { + return pcidev_path_on_segbus(0, bus, devfn); +} + +DEVTREE_CONST struct device *pcidev_path_on_segbus(unsigned int segment, + unsigned int bus, + pci_devfn_t devfn) +{ DEVTREE_CONST struct bus *parent = pci_root_bus(); DEVTREE_CONST struct device *dev = parent->children; + assert(segment < CONFIG_ECAM_SEGMENT_COUNT); /* FIXME: Write the loop with topology links. */ while (dev) { @@ -233,7 +242,7 @@ dev = dev->next; continue; } - if (dev->bus->secondary == bus) + if (dev->bus->secondary == bus && dev->bus->segment == segment) return pcidev_path_behind(dev->bus, devfn); dev = dev->next; } diff --git a/src/device/device_util.c b/src/device/device_util.c index b37d1d9..fcc78e9 100644 --- a/src/device/device_util.c +++ b/src/device/device_util.c @@ -97,7 +97,7 @@ case DEVICE_PATH_ROOT: break; case DEVICE_PATH_PCI: - ret |= dev->bus->secondary << 8 | dev->path.pci.devfn; + ret |= dev->bus->segment << 16 | dev->bus->secondary << 8 | dev->path.pci.devfn; break; case DEVICE_PATH_PNP: ret |= dev->path.pnp.port << 8 | dev->path.pnp.device; @@ -168,7 +168,8 @@ break; case DEVICE_PATH_PCI: snprintf(buffer, sizeof(buffer), - "PCI: %02x:%02x.%01x", + "PCI: %02x:%02x:%02x.%01x", + dev->bus->segment, dev->bus->secondary, PCI_SLOT(dev->path.pci.devfn), PCI_FUNC(dev->path.pci.devfn)); @@ -525,7 +526,8 @@ if (dev->link_list && (resource->flags & IORESOURCE_PCI_BRIDGE)) { snprintf(buf, sizeof(buf), - "bus %02x ", dev->link_list->secondary); + "seg %02x bus %02x ", dev->link_list->segment, + dev->link_list->secondary); } printk(BIOS_DEBUG, "%s %02lx <- [0x%016llx - 0x%016llx] size 0x%08llx " "gran 0x%02x %s%s%s\n", dev_path(dev), resource->index, diff --git a/src/device/pci_device.c b/src/device/pci_device.c index 21b4352..f3fd5ee 100644 --- a/src/device/pci_device.c +++ b/src/device/pci_device.c @@ -1314,7 +1314,8 @@ */ unsigned int pci_match_simple_dev(struct device *dev, pci_devfn_t sdev) { - return dev->bus->secondary == PCI_DEV2SEGBUS(sdev) && + return dev->bus->secondary == PCI_DEV2BUS(sdev) && + dev->bus->segment == PCI_DEV2SEG(sdev) && dev->path.pci.devfn == PCI_DEV2DEVFN(sdev); } @@ -1428,7 +1429,8 @@ struct device *dev, **prev; int once = 0; - printk(BIOS_DEBUG, "PCI: %s for bus %02x\n", __func__, bus->secondary); + printk(BIOS_DEBUG, "PCI: %s for segment %02x bus %02x\n", __func__, + bus->segment, bus->secondary); /* Maximum sane devfn is 0xFF. */ if (max_devfn > 0xff) { @@ -1550,6 +1552,7 @@ link->max_subordinate = parent->max_subordinate ? parent->max_subordinate : (CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); + link->segment = parent->segment; } if (link->secondary > link->max_subordinate) diff --git a/src/include/device/device.h b/src/include/device/device.h index 41ec528..ab73f16 100644 --- a/src/include/device/device.h +++ b/src/include/device/device.h @@ -86,6 +86,7 @@ uint16_t secondary; /* secondary bus number */ uint16_t subordinate; /* subordinate bus number */ uint16_t max_subordinate; /* max subordinate bus number */ + uint8_t segment; /* PCI segment */ unsigned int reset_needed : 1; unsigned int no_vga16 : 1; /* No support for 16-bit VGA decoding */ @@ -425,6 +426,9 @@ pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_path_on_root(pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_path_on_bus(unsigned int bus, pci_devfn_t devfn); +DEVTREE_CONST struct device *pcidev_path_on_segbus(unsigned int segment, + unsigned int bus, + pci_devfn_t devfn); DEVTREE_CONST struct device *pcidev_on_root(uint8_t dev, uint8_t fn); DEVTREE_CONST struct bus *pci_root_bus(void); /* Find PCI device with given D#:F# sitting behind the given PCI-to-PCI bridge device. */ diff --git a/src/include/device/pci_def.h b/src/include/device/pci_def.h index 8b90163..7821bc1 100644 --- a/src/include/device/pci_def.h +++ b/src/include/device/pci_def.h @@ -594,6 +594,8 @@ /* Translation from PCI_DEV() to devicetree bus and path.pci.devfn. */ #define PCI_DEV2DEVFN(sdev) (((sdev)>>12) & 0xff) #define PCI_DEV2SEGBUS(sdev) (((sdev)>>20) & 0xfff) +#define PCI_DEV2BUS(sdev) (((sdev)>>20) & 0xff) +#define PCI_DEV2SEG(sdev) (((sdev)>>28) & 0xf) /* Fields from within the device's class value. */ #define PCI_CLASS_GET_DEVICE(c) (c >> 8) diff --git a/src/include/device/pci_ops.h b/src/include/device/pci_ops.h index b5d4e23..3e75be7 100644 --- a/src/include/device/pci_ops.h +++ b/src/include/device/pci_ops.h @@ -12,7 +12,8 @@ static __always_inline pci_devfn_t pcidev_bdf(const struct device *dev) { - return (dev->path.pci.devfn << 12) | (dev->bus->secondary << 20); + return (dev->path.pci.devfn << 12) | (dev->bus->secondary << 20) | + (dev->bus->segment << 28); } static __always_inline pci_devfn_t pcidev_assert(const struct device *dev) diff --git a/src/lib/smbios.c b/src/lib/smbios.c index 3ef3c21..2763a29 100644 --- a/src/lib/smbios.c +++ b/src/lib/smbios.c @@ -1113,7 +1113,7 @@ return smbios_write_type41(current, handle, name, // name instance_id, // inst - 0, // segment + dev->bus->segment, // segment dev->bus->secondary, //bus PCI_SLOT(dev->path.pci.devfn), // device PCI_FUNC(dev->path.pci.devfn), // func diff --git a/src/soc/amd/common/block/data_fabric/domain.c b/src/soc/amd/common/block/data_fabric/domain.c index 39f5790..7e7bb53 100644 --- a/src/soc/amd/common/block/data_fabric/domain.c +++ b/src/soc/amd/common/block/data_fabric/domain.c @@ -38,6 +38,7 @@ domain->link_list->subordinate = bus; /* Tell allocator about maximum PCI bus number in domain */ domain->link_list->max_subordinate = limit; + domain->link_list->segment = segment_group; pci_host_bridge_scan_bus(domain); } -- To view, visit https://review.coreboot.org/c/coreboot/+/79877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab2c97a71a650e1ceadce4f985147ce05d4e8c86 Gerrit-Change-Number: 79877 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[main]: soc/intel/common/tcss: Fix Kconfig dependency
by Sean Rhodes (Code Review) 10 Jan '24

10 Jan '24

Sean Rhodes has uploaded a new patch set (#2). ( https://review.coreboot.org/c/coreboot/+/79875?usp=email ) Change subject: soc/intel/common/tcss: Fix Kconfig dependency ...................................................................... soc/intel/common/tcss: Fix Kconfig dependency ENABLE_TCSS_DISPLAY_DETECTION will call usbc_get_ops, which depends on ENABLE_TCSS_USB_DETECTION. Add this is Kconfig to avoid issues. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I46cab8b385b2aefe1fc106bf5a2dcfe8f15dbe10 --- M src/soc/intel/common/block/tcss/Kconfig 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/75/79875/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79875?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46cab8b385b2aefe1fc106bf5a2dcfe8f15dbe10 Gerrit-Change-Number: 79875 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/nissa/var/anraggar: Add FW_CONFIG probe for mipi camera
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79802?usp=email ) Change subject: mb/google/nissa/var/anraggar: Add FW_CONFIG probe for mipi camera ...................................................................... mb/google/nissa/var/anraggar: Add FW_CONFIG probe for mipi camera Due to some without mipi camera SKUs can't entering S0i3. BUG=b:317670018 TEST=suspend_stress_test -c 1 Change-Id: Ifa8649a603c59946b530abd315113b405ceaf35a Signed-off-by: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79802 Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> Reviewed-by: Eric Lai <ericllai(a)google.com> --- M src/mainboard/google/brya/variants/anraggar/overridetree.cb 1 file changed, 25 insertions(+), 4 deletions(-) Approvals: Weimin Wu: Looks good to me, but someone else must approve build bot (Jenkins): Verified Eric Lai: Looks good to me, approved diff --git a/src/mainboard/google/brya/variants/anraggar/overridetree.cb b/src/mainboard/google/brya/variants/anraggar/overridetree.cb index a95c763..8fe4316 100644 --- a/src/mainboard/google/brya/variants/anraggar/overridetree.cb +++ b/src/mainboard/google/brya/variants/anraggar/overridetree.cb @@ -1,3 +1,12 @@ +fw_config + field CAMERA 12 13 + option UF_720P_WF 0 + option UF_1080P 1 + option UF_720P 2 + option UF_1080P_WF 3 + end +end + chip soc/intel/alderlake register "sagv" = "SaGv_Enabled" @@ -210,7 +219,10 @@ register "cio2_lanes_used" = "{4}" # 4 CSI Camera lanes are used register "cio2_lane_endpoint[0]" = ""^I2C2.CAM0"" register "cio2_prt[0]" = "1" - device generic 0 on end + device generic 0 on + probe CAMERA UF_720P_WF + probe CAMERA UF_1080P_WF + end end end device ref i2c1 on @@ -281,7 +293,10 @@ register "off_seq.ops[2]" = "SEQ_OPS_GPIO_DISABLE(1, 0)" register "off_seq.ops[3]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 36 on end + device i2c 36 on + probe CAMERA UF_720P_WF + probe CAMERA UF_1080P_WF + end end chip drivers/intel/mipi_camera register "acpi_uid" = "2" @@ -303,7 +318,10 @@ register "off_seq.ops_cnt" = "1" register "off_seq.ops[0]" = "SEQ_OPS_GPIO_DISABLE(0, 0)" - device i2c 0C on end + device i2c 0C on + probe CAMERA UF_720P_WF + probe CAMERA UF_1080P_WF + end end chip drivers/intel/mipi_camera register "acpi_uid" = "1" @@ -317,7 +335,10 @@ register "nvm_width" = "0x10" register "nvm_compat" = ""atmel,24c64"" - device i2c 50 on end + device i2c 50 on + probe CAMERA UF_720P_WF + probe CAMERA UF_1080P_WF + end end end device ref i2c3 on -- To view, visit https://review.coreboot.org/c/coreboot/+/79802?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ifa8649a603c59946b530abd315113b405ceaf35a Gerrit-Change-Number: 79802 Gerrit-PatchSet: 2 Gerrit-Owner: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Weimin Wu <wuweimin(a)huaqin.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dolan Liu <liuyong5(a)huaqin.corp-partner.google.com> Gerrit-MessageType: merged

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