coreboot-gerrit January 2024

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[M] Change in coreboot[main]: device: Add support for multiple PCI segments
by Nico Huber (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Cliff Huang, Felix Held, Fred Reitberger, Jason Glenesk, Lance Zhao, Matt DeVillier, Patrick Rudolph, Tim Wawrzynczak. Nico Huber has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79877?usp=email ) Change subject: device: Add support for multiple PCI segments ...................................................................... Patch Set 1: Code-Review+1 (5 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79877/comment/12c8ec3d_df8b7a63 : PS1, Line 7: PCI segments I wouldn't call this segments. Linux calls this "PCI domains", ACPI calls it "PCI segment groups". A segment is just the (sub)tree below any node. So this could be confused. Patchset: PS1: Finally somebody does it :) File src/acpi/acpi.c: https://review.coreboot.org/c/coreboot/+/79877/comment/e1420dea_04355813 : PS1, Line 157: i * CONFIG_ECAM_MMCONF_BUS_NUMBER Shouldn't this still be 0? In each segment group we start from 0, I guess. File src/include/device/device.h: https://review.coreboot.org/c/coreboot/+/79877/comment/136de95f_c22cf55f : PS1, Line 89: uint8_t segment; /* PCI segment */ We also discussed lately if it wouldn't be easier to make it part of the bus number, i.e. `secondary` which is already 16 bits. That would spare us a lot of manual handling (and potential bugs if it's missed somewhere). It also fits the idea of a consecutive ECAM space. We could still split the numbers in console output if that's preferred. WDYT? File src/soc/amd/common/block/data_fabric/domain.c: https://review.coreboot.org/c/coreboot/+/79877/comment/af419df6_36d72190 : PS1, Line 23: : /* TODO: Implement support for more than one PCI segment group in coreboot */ : if (segment_group) { : printk(BIOS_ERR, "coreboot currently only supports one PCI segment group.\n"); : return; : } Should this stay? -- To view, visit https://review.coreboot.org/c/coreboot/+/79877?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iab2c97a71a650e1ceadce4f985147ce05d4e8c86 Gerrit-Change-Number: 79877 Gerrit-PatchSet: 1 Gerrit-Owner: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Lance Zhao <lance.zhao(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Cliff Huang <cliff.huang(a)intel.com> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Tim Wawrzynczak <inforichland(a)gmail.com> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Wed, 10 Jan 2024 20:28:28 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[M] Change in coreboot[main]: sb/intel/common: Get memory map from SPI controller
by Arthur Heymans (Code Review) 10 Jan '24

10 Jan '24

Arthur Heymans has uploaded a new patch set (#5). ( https://review.coreboot.org/c/coreboot/+/79880?usp=email ) Change subject: sb/intel/common: Get memory map from SPI controller ...................................................................... sb/intel/common: Get memory map from SPI controller Instead of always assuming that the top of a flash matches the top of 4G use the real memory map that's configured in the IFD and is reflected in the SPI registers. One possible use case is to cleanly generate images for some hacks rather than having to apply some 'dd' trickery: e.g. on HP Sure Start a part of the flash is checked by EC. UNTESTED. This might break some hacks people use to work around SPI locked images by modifying the IFD when booted with a recovery strap pulled. Those would also need a specifically crafted FMAP. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 --- M src/southbridge/intel/common/Kconfig.common M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/rcba.h A src/southbridge/intel/common/spi_memmap.c 4 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/79880/5 -- To view, visit https://review.coreboot.org/c/coreboot/+/79880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 Gerrit-Change-Number: 79880 Gerrit-PatchSet: 5 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: sb/intel/common: Get memory map from SPI controller
by Arthur Heymans (Code Review) 10 Jan '24

10 Jan '24

Arthur Heymans has uploaded a new patch set (#4). ( https://review.coreboot.org/c/coreboot/+/79880?usp=email ) Change subject: sb/intel/common: Get memory map from SPI controller ...................................................................... sb/intel/common: Get memory map from SPI controller Instead of always assuming that the top of a flash matches the top of 4G use the real memory map that's configured in the IFD and is reflected in the SPI registers. One possible use case is to cleanly generate images for some hacks rather than having to apply some 'dd' trickery: e.g. on HP Sure Start a part of the flash is checked by EC. UNTESTED. This might break some hacks people use to work around SPI locked images by modifying the IFD when booted with a recovery strap pulled. Those would also need a specifically crafted FMAP. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 --- M src/southbridge/intel/common/Kconfig.common M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/rcba.h A src/southbridge/intel/common/spi_memmap.c 4 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/79880/4 -- To view, visit https://review.coreboot.org/c/coreboot/+/79880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 Gerrit-Change-Number: 79880 Gerrit-PatchSet: 4 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: arch/x86/include/smm_call: use pm_acpi_smi_cmd_port
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Arthur Heymans, Felix Held, Jérémy Compostella, Matt DeVillier. Hello Jérémy Compostella, Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79568?usp=email to look at the new patch set (#8). Change subject: arch/x86/include/smm_call: use pm_acpi_smi_cmd_port ...................................................................... arch/x86/include/smm_call: use pm_acpi_smi_cmd_port Use pm_acpi_smi_cmd_port() to get the APMC trigger IO port instead of using the hard-coded APM_CNT define. This makes sure that the correct APMC IO port will be used even when a system doesn't use the default APM IO port. TEST=SMMSTORE V2 still works with the EDK2 payload on Careena Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Icb79c91cfcd75db760bd80cff7f3d0400d1f16cd --- M src/arch/x86/include/smm_call.h 1 file changed, 2 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/68/79568/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/79568?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icb79c91cfcd75db760bd80cff7f3d0400d1f16cd Gerrit-Change-Number: 79568 Gerrit-PatchSet: 8 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: drivers/smmstore/ramstage: use call_smm
by Felix Held (Code Review) 10 Jan '24

10 Jan '24

Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79766?usp=email to look at the new patch set (#6). Change subject: drivers/smmstore/ramstage: use call_smm ...................................................................... drivers/smmstore/ramstage: use call_smm Use call_smm instead of open-coding the same in inline assembly functionality in init_store. The local ebx variable is dropped, since call_smm takes a pointer to the argument instead of an integer, and the local eax variable is renamed to res to make the code a bit clearer, since the EAX register is used for both passing the command and subcommand to the APMC SMI handler and to get the return value from the handler. TEST=SMMSTORE V2 still works with the EDK2 payload on Careena Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Change-Id: Ib14de0d120ae5c7db3bb7a529837ababe653e1a2 --- M src/drivers/smmstore/ramstage.c 1 file changed, 4 insertions(+), 11 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/66/79766/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/79766?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib14de0d120ae5c7db3bb7a529837ababe653e1a2 Gerrit-Change-Number: 79766 Gerrit-PatchSet: 6 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: sb/intel/common: Get memory map from SPI controller
by Arthur Heymans (Code Review) 10 Jan '24

10 Jan '24

Arthur Heymans has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/79880?usp=email ) Change subject: sb/intel/common: Get memory map from SPI controller ...................................................................... sb/intel/common: Get memory map from SPI controller Instead of always assuming that the top of a flash matches the top of 4G use the real memory map that's configured in the IFD and is reflected in the SPI registers. One possible use case is to cleanly generate images for some hacks rather than having to apply some 'dd' trickery: e.g. on HP Sure Start a part of the flash is checked by EC. UNTESTED. This might break some hacks people use to work around SPI locked images by modifying the IFD when booted with a recovery strap pulled. Those would also need a specifically crafted FMAP. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 --- M src/southbridge/intel/common/Kconfig.common M src/southbridge/intel/common/Makefile.inc M src/southbridge/intel/common/rcba.h A src/southbridge/intel/common/spi_memmap.c 4 files changed, 90 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/80/79880/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79880?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5f31c175345ec3efab02255a7063054eb0ad29e4 Gerrit-Change-Number: 79880 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/common/tcss: Fix Kconfig dependency
by Sean Rhodes (Code Review) 10 Jan '24

10 Jan '24

Sean Rhodes has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/79875?usp=email ) Change subject: soc/intel/common/tcss: Fix Kconfig dependency ...................................................................... Abandoned Doesn't work -- To view, visit https://review.coreboot.org/c/coreboot/+/79875?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I46cab8b385b2aefe1fc106bf5a2dcfe8f15dbe10 Gerrit-Change-Number: 79875 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: abandon

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[XS] Change in coreboot[main]: soc/intel/common/tcss: Guard disconnect_tcss_display for ChromeOS
by Sean Rhodes (Code Review) 10 Jan '24

10 Jan '24

Sean Rhodes has uploaded a new patch set (#3). ( https://review.coreboot.org/c/coreboot/+/79876?usp=email ) Change subject: soc/intel/common/tcss: Guard disconnect_tcss_display for ChromeOS ...................................................................... soc/intel/common/tcss: Guard disconnect_tcss_display for ChromeOS Only ChromeOS devices can reconnect a display, so guard against this to avoid displays being disconnected without the possibility of being reconnected. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I4685344224f321211944505b666d0d643affef2e --- M src/soc/intel/common/block/tcss/tcss.c 1 file changed, 3 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/76/79876/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79876?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4685344224f321211944505b666d0d643affef2e Gerrit-Change-Number: 79876 Gerrit-PatchSet: 3 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-CC: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: soc/intel/common/tcss: Rename tcss_mux_init
by Sean Rhodes (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Matt DeVillier. Hello Matt DeVillier, build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79874?usp=email to look at the new patch set (#2). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/intel/common/tcss: Rename tcss_mux_init ...................................................................... soc/intel/common/tcss: Rename tcss_mux_init Rename tcss_mux_init to disconnect_tcss_devices to make it clear what this function is doing, as it doesn't initialise anything. Signed-off-by: Sean Rhodes <sean(a)starlabs.systems> Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584 --- M src/soc/intel/common/block/tcss/tcss.c 1 file changed, 2 insertions(+), 2 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/74/79874/2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79874?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5e43f0cca9d49bc30fc189663490a306efd71584 Gerrit-Change-Number: 79874 Gerrit-PatchSet: 2 Gerrit-Owner: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Matt DeVillier <matt.devillier(a)gmail.com> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[main]: mb/hp/(elitebook_820_g2|folio_9480m): Add HP Sure Start workaround
by Arthur Heymans (Code Review) 10 Jan '24

10 Jan '24

Attention is currently required from: Iru Cai, Iru Cai. Hello Iru Cai, Iru Cai, I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79881?usp=email to look at the new patch set (#3). Change subject: mb/hp/(elitebook_820_g2|folio_9480m): Add HP Sure Start workaround ...................................................................... mb/hp/(elitebook_820_g2|folio_9480m): Add HP Sure Start workaround To work around HP Sure Start the top of flash needs to contain a vendor provided image that the EC verifies before releasing the X86 from reset. Instead of using the wrong flash size and padding the image with dd, add an fmap layout and use cbfstool memory map arguments to achieve the same. UNTESTED. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I0e59d035ce9281062272aeef92f50f2bbf3a9c5f --- M Documentation/mainboard/hp/elitebook_820_g2.md M src/mainboard/hp/elitebook_820_g2/Kconfig M src/mainboard/hp/elitebook_820_g2/Makefile.inc A src/mainboard/hp/elitebook_820_g2/board.fmd M src/mainboard/hp/folio_9480m/Kconfig M src/mainboard/hp/folio_9480m/Makefile.inc A src/mainboard/hp/folio_9480m/board.fmd 7 files changed, 80 insertions(+), 8 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/81/79881/3 -- To view, visit https://review.coreboot.org/c/coreboot/+/79881?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I0e59d035ce9281062272aeef92f50f2bbf3a9c5f Gerrit-Change-Number: 79881 Gerrit-PatchSet: 3 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-Attention: Iru Cai <mytbk920423(a)gmail.com> Gerrit-MessageType: newpatchset

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coreboot-gerrit January 2024