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[M] Change in coreboot[main]: arch/arm: Reformat C files with clang-format v16
by Martin L Roth (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Julius Werner. Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80008?usp=email ) Change subject: arch/arm: Reformat C files with clang-format v16 ...................................................................... arch/arm: Reformat C files with clang-format v16 Reformat only - No functional changes. Change-Id: Icace93f70f024f8690172e030d0922973beb2727 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M src/arch/arm/armv4/cache.c M src/arch/arm/armv7/cache.c M src/arch/arm/armv7/cache_m.c M src/arch/arm/armv7/exception.c M src/arch/arm/armv7/mmu.c M src/arch/arm/clock.c M src/arch/arm/eabi_compat.c M src/arch/arm/fit_payload.c M src/arch/arm/tables.c 9 files changed, 99 insertions(+), 110 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/08/80008/1 diff --git a/src/arch/arm/armv4/cache.c b/src/arch/arm/armv4/cache.c index 0ed11ac..019adc0 100644 --- a/src/arch/arm/armv4/cache.c +++ b/src/arch/arm/armv4/cache.c @@ -34,15 +34,15 @@ return 64; } -void dcache_clean_by_mva(void const *addr, size_t len) +void dcache_clean_by_mva(const void *addr, size_t len) { } -void dcache_clean_invalidate_by_mva(void const *addr, size_t len) +void dcache_clean_invalidate_by_mva(const void *addr, size_t len) { } -void dcache_invalidate_by_mva(void const *addr, size_t len) +void dcache_invalidate_by_mva(const void *addr, size_t len) { } diff --git a/src/arch/arm/armv7/cache.c b/src/arch/arm/armv7/cache.c index 1c46e04..9846a37 100644 --- a/src/arch/arm/armv7/cache.c +++ b/src/arch/arm/armv7/cache.c @@ -37,8 +37,8 @@ ccsidr = read_ccsidr(); /* [2:0] - Indicates (Log2(number of words in cache line)) - 2 */ - line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */ - line_bytes *= sizeof(unsigned int); /* bytes per line */ + line_bytes = 1 << ((ccsidr & 0x7) + 2); /* words per line */ + line_bytes *= sizeof(unsigned int); /* bytes per line */ return line_bytes; } @@ -49,7 +49,7 @@ * perform cache maintenance on a particular memory range rather than the * entire cache. */ -static void dcache_op_mva(void const *addr, size_t len, enum dcache_op op) +static void dcache_op_mva(const void *addr, size_t len, enum dcache_op op) { unsigned long line, linesize; @@ -76,17 +76,17 @@ isb(); } -void dcache_clean_by_mva(void const *addr, size_t len) +void dcache_clean_by_mva(const void *addr, size_t len) { dcache_op_mva(addr, len, OP_DCCMVAC); } -void dcache_clean_invalidate_by_mva(void const *addr, size_t len) +void dcache_clean_invalidate_by_mva(const void *addr, size_t len) { dcache_op_mva(addr, len, OP_DCCIMVAC); } -void dcache_invalidate_by_mva(void const *addr, size_t len) +void dcache_invalidate_by_mva(const void *addr, size_t len) { dcache_op_mva(addr, len, OP_DCIMVAC); } @@ -126,7 +126,7 @@ else if (sctlr & SCTLR_I) dcache_clean_invalidate_all(); - iciallu(); /* includes BPIALLU (architecturally) */ + iciallu(); /* includes BPIALLU (architecturally) */ dsb(); isb(); } diff --git a/src/arch/arm/armv7/cache_m.c b/src/arch/arm/armv7/cache_m.c index 06ed599..311216c 100644 --- a/src/arch/arm/armv7/cache_m.c +++ b/src/arch/arm/armv7/cache_m.c @@ -26,15 +26,15 @@ return 0; } -void dcache_clean_by_mva(void const *addr, size_t len) +void dcache_clean_by_mva(const void *addr, size_t len) { } -void dcache_clean_invalidate_by_mva(void const *addr, size_t len) +void dcache_clean_invalidate_by_mva(const void *addr, size_t len) { } -void dcache_invalidate_by_mva(void const *addr, size_t len) +void dcache_invalidate_by_mva(const void *addr, size_t len) { } diff --git a/src/arch/arm/armv7/exception.c b/src/arch/arm/armv7/exception.c index 799ae02..d98686c 100644 --- a/src/arch/arm/armv7/exception.c +++ b/src/arch/arm/armv7/exception.c @@ -53,7 +53,7 @@ void exception_undefined_instruction(uint32_t *regs) { printk(BIOS_ERR, "exception _undefined_instruction\n"); - regs[15] -= 2; /* CAREFUL: specific to thumb mode (otherwise 4)! */ + regs[15] -= 2; /* CAREFUL: specific to thumb mode (otherwise 4)! */ print_regs(regs); dump_stack(regs[13], 512); die("exception"); diff --git a/src/arch/arm/armv7/mmu.c b/src/arch/arm/armv7/mmu.c index 66ce533..3cbbd53 100644 --- a/src/arch/arm/armv7/mmu.c +++ b/src/arch/arm/armv7/mmu.c @@ -12,30 +12,29 @@ #if CONFIG(ARM_LPAE) /* See B3.6.2 of ARMv7 Architecture Reference Manual */ /* TODO: Utilize the contiguous hint flag */ -#define ATTR_BLOCK (\ - 0ULL << 54 | /* XN. 0:Not restricted */ \ - 0ULL << 53 | /* PXN. 0:Not restricted */ \ - 1 << 10 | /* AF. 1:Accessed. This is to prevent access */ \ - /* fault when accessed for the first time */ \ - 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \ - 0 << 5 | /* NS. 0:Output address is in Secure space */ \ - 0 << 1 | /* block/table. 0:block entry */ \ - 1 << 0 /* validity. 1:valid */ \ +#define ATTR_BLOCK \ + (0ULL << 54 | /* XN. 0:Not restricted */ \ + 0ULL << 53 | /* PXN. 0:Not restricted */ \ + 1 << 10 | /* AF. 1:Accessed. This is to prevent access fault when accessed for the first time */ \ + 0 << 6 | /* AP[2:1]. 0b00:full access from PL1 */ \ + 0 << 5 | /* NS. 0:Output address is in Secure space */ \ + 0 << 1 | /* block/table. 0:block entry */ \ + 1 << 0 /* validity. 1:valid */ \ ) -#define ATTR_PAGE (ATTR_BLOCK | 1 << 1) -#define ATTR_NEXTLEVEL (0x3) -#define ATTR_NC ((MAIR_INDX_NC << 2) | (1ULL << 53) | (1ULL << 54)) -#define ATTR_WT (MAIR_INDX_WT << 2) -#define ATTR_WB (MAIR_INDX_WB << 2) +#define ATTR_PAGE (ATTR_BLOCK | 1 << 1) +#define ATTR_NEXTLEVEL (0x3) +#define ATTR_NC ((MAIR_INDX_NC << 2) | (1ULL << 53) | (1ULL << 54)) +#define ATTR_WT (MAIR_INDX_WT << 2) +#define ATTR_WB (MAIR_INDX_WB << 2) -#define PAGE_MASK 0x000ffffffffff000ULL -#define BLOCK_MASK 0x000fffffffe00000ULL -#define NEXTLEVEL_MASK PAGE_MASK -#define BLOCK_SHIFT 21 +#define PAGE_MASK 0x000ffffffffff000ULL +#define BLOCK_MASK 0x000fffffffe00000ULL +#define NEXTLEVEL_MASK PAGE_MASK +#define BLOCK_SHIFT 21 typedef uint64_t pte_t; -#else /* CONFIG_ARM_LPAE */ - /* +#else /* CONFIG_ARM_LPAE */ +/* * Section entry bits: * 31:20 - section base address * 18 - 0 to indicate normal section (versus supersection) @@ -51,39 +50,39 @@ * 2 - B, 1 for bufferable * 1: 0 - 0b10 to indicate section entry */ -#define ATTR_BLOCK ((3 << 10) | 0x2) -#define ATTR_PAGE ((3 << 4) | 0x2) -#define ATTR_NEXTLEVEL (0x1) -#define ATTR_NC (1 << 4) -#define ATTR_WT (1 << 3) -#define ATTR_WB ((1 << 3) | (1 << 2)) +#define ATTR_BLOCK ((3 << 10) | 0x2) +#define ATTR_PAGE ((3 << 4) | 0x2) +#define ATTR_NEXTLEVEL (0x1) +#define ATTR_NC (1 << 4) +#define ATTR_WT (1 << 3) +#define ATTR_WB ((1 << 3) | (1 << 2)) -#define PAGE_MASK 0xfffff000UL -#define BLOCK_MASK 0xfff00000UL -#define NEXTLEVEL_MASK 0xfffffc00UL -#define BLOCK_SHIFT 20 +#define PAGE_MASK 0xfffff000UL +#define BLOCK_MASK 0xfff00000UL +#define NEXTLEVEL_MASK 0xfffffc00UL +#define BLOCK_SHIFT 20 typedef uint32_t pte_t; -#endif /* CONFIG_ARM_LPAE */ +#endif /* CONFIG_ARM_LPAE */ /* We set the first PTE to a sentinel value that cannot occur naturally (has * attributes set but bits [1:0] are 0 -> unmapped) to mark unused subtables. */ -#define ATTR_UNUSED 0xBADbA6E0 -#define SUBTABLE_PTES (1 << (BLOCK_SHIFT - PAGE_SHIFT)) +#define ATTR_UNUSED 0xBADbA6E0 +#define SUBTABLE_PTES (1 << (BLOCK_SHIFT - PAGE_SHIFT)) /* * mask/shift/size for pages and blocks */ -#define PAGE_SHIFT 12 -#define PAGE_SIZE (1UL << PAGE_SHIFT) -#define BLOCK_SIZE (1UL << BLOCK_SHIFT) +#define PAGE_SHIFT 12 +#define PAGE_SIZE (1UL << PAGE_SHIFT) +#define BLOCK_SIZE (1UL << BLOCK_SHIFT) /* * MAIR Index */ -#define MAIR_INDX_NC 0 -#define MAIR_INDX_WT 1 -#define MAIR_INDX_WB 2 +#define MAIR_INDX_NC 0 +#define MAIR_INDX_WT 1 +#define MAIR_INDX_WB 2 static pte_t *const ttb_buff = (void *)_ttb; @@ -91,16 +90,16 @@ pte_t value; const char *name; } attrs[] = { - [DCACHE_OFF] = {.value = ATTR_NC, .name = "uncached"}, - [DCACHE_WRITEBACK] = {.value = ATTR_WB, .name = "writeback"}, + [DCACHE_OFF] = {.value = ATTR_NC, .name = "uncached" }, + [DCACHE_WRITEBACK] = {.value = ATTR_WB, .name = "writeback" }, [DCACHE_WRITETHROUGH] = {.value = ATTR_WT, .name = "writethrough"}, }; /* Fills page table entries in |table| from |start_idx| to |end_idx| with |attr| * and performs necessary invalidations. |offset| is the start address of the * area described by |table|, and |shift| is the size-shift of each frame. */ -static void mmu_fill_table(pte_t *table, u32 start_idx, u32 end_idx, - uintptr_t offset, u32 shift, pte_t attr) +static void mmu_fill_table(pte_t *table, u32 start_idx, u32 end_idx, uintptr_t offset, + u32 shift, pte_t attr) { int i; @@ -133,8 +132,8 @@ /* We assume that *pgd_entry must already be a valid block mapping. */ uintptr_t start_addr = (uintptr_t)(*pgd_entry & BLOCK_MASK); - printk(BIOS_DEBUG, "Creating new subtable @%p for [%#.8lx:%#.8lx)\n", - table, start_addr, start_addr + BLOCK_SIZE); + printk(BIOS_DEBUG, "Creating new subtable @%p for [%#.8lx:%#.8lx)\n", table, start_addr, + start_addr + BLOCK_SIZE); /* Initialize the new subtable with entries of the same attributes * (XN bit moves from 4 to 0, set PAGE unless block was unmapped). */ @@ -158,12 +157,13 @@ static pte_t *mmu_validate_create_sub_table(u32 start_kb, u32 size_kb) { - pte_t *pgd_entry = &ttb_buff[start_kb / (BLOCK_SIZE/KiB)]; + pte_t *pgd_entry = &ttb_buff[start_kb / (BLOCK_SIZE / KiB)]; pte_t *table = (void *)(uintptr_t)(*pgd_entry & NEXTLEVEL_MASK); /* Make sure the range is contained within a single superpage. */ - assert(((start_kb + size_kb - 1) & (BLOCK_MASK/KiB)) - == (start_kb & (BLOCK_MASK/KiB)) && start_kb < 4 * (GiB/KiB)); + assert(((start_kb + size_kb - 1) & (BLOCK_MASK / KiB)) == + (start_kb & (BLOCK_MASK / KiB)) && + start_kb < 4 * (GiB / KiB)); if ((*pgd_entry & ~NEXTLEVEL_MASK) != ATTR_NEXTLEVEL) table = mmu_create_subtable(pgd_entry); @@ -181,17 +181,15 @@ attr = ((attr & ~(1 << 4)) | (1 << 0)); /* Mask away high address bits that are handled by upper level table. */ - u32 mask = BLOCK_SIZE/KiB - 1; - printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n", - start_kb * KiB, (start_kb + size_kb) * KiB, attrs[policy].name); + u32 mask = BLOCK_SIZE / KiB - 1; + printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n", start_kb * KiB, + (start_kb + size_kb) * KiB, attrs[policy].name); - u32 end_kb = ALIGN_UP((start_kb + size_kb), PAGE_SIZE/KiB) - - (start_kb & ~mask); + u32 end_kb = ALIGN_UP((start_kb + size_kb), PAGE_SIZE / KiB) - (start_kb & ~mask); - assert(end_kb <= BLOCK_SIZE/KiB); + assert(end_kb <= BLOCK_SIZE / KiB); - mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB), - end_kb / (PAGE_SIZE/KiB), + mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE / KiB), end_kb / (PAGE_SIZE / KiB), (start_kb & ~mask) * KiB, PAGE_SHIFT, ATTR_PAGE | attr); } @@ -200,32 +198,31 @@ pte_t *table = mmu_validate_create_sub_table(start_kb, size_kb); /* Mask away high address bits that are handled by upper level table. */ - u32 mask = BLOCK_SIZE/KiB - 1; - printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n", - start_kb * KiB, (start_kb + size_kb) * KiB); - mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE/KiB), - DIV_ROUND_UP((start_kb + size_kb) & mask, PAGE_SIZE/KiB), + u32 mask = BLOCK_SIZE / KiB - 1; + printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n", start_kb * KiB, + (start_kb + size_kb) * KiB); + mmu_fill_table(table, (start_kb & mask) / (PAGE_SIZE / KiB), + DIV_ROUND_UP((start_kb + size_kb) & mask, PAGE_SIZE / KiB), (start_kb & ~mask) * KiB, PAGE_SHIFT, 0); } void mmu_disable_range(u32 start_mb, u32 size_mb) { - printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n", - start_mb * MiB, (start_mb + size_mb) * MiB); - assert(start_mb + size_mb <= 4 * (GiB/MiB)); - mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB), - DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE/MiB), - 0, BLOCK_SHIFT, 0); + printk(BIOS_DEBUG, "Setting address range [%#.8x:%#.8x) as unmapped\n", start_mb * MiB, + (start_mb + size_mb) * MiB); + assert(start_mb + size_mb <= 4 * (GiB / MiB)); + mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE / MiB), + DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE / MiB), 0, BLOCK_SHIFT, 0); } void mmu_config_range(u32 start_mb, u32 size_mb, enum dcache_policy policy) { - printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n", - start_mb * MiB, (start_mb + size_mb) * MiB, attrs[policy].name); - assert(start_mb + size_mb <= 4 * (GiB/MiB)); - mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE/MiB), - DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE/MiB), - 0, BLOCK_SHIFT, ATTR_BLOCK | attrs[policy].value); + printk(BIOS_DEBUG, "Mapping address range [%#.8x:%#.8x) as %s\n", start_mb * MiB, + (start_mb + size_mb) * MiB, attrs[policy].name); + assert(start_mb + size_mb <= 4 * (GiB / MiB)); + mmu_fill_table(ttb_buff, start_mb / (BLOCK_SIZE / MiB), + DIV_ROUND_UP(start_mb + size_mb, BLOCK_SIZE / MiB), 0, BLOCK_SHIFT, + ATTR_BLOCK | attrs[policy].value); } /* @@ -247,24 +244,22 @@ table[0] = ATTR_UNUSED; if (CONFIG(ARM_LPAE)) { - pte_t *const pgd_buff = (pte_t *)(_ttb + 16*KiB); + pte_t *const pgd_buff = (pte_t *)(_ttb + 16 * KiB); pte_t *pmd = ttb_buff; int i; - printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", - ttb_buff); + printk(BIOS_DEBUG, "LPAE Translation tables are @ %p\n", ttb_buff); ASSERT((read_mmfr0() & 0xf) >= 5); /* * Set MAIR * See B4.1.104 of ARMv7 Architecture Reference Manual */ - write_mair0( - 0x00 << (MAIR_INDX_NC*8) | /* Strongly-ordered, + write_mair0(0x00 << (MAIR_INDX_NC * 8) | /* Strongly-ordered, * Non-Cacheable */ - 0xaa << (MAIR_INDX_WT*8) | /* Write-Thru, + 0xaa << (MAIR_INDX_WT * 8) | /* Write-Thru, * Read-Allocate */ - 0xff << (MAIR_INDX_WB*8) /* Write-Back, + 0xff << (MAIR_INDX_WB * 8) /* Write-Back, * Read/Write-Allocate */ ); @@ -274,8 +269,7 @@ * See B3.6.1 of ARMv7 Architecture Reference Manual */ for (i = 0; i < 4; i++) { - pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | - ATTR_NEXTLEVEL; + pgd_buff[i] = ((uint32_t)pmd & NEXTLEVEL_MASK) | ATTR_NEXTLEVEL; pmd += BLOCK_SIZE / PAGE_SIZE; } @@ -299,10 +293,9 @@ * See B4.1.153 of ARMv7 Architecture Reference Manual * See B3.5.4 and B3.6.4 for how TTBR0 or TTBR1 is selected. */ - write_ttbcr( - CONFIG(ARM_LPAE) << 31 |/* EAE. 1:Enable LPAE */ - 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ - ); + write_ttbcr(CONFIG(ARM_LPAE) << 31 | /* EAE. 1:Enable LPAE */ + 0 << 16 | 0 << 0 /* Use TTBR0 for all addresses */ + ); /* Set domain 0 to Client so XN bit works (to prevent prefetches) */ write_dacr(0x5); diff --git a/src/arch/arm/clock.c b/src/arch/arm/clock.c index 8855c75..f1f1fe14 100644 --- a/src/arch/arm/clock.c +++ b/src/arch/arm/clock.c @@ -5,5 +5,5 @@ void set_cntfrq(uint32_t freq) { - __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" :: "r"(freq)); + __asm__ __volatile__("mcr p15, 0, %0, c14, c0, 0\n" ::"r"(freq)); } diff --git a/src/arch/arm/eabi_compat.c b/src/arch/arm/eabi_compat.c index 849fc65..79c38cc 100644 --- a/src/arch/arm/eabi_compat.c +++ b/src/arch/arm/eabi_compat.c @@ -45,11 +45,9 @@ /* Support the alias for the __aeabi_memclr which may assume memory alignment. */ -void __aeabi_memclr4(void *dest, size_t n) - __attribute((alias("__aeabi_memclr"))); +void __aeabi_memclr4(void *dest, size_t n) __attribute((alias("__aeabi_memclr"))); -void __aeabi_memclr8(void *dest, size_t n) - __attribute((alias("__aeabi_memclr"))); +void __aeabi_memclr8(void *dest, size_t n) __attribute((alias("__aeabi_memclr"))); /* Support the routine __aeabi_memclr. */ void __aeabi_memclr(void *dest, size_t n); diff --git a/src/arch/arm/fit_payload.c b/src/arch/arm/fit_payload.c index 19f46a8..46019f5 100644 --- a/src/arch/arm/fit_payload.c +++ b/src/arch/arm/fit_payload.c @@ -28,9 +28,7 @@ } bool fit_payload_arch(struct prog *payload, struct fit_config_node *config, - struct region *kernel, - struct region *fdt, - struct region *initrd) + struct region *kernel, struct region *fdt, struct region *initrd) { void *arg = NULL; diff --git a/src/arch/arm/tables.c b/src/arch/arm/tables.c index 0c68fc7..4fc63e9 100644 --- a/src/arch/arm/tables.c +++ b/src/arch/arm/tables.c @@ -17,8 +17,8 @@ if (!CONFIG(COMMON_CBFS_SPI_WRAPPER)) return; - bootmem_add_range((uintptr_t)_postram_cbfs_cache, - REGION_SIZE(postram_cbfs_cache), BM_MEM_RAMSTAGE); + bootmem_add_range((uintptr_t)_postram_cbfs_cache, REGION_SIZE(postram_cbfs_cache), + BM_MEM_RAMSTAGE); } void lb_arch_add_records(struct lb_header *header) -- To view, visit https://review.coreboot.org/c/coreboot/+/80008?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Icace93f70f024f8690172e030d0922973beb2727 Gerrit-Change-Number: 80008 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: newchange

1 0

[XL] Change in coreboot[main]: acpi: Reformat C files with clang-format v16
by Martin L Roth (Code Review) 16 Jan '24

16 Jan '24

Martin L Roth has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/80007?usp=email ) Change subject: acpi: Reformat C files with clang-format v16 ...................................................................... acpi: Reformat C files with clang-format v16 Reformat only - No functional changes. Change-Id: I5814fc7f04544a4968d3328e19cf67264a5f39d8 Signed-off-by: Martin Roth <gaumless(a)gmail.com> --- M src/acpi/acpi.c M src/acpi/acpi_apic.c M src/acpi/acpi_dmar.c M src/acpi/acpi_gic.c M src/acpi/acpi_hpet.c M src/acpi/acpi_pm.c M src/acpi/acpi_pptt.c M src/acpi/acpigen.c M src/acpi/acpigen_dptf.c M src/acpi/acpigen_dsm.c M src/acpi/acpigen_ps2_keybd.c M src/acpi/acpigen_usb.c M src/acpi/device.c M src/acpi/fadt_filler.c M src/acpi/gnvs.c M src/acpi/soundwire.c 16 files changed, 547 insertions(+), 659 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/07/80007/1 diff --git a/src/acpi/acpi.c b/src/acpi/acpi.c index 5e76916..65014db 100644 --- a/src/acpi/acpi.c +++ b/src/acpi/acpi.c @@ -66,7 +66,7 @@ if (i >= entries_num) { printk(BIOS_ERR, "ACPI: Error: Could not add ACPI table, " - "too many tables.\n"); + "too many tables.\n"); return; } @@ -96,8 +96,8 @@ rsdt->header.checksum = acpi_checksum((u8 *)rsdt, rsdt->header.length); } - printk(BIOS_DEBUG, "ACPI: added table %d/%d, length now %d\n", - i + 1, entries_num, xsdt->header.length); + printk(BIOS_DEBUG, "ACPI: added table %d/%d, length now %d\n", i + 1, entries_num, + xsdt->header.length); } static enum cb_err acpi_fill_header(acpi_header_t *header, const char name[4], @@ -119,8 +119,8 @@ return CB_SUCCESS; } -static int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u64 base, - u16 seg_nr, u8 start, u8 end) +static int acpi_create_mcfg_mmconfig(acpi_mcfg_mmconfig_t *mmconfig, u64 base, u16 seg_nr, + u8 start, u8 end) { memset(mmconfig, 0, sizeof(*mmconfig)); mmconfig->base_address = base; @@ -151,8 +151,8 @@ static unsigned long acpi_fill_mcfg(unsigned long current) { current += acpi_create_mcfg_mmconfig((acpi_mcfg_mmconfig_t *)current, - CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0, - CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); + CONFIG_ECAM_MMCONF_BASE_ADDRESS, 0, 0, + CONFIG_ECAM_MMCONF_BUS_NUMBER - 1); return current; } @@ -162,7 +162,6 @@ acpi_mcfg_t *mcfg = (acpi_mcfg_t *)header; unsigned long current = (unsigned long)mcfg + sizeof(acpi_mcfg_t); - if (acpi_fill_header(header, "MCFG", MCFG, sizeof(acpi_mcfg_t)) != CB_SUCCESS) return; @@ -301,8 +300,8 @@ acpigen_write_name("_CRS"); acpigen_write_resourcetemplate_header(); acpigen_resource_consumer_mmio(base, base + size - 1, - MEM_RSRC_FLAG_MEM_READ_ONLY - | MEM_RSRC_FLAG_MEM_ATTR_CACHE); + MEM_RSRC_FLAG_MEM_READ_ONLY | + MEM_RSRC_FLAG_MEM_ATTR_CACHE); acpigen_write_resourcetemplate_footer(); acpigen_pop_len(); } @@ -331,8 +330,7 @@ ssdt->length = current - (unsigned long)ssdt; } -int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, - u32 flags) +int acpi_create_srat_mem(acpi_srat_mem_t *mem, u8 node, u32 basek, u32 sizek, u32 flags) { mem->type = 1; /* Memory affinity structure */ mem->length = sizeof(acpi_srat_mem_t); @@ -346,8 +344,8 @@ return mem->length; } -int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain, - u16 seg, u8 bus, u8 dev, u8 func, u32 flags) +int acpi_create_srat_gia_pci(acpi_srat_gia_t *gia, u32 proximity_domain, u16 seg, u8 bus, + u8 dev, u8 func, u32 flags) { gia->type = ACPI_SRAT_STRUCTURE_GIA; gia->length = sizeof(acpi_srat_gia_t); @@ -364,8 +362,7 @@ } /* http://www.microsoft.com/whdc/system/sysinternals/sratdwn.mspx */ -void acpi_create_srat(acpi_srat_t *srat, - unsigned long (*acpi_fill_srat)(unsigned long current)) +void acpi_create_srat(acpi_srat_t *srat, unsigned long (*acpi_fill_srat)(unsigned long current)) { acpi_header_t *header = &(srat->header); unsigned long current = (unsigned long)srat + sizeof(acpi_srat_t); @@ -475,8 +472,7 @@ return mpda->length; } -void acpi_create_hmat(acpi_hmat_t *hmat, - unsigned long (*acpi_fill_hmat)(unsigned long current)) +void acpi_create_hmat(acpi_hmat_t *hmat, unsigned long (*acpi_fill_hmat)(unsigned long current)) { acpi_header_t *header = &(hmat->header); unsigned long current = (unsigned long)hmat + sizeof(acpi_hmat_t); @@ -494,8 +490,7 @@ } /* http://h21007.www2.hp.com/portal/download/files/unprot/Itanium/slit.pdf */ -void acpi_create_slit(acpi_slit_t *slit, - unsigned long (*acpi_fill_slit)(unsigned long current)) +void acpi_create_slit(acpi_slit_t *slit, unsigned long (*acpi_fill_slit)(unsigned long current)) { acpi_header_t *header = &(slit->header); unsigned long current = (unsigned long)slit + sizeof(acpi_slit_t); @@ -535,10 +530,10 @@ printk(BIOS_DEBUG, "%s einj_smi = %p\n", __func__, einj_smi); memset(einj_smi, 0, sizeof(acpi_einj_smi_t)); tat = (acpi_einj_trigger_table_t *)((uint8_t *)einj_smi + sizeof(acpi_einj_smi_t)); - tat->header_size = 16; - tat->revision = 0; - tat->table_size = sizeof(acpi_einj_trigger_table_t) + - sizeof(acpi_einj_action_table_t) * actions - 1; + tat->header_size = 16; + tat->revision = 0; + tat->table_size = sizeof(acpi_einj_trigger_table_t) + + sizeof(acpi_einj_action_table_t) * actions - 1; tat->entry_count = actions; printk(BIOS_DEBUG, "%s trigger_action_table = %p\n", __func__, tat); @@ -556,87 +551,68 @@ } acpi_einj_action_table_t default_actions[ACTION_COUNT] = { - [0] = { - .action = BEGIN_INJECT_OP, - .instruction = WRITE_REGISTER_VALUE, - .flags = FLAG_PRESERVE, - .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_state), - .value = 0, - .mask = 0xFFFFFFFF - }, - [1] = { - .action = GET_TRIGGER_ACTION_TABLE, - .instruction = READ_REGISTER, - .flags = FLAG_IGNORE, - .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->trigger_action_table), - .value = 0, - .mask = 0xFFFFFFFFFFFFFFFF - }, - [2] = { - .action = SET_ERROR_TYPE, - .instruction = WRITE_REGISTER, - .flags = FLAG_PRESERVE, - .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->err_inject[0]), - .value = 0, - .mask = 0xFFFFFFFF - }, - [3] = { - .action = GET_ERROR_TYPE, - .instruction = READ_REGISTER, - .flags = FLAG_IGNORE, - .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->err_inj_cap), - .value = 0, - .mask = 0xFFFFFFFF - }, - [4] = { - .action = END_INJECT_OP, - .instruction = WRITE_REGISTER_VALUE, - .flags = FLAG_PRESERVE, - .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_state), - .value = 0, - .mask = 0xFFFFFFFF - - }, - [5] = { - .action = EXECUTE_INJECT_OP, - .instruction = WRITE_REGISTER_VALUE, - .flags = FLAG_PRESERVE, - .reg = EINJ_REG_IO(), - .value = 0x9a, - .mask = 0xFFFF, - }, - [6] = { - .action = CHECK_BUSY_STATUS, - .instruction = READ_REGISTER_VALUE, - .flags = FLAG_IGNORE, - .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_status), - .value = 1, - .mask = 1, - }, - [7] = { - .action = GET_CMD_STATUS, - .instruction = READ_REGISTER, - .flags = FLAG_PRESERVE, - .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->cmd_sts), - .value = 0, - .mask = 0x1fe, - }, - [8] = { - .action = SET_ERROR_TYPE_WITH_ADDRESS, - .instruction = WRITE_REGISTER, - .flags = FLAG_PRESERVE, - .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->setaddrtable), - .value = 1, - .mask = 0xffffffff - } - }; + [0] = {.action = BEGIN_INJECT_OP, + .instruction = WRITE_REGISTER_VALUE, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_state), + .value = 0, + .mask = 0xFFFFFFFF }, + [1] = {.action = GET_TRIGGER_ACTION_TABLE, + .instruction = READ_REGISTER, + .flags = FLAG_IGNORE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->trigger_action_table), + .value = 0, + .mask = 0xFFFFFFFFFFFFFFFF}, + [2] = {.action = SET_ERROR_TYPE, + .instruction = WRITE_REGISTER, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->err_inject[0]), + .value = 0, + .mask = 0xFFFFFFFF }, + [3] = {.action = GET_ERROR_TYPE, + .instruction = READ_REGISTER, + .flags = FLAG_IGNORE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->err_inj_cap), + .value = 0, + .mask = 0xFFFFFFFF }, + [4] = {.action = END_INJECT_OP, + .instruction = WRITE_REGISTER_VALUE, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_state), + .value = 0, + .mask = 0xFFFFFFFF }, + [5] = {.action = EXECUTE_INJECT_OP, + .instruction = WRITE_REGISTER_VALUE, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_IO(), + .value = 0x9a, + .mask = 0xFFFF }, + [6] = {.action = CHECK_BUSY_STATUS, + .instruction = READ_REGISTER_VALUE, + .flags = FLAG_IGNORE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->op_status), + .value = 1, + .mask = 1 }, + [7] = {.action = GET_CMD_STATUS, + .instruction = READ_REGISTER, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->cmd_sts), + .value = 0, + .mask = 0x1fe }, + [8] = {.action = SET_ERROR_TYPE_WITH_ADDRESS, + .instruction = WRITE_REGISTER, + .flags = FLAG_PRESERVE, + .reg = EINJ_REG_MEMORY((u64)(uintptr_t)&einj_smi->setaddrtable), + .value = 1, + .mask = 0xffffffff } + }; einj_smi->err_inj_cap = ACPI_EINJ_DEFAULT_CAP; einj_smi->trigger_action_table = (u64)(uintptr_t)tat; for (i = 0; i < ACTION_COUNT; i++) printk(BIOS_DEBUG, "default_actions[%d].reg.addr is %llx\n", i, - default_actions[i].reg.addr); + default_actions[i].reg.addr); memset((void *)einj, 0, sizeof(*einj)); @@ -646,16 +622,15 @@ inj_header->einj_header_size = sizeof(acpi_injection_header_t); inj_header->entry_count = ACTION_COUNT; - printk(BIOS_DEBUG, "%s einj->action_table = %p\n", - __func__, einj->action_table); + printk(BIOS_DEBUG, "%s einj->action_table = %p\n", __func__, einj->action_table); memcpy((void *)einj->action_table, (void *)default_actions, sizeof(einj->action_table)); header->checksum = acpi_checksum((void *)einj, sizeof(*einj)); } -void acpi_create_vfct(const struct device *device, - acpi_vfct_t *vfct, +void acpi_create_vfct(const struct device *device, acpi_vfct_t *vfct, unsigned long (*acpi_fill_vfct)(const struct device *device, - acpi_vfct_t *vfct_struct, unsigned long current)) + acpi_vfct_t *vfct_struct, + unsigned long current)) { acpi_header_t *header = &(vfct->header); unsigned long current = (unsigned long)vfct + sizeof(acpi_vfct_t); @@ -676,14 +651,10 @@ header->checksum = acpi_checksum((void *)vfct, header->length); } -void acpi_create_ipmi(const struct device *device, - struct acpi_spmi *spmi, - const u16 ipmi_revision, - const acpi_addr_t *addr, - const enum acpi_ipmi_interface_type type, - const s8 gpe_interrupt, - const u32 apic_interrupt, - const u32 uid) +void acpi_create_ipmi(const struct device *device, struct acpi_spmi *spmi, + const u16 ipmi_revision, const acpi_addr_t *addr, + const enum acpi_ipmi_interface_type type, const s8 gpe_interrupt, + const u32 apic_interrupt, const u32 uid) { acpi_header_t *header = &(spmi->header); memset((void *)spmi, 0, sizeof(struct acpi_spmi)); @@ -722,7 +693,7 @@ void acpi_create_ivrs(acpi_ivrs_t *ivrs, unsigned long (*acpi_fill_ivrs)(acpi_ivrs_t *ivrs_struct, - unsigned long current)) + unsigned long current)) { acpi_header_t *header = &(ivrs->header); unsigned long current = (unsigned long)ivrs + sizeof(acpi_ivrs_t); @@ -741,14 +712,15 @@ void acpi_create_crat(struct acpi_crat_header *crat, unsigned long (*acpi_fill_crat)(struct acpi_crat_header *crat_struct, - unsigned long current)) + unsigned long current)) { acpi_header_t *header = &(crat->header); unsigned long current = (unsigned long)crat + sizeof(struct acpi_crat_header); memset((void *)crat, 0, sizeof(struct acpi_crat_header)); - if (acpi_fill_header(header, "CRAT", CRAT, sizeof(struct acpi_crat_header)) != CB_SUCCESS) + if (acpi_fill_header(header, "CRAT", CRAT, sizeof(struct acpi_crat_header)) != + CB_SUCCESS) return; current = acpi_fill_crat(crat, current); @@ -758,10 +730,9 @@ header->checksum = acpi_checksum((void *)crat, header->length); } -static void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, - int port_type, int port_subtype, - acpi_addr_t *address, uint32_t address_size, - const char *device_path) +static void acpi_create_dbg2(acpi_dbg2_header_t *dbg2, int port_type, int port_subtype, + acpi_addr_t *address, uint32_t address_size, + const char *device_path) { uintptr_t current; acpi_dbg2_device_t *device; @@ -806,7 +777,7 @@ current += sizeof(uint32_t); /* Namespace string comes last, use '.' if not provided */ - path = device_path ? : "."; + path = device_path ?: "."; /* Namespace string length includes NULL terminator */ path_len = strlen(path) + 1; namespace = (char *)current; @@ -844,11 +815,7 @@ else return current; - acpi_create_dbg2(dbg2, - ACPI_DBG2_PORT_SERIAL, - subtype, - &address, size, - name); + acpi_create_dbg2(dbg2, ACPI_DBG2_PORT_SERIAL, subtype, &address, size, name); if (dbg2->header.length) { current += dbg2->header.length; @@ -874,8 +841,8 @@ } res = probe_resource(dev, PCI_BASE_ADDRESS_0); if (!res) { - printk(BIOS_ERR, "%s: Unable to find resource for %s\n", - __func__, dev_path(dev)); + printk(BIOS_ERR, "%s: Unable to find resource for %s\n", __func__, + dev_path(dev)); return current; } @@ -889,7 +856,8 @@ return current; } - return acpi_write_dbg2_uart(rsdp, current, space_id, res->base, res->size, access_size, acpi_device_path(dev)); + return acpi_write_dbg2_uart(rsdp, current, space_id, res->base, res->size, access_size, + acpi_device_path(dev)); } unsigned long acpi_pl011_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current, @@ -901,11 +869,10 @@ } unsigned long acpi_16550_mmio32_write_dbg2_uart(acpi_rsdp_t *rsdp, unsigned long current, - uint64_t base, const char *name) + uint64_t base, const char *name) { - return acpi_write_dbg2_uart(rsdp, current, ACPI_ADDRESS_SPACE_MEMORY, base, - 0x100, ACPI_ACCESS_SIZE_DWORD_ACCESS, - name); + return acpi_write_dbg2_uart(rsdp, current, ACPI_ADDRESS_SPACE_MEMORY, base, 0x100, + ACPI_ACCESS_SIZE_DWORD_ACCESS, name); } static void acpi_create_facs(void *header) @@ -949,8 +916,8 @@ header->checksum = acpi_checksum((void *)xsdt, sizeof(acpi_xsdt_t)); } -static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, - acpi_xsdt_t *xsdt, char *oem_id) +static void acpi_write_rsdp(acpi_rsdp_t *rsdp, acpi_rsdt_t *rsdt, acpi_xsdt_t *xsdt, + char *oem_id) { memset(rsdp, 0, sizeof(acpi_rsdp_t)); @@ -979,8 +946,8 @@ rsdp->ext_checksum = acpi_checksum((void *)rsdp, sizeof(acpi_rsdp_t)); } -unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, - acpi_hest_esd_t *esd, u16 type, void *data, u16 data_len) +unsigned long acpi_create_hest_error_source(acpi_hest_t *hest, acpi_hest_esd_t *esd, u16 type, + void *data, u16 data_len) { acpi_header_t *header = &(hest->header); acpi_hest_hen_t *hen; @@ -990,9 +957,9 @@ pos = esd; memset(pos, 0, sizeof(acpi_hest_esd_t)); len = 0; - esd->type = type; /* MCE */ + esd->type = type; /* MCE */ esd->source_id = hest->error_source_count; - esd->flags = 0; /* FIRMWARE_FIRST */ + esd->flags = 0; /* FIRMWARE_FIRST */ esd->enabled = 1; esd->prealloc_erecords = 1; esd->max_section_per_record = 0x1; @@ -1001,14 +968,14 @@ pos = esd + 1; switch (type) { - case 0: /* MCE */ + case 0: /* MCE */ break; - case 1: /* CMC */ + case 1: /* CMC */ hen = (acpi_hest_hen_t *)(pos); memset(pos, 0, sizeof(acpi_hest_hen_t)); - hen->type = 3; /* SCI? */ + hen->type = 3; /* SCI? */ hen->length = sizeof(acpi_hest_hen_t); - hen->conf_we = 0; /* Configuration Write Enable. */ + hen->conf_we = 0; /* Configuration Write Enable. */ hen->poll_interval = 0; hen->vector = 0; hen->sw2poll_threshold_val = 0; @@ -1018,11 +985,11 @@ len += sizeof(acpi_hest_hen_t); pos = hen + 1; break; - case 2: /* NMI */ - case 6: /* AER Root Port */ - case 7: /* AER Endpoint */ - case 8: /* AER Bridge */ - case 9: /* Generic Hardware Error Source. */ + case 2: /* NMI */ + case 6: /* AER Root Port */ + case 7: /* AER Endpoint */ + case 8: /* AER Bridge */ + case 9: /* Generic Hardware Error Source. */ /* TODO: */ break; default: @@ -1040,8 +1007,7 @@ } /* ACPI 4.0 */ -void acpi_write_hest(acpi_hest_t *hest, - unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)) +void acpi_write_hest(acpi_hest_t *hest, unsigned long (*acpi_fill_hest)(acpi_hest_t *hest)) { acpi_header_t *header = &(hest->header); @@ -1076,9 +1042,15 @@ bert->region_length = (size_t)size; } -__weak void arch_fill_fadt(acpi_fadt_t *fadt) { } -__weak void soc_fill_fadt(acpi_fadt_t *fadt) { } -__weak void mainboard_fill_fadt(acpi_fadt_t *fadt) { } +__weak void arch_fill_fadt(acpi_fadt_t *fadt) +{ +} +__weak void soc_fill_fadt(acpi_fadt_t *fadt) +{ +} +__weak void mainboard_fill_fadt(acpi_fadt_t *fadt) +{ +} static acpi_header_t *dsdt; static void acpi_create_fadt(acpi_header_t *header, void *arg1) @@ -1162,7 +1134,7 @@ } unsigned long acpi_gtdt_add_timer_block(unsigned long current, const uint64_t address, - struct acpi_gtdt_timer_entry *timers, size_t number) + struct acpi_gtdt_timer_entry *timers, size_t number) { struct acpi_gtdt_timer_block *block = (struct acpi_gtdt_timer_block *)current; memset(block, 0, sizeof(struct acpi_gtdt_timer_block)); @@ -1171,8 +1143,7 @@ const size_t entries_size = number * sizeof(struct acpi_gtdt_timer_entry); block->header.type = ACPI_GTDT_TYPE_TIMER_BLOCK; - block->header.length = sizeof(struct acpi_gtdt_timer_block) - + entries_size; + block->header.length = sizeof(struct acpi_gtdt_timer_block) + entries_size; block->block_address = address; block->timer_count = number; block->timer_offset = sizeof(struct acpi_gtdt_timer_block); @@ -1286,10 +1257,11 @@ return; spcr->interface_type = acpi_spcr_type(); - assert(serial.type == LB_SERIAL_TYPE_IO_MAPPED - || serial.type == LB_SERIAL_TYPE_MEMORY_MAPPED); + assert(serial.type == LB_SERIAL_TYPE_IO_MAPPED || + serial.type == LB_SERIAL_TYPE_MEMORY_MAPPED); spcr->base_address.space_id = serial.type == LB_SERIAL_TYPE_IO_MAPPED ? - ACPI_ADDRESS_SPACE_IO : ACPI_ADDRESS_SPACE_MEMORY; + ACPI_ADDRESS_SPACE_IO : + ACPI_ADDRESS_SPACE_MEMORY; spcr->base_address.bit_width = serial.regwidth * 8; spcr->base_address.bit_offset = 0; switch (serial.regwidth) { @@ -1360,8 +1332,7 @@ if (dev->ops && dev->ops->acpi_inject_dsdt) dev->ops->acpi_inject_dsdt(dev); current = (unsigned long)acpigen_get_current(); - memcpy((char *)current, - (char *)dsdt_file + sizeof(acpi_header_t), + memcpy((char *)current, (char *)dsdt_file + sizeof(acpi_header_t), dsdt->length - sizeof(acpi_header_t)); current += dsdt->length - sizeof(acpi_header_t); @@ -1402,8 +1373,7 @@ printk(BIOS_SPEW, " "); printk(BIOS_SPEW, " "); for (j = 0; j < num_bytes; j++) - printk(BIOS_SPEW, "%c", - isprint(line[j]) ? line[j] : '.'); + printk(BIOS_SPEW, "%c", isprint(line[j]) ? line[j] : '.'); printk(BIOS_SPEW, "\n"); } } @@ -1439,21 +1409,21 @@ void *args; size_t min_size; } tables[] = { - { acpi_create_dsdt, &dsdt_file, sizeof(acpi_header_t) }, - { acpi_create_fadt, &facs, sizeof(acpi_fadt_t) }, - { acpi_create_slic, &slic_file, sizeof(acpi_header_t) }, - { acpi_create_ssdt_generator, NULL, sizeof(acpi_header_t) }, - { acpi_create_mcfg, NULL, sizeof(acpi_mcfg_t) }, - { acpi_create_tcpa, NULL, sizeof(acpi_tcpa_t) }, - { acpi_create_tpm2, NULL, sizeof(acpi_tpm2_t) }, - { acpi_create_lpit, NULL, sizeof(acpi_lpit_t) }, - { acpi_create_madt, NULL, sizeof(acpi_header_t) }, - { acpi_create_bert, NULL, sizeof(acpi_bert_t) }, - { acpi_create_spcr, NULL, sizeof(acpi_spcr_t) }, - { acpi_create_gtdt, NULL, sizeof(acpi_gtdt_t) }, - { acpi_create_pptt, NULL, sizeof(acpi_pptt_t) }, - { acpi_create_iort, NULL, sizeof(acpi_iort_t) }, - { acpi_create_wdat, NULL, sizeof(acpi_wdat_t) }, + {acpi_create_dsdt, &dsdt_file, sizeof(acpi_header_t)}, + {acpi_create_fadt, &facs, sizeof(acpi_fadt_t) }, + {acpi_create_slic, &slic_file, sizeof(acpi_header_t)}, + {acpi_create_ssdt_generator, NULL, sizeof(acpi_header_t)}, + {acpi_create_mcfg, NULL, sizeof(acpi_mcfg_t) }, + {acpi_create_tcpa, NULL, sizeof(acpi_tcpa_t) }, + {acpi_create_tpm2, NULL, sizeof(acpi_tpm2_t) }, + {acpi_create_lpit, NULL, sizeof(acpi_lpit_t) }, + {acpi_create_madt, NULL, sizeof(acpi_header_t)}, + {acpi_create_bert, NULL, sizeof(acpi_bert_t) }, + {acpi_create_spcr, NULL, sizeof(acpi_spcr_t) }, + {acpi_create_gtdt, NULL, sizeof(acpi_gtdt_t) }, + {acpi_create_pptt, NULL, sizeof(acpi_pptt_t) }, + {acpi_create_iort, NULL, sizeof(acpi_iort_t) }, + {acpi_create_wdat, NULL, sizeof(acpi_wdat_t) }, }; current = start; @@ -1487,7 +1457,8 @@ * Qemu only creates an RSDT. * Add an XSDT based on the existing RSDT entries. */ - acpi_rsdt_t *existing_rsdt = (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address; + acpi_rsdt_t *existing_rsdt = + (acpi_rsdt_t *)(uintptr_t)rsdp->rsdt_address; acpi_write_rsdp(rsdp, existing_rsdt, xsdt, oem_id); acpi_write_xsdt(xsdt, oem_id, oem_table_id); /* @@ -1495,8 +1466,8 @@ * RSDT entries with the same value. */ for (int i = 0; existing_rsdt->entry[i]; i++) - acpi_add_table(rsdp, (void *)(uintptr_t)existing_rsdt->entry[i]); - + acpi_add_table(rsdp, + (void *)(uintptr_t)existing_rsdt->entry[i]); } /* Add BOOT0000 for Linux google firmware driver */ @@ -1537,20 +1508,18 @@ return start; } - if (dsdt_file->length > dsdt_size - || dsdt_file->length < sizeof(acpi_header_t) - || memcmp(dsdt_file->signature, "DSDT", 4) != 0) { + if (dsdt_file->length > dsdt_size || dsdt_file->length < sizeof(acpi_header_t) || + memcmp(dsdt_file->signature, "DSDT", 4) != 0) { printk(BIOS_ERR, "Invalid DSDT file, skipping ACPI tables\n"); cbfs_unmap(dsdt_file); return start; } slic_file = cbfs_map(CONFIG_CBFS_PREFIX "/slic", &slic_size); - if (slic_file - && (slic_file->length > slic_size - || slic_file->length < sizeof(acpi_header_t) - || (memcmp(slic_file->signature, "SLIC", 4) != 0 - && memcmp(slic_file->signature, "MSDM", 4) != 0))) { + if (slic_file && + (slic_file->length > slic_size || slic_file->length < sizeof(acpi_header_t) || + (memcmp(slic_file->signature, "SLIC", 4) != 0 && + memcmp(slic_file->signature, "MSDM", 4) != 0))) { cbfs_unmap(slic_file); slic_file = 0; } @@ -1629,8 +1598,7 @@ for (dev = all_devices; dev; dev = dev->next) { if (dev->ops && dev->ops->write_acpi_tables) { - current = dev->ops->write_acpi_tables(dev, current, - rsdp); + current = dev->ops->write_acpi_tables(dev, current, rsdp); current = acpi_align_current(current); } } @@ -1662,8 +1630,7 @@ return NULL; printk(BIOS_DEBUG, "Checksum 1 passed\n"); - if ((rsdp->revision > 1) && (acpi_checksum((void *)rsdp, - rsdp->length) != 0)) + if ((rsdp->revision > 1) && (acpi_checksum((void *)rsdp, rsdp->length) != 0)) return NULL; printk(BIOS_DEBUG, "Checksum 2 passed all OK\n"); @@ -1693,8 +1660,7 @@ } if (rsdp == NULL) { - printk(BIOS_ALERT, - "No RSDP found, wake up from S3 not possible.\n"); + printk(BIOS_ALERT, "No RSDP found, wake up from S3 not possible.\n"); return NULL; } @@ -1712,18 +1678,16 @@ } if (fadt == NULL) { - printk(BIOS_ALERT, - "No FADT found, wake up from S3 not possible.\n"); + printk(BIOS_ALERT, "No FADT found, wake up from S3 not possible.\n"); return NULL; } printk(BIOS_DEBUG, "FADT found at %p\n", fadt); - facs = (acpi_facs_t *)(uintptr_t)((uint64_t)fadt->x_firmware_ctl_l - | (uint64_t)fadt->x_firmware_ctl_h << 32); + facs = (acpi_facs_t *)(uintptr_t)((uint64_t)fadt->x_firmware_ctl_l | + (uint64_t)fadt->x_firmware_ctl_h << 32); if (facs == NULL) { - printk(BIOS_ALERT, - "No FACS found, wake up from S3 not possible.\n"); + printk(BIOS_ALERT, "No FACS found, wake up from S3 not possible.\n"); return NULL; } diff --git a/src/acpi/acpi_apic.c b/src/acpi/acpi_apic.c index d6937fc..ca07454 100644 --- a/src/acpi/acpi_apic.c +++ b/src/acpi/acpi_apic.c @@ -33,8 +33,8 @@ unsigned long acpi_create_madt_one_lapic(unsigned long current, u32 index, u32 lapic_id) { if (lapic_id <= ACPI_MADT_MAX_LAPIC_ID) - current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, index, - lapic_id); + current += + acpi_create_madt_lapic((acpi_madt_lapic_t *)current, index, lapic_id); else current += acpi_create_madt_lx2apic((acpi_madt_lx2apic_t *)current, index, lapic_id); @@ -81,8 +81,7 @@ return current; } -static int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, - u32 gsi_base) +static int acpi_create_madt_ioapic(acpi_madt_ioapic_t *ioapic, u8 id, u32 addr, u32 gsi_base) { ioapic->type = IO_APIC; /* I/O APIC structure */ ioapic->length = sizeof(acpi_madt_ioapic_t); @@ -108,8 +107,8 @@ return acpi_create_madt_ioapic(ioapic, id, addr, my_base); } -static int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, - u8 bus, u8 source, u32 gsirq, u16 flags) +static int acpi_create_madt_irqoverride(acpi_madt_irqoverride_t *irqoverride, u8 bus, u8 source, + u32 gsirq, u16 flags) { irqoverride->type = IRQ_SOURCE_OVERRIDE; /* Interrupt source override */ irqoverride->length = sizeof(acpi_madt_irqoverride_t); @@ -152,8 +151,8 @@ return current; } -static int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, - u16 flags, u8 lint) +static int acpi_create_madt_lapic_nmi(acpi_madt_lapic_nmi_t *lapic_nmi, u8 cpu, u16 flags, + u8 lint) { lapic_nmi->type = LOCAL_APIC_NMI; /* Local APIC NMI structure */ lapic_nmi->length = sizeof(acpi_madt_lapic_nmi_t); @@ -164,8 +163,8 @@ return lapic_nmi->length; } -static int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, - u16 flags, u8 lint) +static int acpi_create_madt_lx2apic_nmi(acpi_madt_lx2apic_nmi_t *lapic_nmi, u32 cpu, u16 flags, + u8 lint) { lapic_nmi->type = LOCAL_X2APIC_NMI; /* Local APIC NMI structure */ lapic_nmi->length = sizeof(acpi_madt_lx2apic_nmi_t); @@ -186,11 +185,12 @@ /* 1: LINT1 connect to NMI */ /* create all subtables for processors */ current += acpi_create_madt_lapic_nmi((acpi_madt_lapic_nmi_t *)current, - ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1); + ACPI_MADT_LAPIC_NMI_ALL_PROCESSORS, flags, 1); if (!CONFIG(XAPIC_ONLY)) current += acpi_create_madt_lx2apic_nmi((acpi_madt_lx2apic_nmi_t *)current, - ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, flags, 1); + ACPI_MADT_LX2APIC_NMI_ALL_PROCESSORS, + flags, 1); return current; } diff --git a/src/acpi/acpi_dmar.c b/src/acpi/acpi_dmar.c index 9a5ebed..90fca02 100644 --- a/src/acpi/acpi_dmar.c +++ b/src/acpi/acpi_dmar.c @@ -36,8 +36,7 @@ header->checksum = acpi_checksum((void *)dmar, header->length); } -unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, - u16 segment, u64 bar) +unsigned long acpi_create_dmar_drhd(unsigned long current, u8 flags, u16 segment, u64 bar) { dmar_entry_t *drhd = (dmar_entry_t *)current; memset(drhd, 0, sizeof(*drhd)); @@ -50,8 +49,7 @@ return drhd->length; } -unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, - u64 bar, u64 limit) +unsigned long acpi_create_dmar_rmrr(unsigned long current, u16 segment, u64 bar, u64 limit) { dmar_rmrr_entry_t *rmrr = (dmar_rmrr_entry_t *)current; memset(rmrr, 0, sizeof(*rmrr)); @@ -64,8 +62,7 @@ return rmrr->length; } -unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, - u16 segment) +unsigned long acpi_create_dmar_atsr(unsigned long current, u8 flags, u16 segment) { dmar_atsr_entry_t *atsr = (dmar_atsr_entry_t *)current; memset(atsr, 0, sizeof(*atsr)); @@ -77,8 +74,7 @@ return atsr->length; } -unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, - u32 proximity_domain) +unsigned long acpi_create_dmar_rhsa(unsigned long current, u64 base_addr, u32 proximity_domain) { dmar_rhsa_entry_t *rhsa = (dmar_rhsa_entry_t *)current; memset(rhsa, 0, sizeof(*rhsa)); @@ -91,7 +87,7 @@ } unsigned long acpi_create_dmar_andd(unsigned long current, u8 device_number, - const char *device_name) + const char *device_name) { dmar_andd_entry_t *andd = (dmar_andd_entry_t *)current; int andd_len = sizeof(dmar_andd_entry_t) + strlen(device_name) + 1; @@ -141,56 +137,49 @@ satc->length = current - base; } -static unsigned long acpi_create_dmar_ds(unsigned long current, - enum dev_scope_type type, u8 enumeration_id, u8 bus, u8 dev, u8 fn) +static unsigned long acpi_create_dmar_ds(unsigned long current, enum dev_scope_type type, + u8 enumeration_id, u8 bus, u8 dev, u8 fn) { /* we don't support longer paths yet */ const size_t dev_scope_length = sizeof(dev_scope_t) + 2; dev_scope_t *ds = (dev_scope_t *)current; memset(ds, 0, dev_scope_length); - ds->type = type; - ds->length = dev_scope_length; - ds->enumeration = enumeration_id; - ds->start_bus = bus; - ds->path[0].dev = dev; - ds->path[0].fn = fn; + ds->type = type; + ds->length = dev_scope_length; + ds->enumeration = enumeration_id; + ds->start_bus = bus; + ds->path[0].dev = dev; + ds->path[0].fn = fn; return ds->length; } -unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, u8 bus, - u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_pci_br(unsigned long current, u8 bus, u8 dev, u8 fn) { - return acpi_create_dmar_ds(current, - SCOPE_PCI_SUB, 0, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_PCI_SUB, 0, bus, dev, fn); } -unsigned long acpi_create_dmar_ds_pci(unsigned long current, u8 bus, - u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_pci(unsigned long current, u8 bus, u8 dev, u8 fn) { - return acpi_create_dmar_ds(current, - SCOPE_PCI_ENDPOINT, 0, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_PCI_ENDPOINT, 0, bus, dev, fn); } -unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, - u8 enumeration_id, u8 bus, u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_ioapic(unsigned long current, u8 enumeration_id, u8 bus, + u8 dev, u8 fn) { - return acpi_create_dmar_ds(current, - SCOPE_IOAPIC, enumeration_id, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_IOAPIC, enumeration_id, bus, dev, fn); } -unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current, - u32 addr, u8 bus, u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_ioapic_from_hw(unsigned long current, u32 addr, u8 bus, + u8 dev, u8 fn) { u8 enumeration_id = get_ioapic_id((void *)(uintptr_t)addr); - return acpi_create_dmar_ds(current, - SCOPE_IOAPIC, enumeration_id, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_IOAPIC, enumeration_id, bus, dev, fn); } -unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, - u8 enumeration_id, u8 bus, u8 dev, u8 fn) +unsigned long acpi_create_dmar_ds_msi_hpet(unsigned long current, u8 enumeration_id, u8 bus, + u8 dev, u8 fn) { - return acpi_create_dmar_ds(current, - SCOPE_MSI_HPET, enumeration_id, bus, dev, fn); + return acpi_create_dmar_ds(current, SCOPE_MSI_HPET, enumeration_id, bus, dev, fn); } diff --git a/src/acpi/acpi_gic.c b/src/acpi/acpi_gic.c index 5898327..5636f13 100644 --- a/src/acpi/acpi_gic.c +++ b/src/acpi/acpi_gic.c @@ -18,7 +18,7 @@ gicc->parked_address = 0; gicc->physical_base_address = 0; /* V3, no compat mode */ gicc->vgic_maintenance_interrupt = vgic_mi; - gicc->gicr_base_address = 0; /* ignored by OSPM if GICR is present */ + gicc->gicr_base_address = 0; /* ignored by OSPM if GICR is present */ gicc->processor_power_efficiency_class = 0; /* Ignore for now */ /* For platforms implementing GIC V3 the format must be: * Bits [63:40] Must be zero diff --git a/src/acpi/acpi_hpet.c b/src/acpi/acpi_hpet.c index fbf8529..01afc02 100644 --- a/src/acpi/acpi_hpet.c +++ b/src/acpi/acpi_hpet.c @@ -7,7 +7,6 @@ #include <device/mmio.h> #include <version.h> - /* http://www.intel.com/hardwaredesign/hpetspec_1.pdf */ static void acpi_create_hpet(acpi_hpet_t *hpet) { diff --git a/src/acpi/acpi_pm.c b/src/acpi/acpi_pm.c index 722d8f6..79567cd 100644 --- a/src/acpi/acpi_pm.c +++ b/src/acpi/acpi_pm.c @@ -9,9 +9,9 @@ #include <smbios.h> static const char *pm_fetch_failure_msg[PS_CLAIMER_MAX] = { - [PS_CLAIMER_ELOG] = "no event recorded in ELOG.", - [PS_CLAIMER_RTC] = "RTC init aborted.", - [PS_CLAIMER_WAKE] = "wake source unknown.", + [PS_CLAIMER_ELOG] = "no event recorded in ELOG.", + [PS_CLAIMER_RTC] = "RTC init aborted.", + [PS_CLAIMER_WAKE] = "wake source unknown.", }; void __weak mainboard_suspend_resume(void) @@ -54,8 +54,8 @@ if (!*ps) { printk(BIOS_ERR, "No CBMEM_ID_POWER_STATE entry, %s\n", - ps_claimer < PS_CLAIMER_MAX ? - pm_fetch_failure_msg[ps_claimer] : "unknown claimer."); + ps_claimer < PS_CLAIMER_MAX ? pm_fetch_failure_msg[ps_claimer] : + "unknown claimer."); return -1; } return 0; diff --git a/src/acpi/acpi_pptt.c b/src/acpi/acpi_pptt.c index 3822bf7..01bb16e 100644 --- a/src/acpi/acpi_pptt.c +++ b/src/acpi/acpi_pptt.c @@ -11,7 +11,7 @@ */ struct cache_reference { struct pptt_cache *cache; // cache pointer - u32 ref; // and its reference within PPTT + u32 ref; // and its reference within PPTT }; /* @@ -19,7 +19,7 @@ * to keep track of generated caches per topology level. */ struct cache_list { - u32 n_caches; // number of caches in list + u32 n_caches; // number of caches in list struct cache_reference cache_refs[CONFIG_ACPI_PPTT_MAX_CACHES]; // cache reference list }; @@ -78,43 +78,46 @@ return 0; } -static inline void cache_list_append(struct cache_list *cache_list, struct pptt_cache *cache, const u32 ref) +static inline void cache_list_append(struct cache_list *cache_list, struct pptt_cache *cache, + const u32 ref) { printk(BIOS_DEBUG, "acpi: pptt: cache=%p ref=%u\n", cache, ref); cache_list->cache_refs[cache_list->n_caches].cache = cache; - cache_list->cache_refs[cache_list->n_caches].ref = ref; + cache_list->cache_refs[cache_list->n_caches].ref = ref; cache_list->n_caches += 1; } -static u32 new_pptt_cache(unsigned long *current, struct pptt_cache *cache, struct cache_list *cache_list) +static u32 new_pptt_cache(unsigned long *current, struct pptt_cache *cache, + struct cache_list *cache_list) { static u32 unique_cache_id = 1; - u32 current_reference = 0; + u32 current_reference = 0; if ((current_reference = cache_list_ref_of(cache_list, cache)) != 0) return current_reference; if (cache_list->n_caches >= CONFIG_ACPI_PPTT_MAX_CACHES) { - printk(BIOS_WARNING, "acpi: pptt: Too many distinct caches! PPTT incomplete.\n"); + printk(BIOS_WARNING, + "acpi: pptt: Too many distinct caches! PPTT incomplete.\n"); return 0; } acpi_pptt_cache_node_t *cache_node = (acpi_pptt_cache_node_t *)*current; memset(cache_node, 0x0, sizeof(acpi_pptt_cache_node_t)); - cache_node->type = PPTT_NODE_TYPE_CACHE; + cache_node->type = PPTT_NODE_TYPE_CACHE; cache_node->length = sizeof(acpi_pptt_cache_node_t); - cache_node->flags = cache->flags.raw; - cache_node->size = cache->size; - cache_node->n_sets = cache->numsets; + cache_node->flags = cache->flags.raw; + cache_node->size = cache->size; + cache_node->n_sets = cache->numsets; cache_node->associativity = cache->associativity; cache_node->attributes = cache->attributes; - cache_node->line_size = cache->line_size; - cache_node->cache_id = unique_cache_id++; + cache_node->line_size = cache->line_size; + cache_node->cache_id = unique_cache_id++; *current += cache_node->length; @@ -127,35 +130,35 @@ return current_reference; } -static u32 new_pptt_cpu(unsigned long *current, const struct pptt_topology *cpu, const u32 parent_ref, struct cache_list *cache_list) +static u32 new_pptt_cpu(unsigned long *current, const struct pptt_topology *cpu, + const u32 parent_ref, struct cache_list *cache_list) { acpi_pptt_cpu_node_t *cpu_node = (acpi_pptt_cpu_node_t *)*current; - const u32 n_resources = count_resources(cpu->resources); + const u32 n_resources = count_resources(cpu->resources); const u32 structure_length = sizeof(acpi_pptt_cpu_node_t) + (n_resources * sizeof(u32)); memset(cpu_node, 0x0, structure_length); - cpu_node->type = PPTT_NODE_TYPE_CPU; - cpu_node->length = structure_length; - cpu_node->flags = cpu->flags.raw; + cpu_node->type = PPTT_NODE_TYPE_CPU; + cpu_node->length = structure_length; + cpu_node->flags = cpu->flags.raw; cpu_node->processor_id = cpu->processor_id; - cpu_node->parent = parent_ref; + cpu_node->parent = parent_ref; *current += cpu_node->length; for (struct pptt_cpu_resources *it = cpu->resources; it != NULL; it = it->next) - cpu_node->resources[cpu_node->n_resources++] = new_pptt_cache(current, it->cache, cache_list); + cpu_node->resources[cpu_node->n_resources++] = + new_pptt_cache(current, it->cache, cache_list); return node_to_reference(cpu_node); } -static void setup_topology(const struct pptt_topology *node, const u32 parent_ref, unsigned long *current) +static void setup_topology(const struct pptt_topology *node, const u32 parent_ref, + unsigned long *current) { - struct cache_list cache_list = { - .cache_refs = { }, - .n_caches = 0 - }; + struct cache_list cache_list = {.cache_refs = {}, .n_caches = 0}; while (node != NULL) { const u32 cpu_ref = new_pptt_cpu(current, node, parent_ref, &cache_list); diff --git a/src/acpi/acpigen.c b/src/acpi/acpigen.c index 257bd52..4be56ec 100644 --- a/src/acpi/acpigen.c +++ b/src/acpi/acpigen.c @@ -4,7 +4,7 @@ #define ACPIGEN_LENSTACK_SIZE 10 /* If you need to change this, change acpigen_pop_len too */ -#define ACPIGEN_RSVD_PKGLEN_BYTES 3 +#define ACPIGEN_RSVD_PKGLEN_BYTES 3 #include <lib.h> #include <string.h> @@ -43,8 +43,8 @@ /* PkgLength of up to 0x3f can be encoded in one PkgLength byte instead of the reserved 3 bytes. Since only 1 PkgLength byte will be written, the payload data needs to be moved by 2 bytes */ - memmove(&p[ACPIGEN_RSVD_PKGLEN_BYTES - 2], - &p[ACPIGEN_RSVD_PKGLEN_BYTES], payload_len); + memmove(&p[ACPIGEN_RSVD_PKGLEN_BYTES - 2], &p[ACPIGEN_RSVD_PKGLEN_BYTES], + payload_len); /* Adjust the PkgLength to take into account that we only use 1 of the 3 reserved bytes */ len -= 2; @@ -58,8 +58,8 @@ /* PkgLength of up to 0xfff can be encoded in 2 PkgLength bytes instead of the reserved 3 bytes. Since only 2 PkgLength bytes will be written, the payload data needs to be moved by 1 byte */ - memmove(&p[ACPIGEN_RSVD_PKGLEN_BYTES - 1], - &p[ACPIGEN_RSVD_PKGLEN_BYTES], payload_len); + memmove(&p[ACPIGEN_RSVD_PKGLEN_BYTES - 1], &p[ACPIGEN_RSVD_PKGLEN_BYTES], + payload_len); /* Adjust the PkgLength to take into account that we only use 2 of the 3 reserved bytes */ len -= 1; @@ -437,7 +437,7 @@ /* Processor() operator is deprecated as of ACPI 6.0, use Device() instead. */ void acpigen_write_processor(u8 cpuindex, u32 pblock_addr, u8 pblock_len) { -/* + /* Processor (\_SB.CPcpuindex, cpuindex, pblock_addr, pblock_len) { */ @@ -707,7 +707,7 @@ void acpigen_write_empty_PCT(void) { -/* + /* Name (_PCT, Package (0x02) { ResourceTemplate () @@ -729,27 +729,25 @@ } }) */ - static char stream[] = { - /* 00000030 "0._PCT.," */ - 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, - /* 00000038 "........" */ - 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, - /* 00000040 "........" */ - 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - /* 00000048 "....y..." */ - 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, - /* 00000050 "........" */ - 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, - /* 00000058 "........" */ - 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x00, 0x79, 0x00 - }; + static char stream[] = {/* 00000030 "0._PCT.," */ + 0x08, 0x5F, 0x50, 0x43, 0x54, 0x12, 0x2C, + /* 00000038 "........" */ + 0x02, 0x11, 0x14, 0x0A, 0x11, 0x82, 0x0C, 0x00, + /* 00000040 "........" */ + 0x7F, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, + /* 00000048 "....y..." */ + 0x00, 0x00, 0x00, 0x00, 0x79, 0x00, 0x11, 0x14, + /* 00000050 "........" */ + 0x0A, 0x11, 0x82, 0x0C, 0x00, 0x7F, 0x00, 0x00, + /* 00000058 "........" */ + 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x79, + 0x00}; acpigen_emit_stream(stream, ARRAY_SIZE(stream)); } void acpigen_write_PTC(uint8_t duty_width, uint8_t duty_offset, uint16_t p_cnt) { -/* + /* Name (_PTC, Package (0x02) { ResourceTemplate () @@ -772,11 +770,11 @@ }) */ acpi_addr_t addr = { - .bit_width = duty_width, - .bit_offset = duty_offset, + .bit_width = duty_width, + .bit_offset = duty_offset, .access_size = ACPI_ACCESS_SIZE_UNDEFINED, - .addrl = p_cnt, - .addrh = 0, + .addrl = p_cnt, + .addrh = 0, }; if (addr.addrl != 0) @@ -956,7 +954,7 @@ */ void acpigen_write_PPC(u8 nr) { -/* + /* Method (_PPC, 0, NotSerialized) { Return (nr) @@ -975,7 +973,7 @@ */ void acpigen_write_PPC_NVS(void) { -/* + /* Method (_PPC, 0, NotSerialized) { Return (PPCM) @@ -990,7 +988,7 @@ void acpigen_write_TPC(const char *gnvs_tpc_limit) { -/* + /* // Sample _TPC method Method (_TPC, 0, NotSerialized) { @@ -1038,10 +1036,11 @@ acpigen_write_name("_PSS"); acpigen_write_package(nentries); for (pstate = 0; pstate < nentries; pstate++) { - acpigen_write_PSS_package( - pstate_values->core_freq, pstate_values->power, - pstate_values->transition_latency, pstate_values->bus_master_latency, - pstate_values->control_value, pstate_values->status_value); + acpigen_write_PSS_package(pstate_values->core_freq, pstate_values->power, + pstate_values->transition_latency, + pstate_values->bus_master_latency, + pstate_values->control_value, + pstate_values->status_value); pstate_values++; } @@ -1053,8 +1052,8 @@ acpigen_write_name("_PSD"); acpigen_write_package(1); acpigen_write_package(5); - acpigen_write_byte(5); // 5 values - acpigen_write_byte(0); // revision 0 + acpigen_write_byte(5); // 5 values + acpigen_write_byte(0); // revision 0 acpigen_write_dword(domain); acpigen_write_dword(coordtype); acpigen_write_dword(numprocs); @@ -1076,7 +1075,7 @@ { int i; acpigen_write_name("_CST"); - acpigen_write_package(nentries+1); + acpigen_write_package(nentries + 1); acpigen_write_integer(nentries); for (i = 0; i < nentries; i++) @@ -1085,14 +1084,13 @@ acpigen_pop_len(); } -void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, - u32 index) +void acpigen_write_CSD_package(u32 domain, u32 numprocs, CSD_coord coordtype, u32 index) { acpigen_write_name("_CSD"); acpigen_write_package(1); acpigen_write_package(6); - acpigen_write_integer(6); // 6 values - acpigen_write_byte(0); // revision 0 + acpigen_write_integer(6); // 6 values + acpigen_write_byte(0); // revision 0 acpigen_write_dword(domain); acpigen_write_dword(coordtype); acpigen_write_dword(numprocs); @@ -1103,7 +1101,7 @@ void acpigen_write_TSS_package(int entries, acpi_tstate_t *tstate_list) { -/* + /* Sample _TSS package with 100% and 50% duty cycles Name (_TSS, Package (0x02) { @@ -1136,8 +1134,8 @@ acpigen_write_name("_TSD"); acpigen_write_package(1); acpigen_write_package(5); - acpigen_write_byte(5); // 5 values - acpigen_write_byte(0); // revision 0 + acpigen_write_byte(5); // 5 values + acpigen_write_byte(0); // revision 0 acpigen_write_dword(domain); acpigen_write_dword(coordtype); acpigen_write_dword(numprocs); @@ -1165,15 +1163,15 @@ static void acpigen_write_register(const acpi_addr_t *addr) { - acpigen_emit_byte(0x82); /* Register Descriptor */ - acpigen_emit_byte(0x0c); /* Register Length 7:0 */ - acpigen_emit_byte(0x00); /* Register Length 15:8 */ - acpigen_emit_byte(addr->space_id); /* Address Space ID */ - acpigen_emit_byte(addr->bit_width); /* Register Bit Width */ - acpigen_emit_byte(addr->bit_offset); /* Register Bit Offset */ - acpigen_emit_byte(addr->access_size); /* Register Access Size */ - acpigen_emit_dword(addr->addrl); /* Register Address Low */ - acpigen_emit_dword(addr->addrh); /* Register Address High */ + acpigen_emit_byte(0x82); /* Register Descriptor */ + acpigen_emit_byte(0x0c); /* Register Length 7:0 */ + acpigen_emit_byte(0x00); /* Register Length 15:8 */ + acpigen_emit_byte(addr->space_id); /* Address Space ID */ + acpigen_emit_byte(addr->bit_width); /* Register Bit Width */ + acpigen_emit_byte(addr->bit_offset); /* Register Bit Offset */ + acpigen_emit_byte(addr->access_size); /* Register Access Size */ + acpigen_emit_dword(addr->addrl); /* Register Address Low */ + acpigen_emit_dword(addr->addrh); /* Register Address High */ } void acpigen_write_register_resource(const acpi_addr_t *addr) @@ -1285,16 +1283,14 @@ acpigen_write_resourcetemplate_header(); /* Add reserved memory ranges. */ - search_global_resources( - IORESOURCE_MEM | IORESOURCE_RESERVE, - IORESOURCE_MEM | IORESOURCE_RESERVE, - acpigen_add_mainboard_rsvd_mem32, 0); + search_global_resources(IORESOURCE_MEM | IORESOURCE_RESERVE, + IORESOURCE_MEM | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_mem32, 0); /* Add reserved io ranges. */ - search_global_resources( - IORESOURCE_IO | IORESOURCE_RESERVE, - IORESOURCE_IO | IORESOURCE_RESERVE, - acpigen_add_mainboard_rsvd_io, 0); + search_global_resources(IORESOURCE_IO | IORESOURCE_RESERVE, + IORESOURCE_IO | IORESOURCE_RESERVE, + acpigen_add_mainboard_rsvd_io, 0); acpigen_write_resourcetemplate_footer(); } @@ -1354,8 +1350,7 @@ void acpigen_write_uuid(const char *uuid) { uint8_t buf[UUID_LEN]; - size_t i, order[UUID_LEN] = { 3, 2, 1, 0, 5, 4, 7, 6, - 8, 9, 10, 11, 12, 13, 14, 15 }; + size_t i, order[UUID_LEN] = {3, 2, 1, 0, 5, 4, 7, 6, 8, 9, 10, 11, 12, 13, 14, 15}; /* Parse UUID string into bytes */ if (hexstrtobin(uuid, buf, UUID_LEN) < UUID_LEN) @@ -1381,14 +1376,14 @@ * PowerResource (name, level, order) */ void acpigen_write_power_res(const char *name, uint8_t level, uint16_t order, - const char * const dev_states[], size_t dev_states_count) + const char *const dev_states[], size_t dev_states_count) { size_t i; for (i = 0; i < dev_states_count; i++) { acpigen_write_name(dev_states[i]); acpigen_write_package(1); acpigen_emit_simple_namestring(name); - acpigen_pop_len(); /* Package */ + acpigen_pop_len(); /* Package */ } acpigen_emit_ext_op(POWER_RES_OP); @@ -1538,8 +1533,7 @@ /* Concatenate (str1, res, tmp_res) Store(tmp_res, DEBUG) */ -void acpigen_write_debug_concatenate_string_op(const char *str, uint8_t res, - uint8_t tmp_res) +void acpigen_write_debug_concatenate_string_op(const char *str, uint8_t res, uint8_t tmp_res) { acpigen_concatenate_string_op(str, res, tmp_res); acpigen_write_debug_op(tmp_res); @@ -1873,14 +1867,13 @@ if (id->callbacks[i]) id->callbacks[i](id->arg); - acpigen_write_if_end(); /* If */ + acpigen_write_if_end(); /* If */ } /* Default case: Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); acpigen_write_if_end(); /* If (LEqual (Local0, ToUUID(uuid))) */ - } /* @@ -1933,7 +1926,7 @@ /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); - acpigen_pop_len(); /* Method _DSM */ + acpigen_pop_len(); /* Method _DSM */ } void acpigen_write_CPPC_package(const struct cppc_config *config) @@ -1975,8 +1968,8 @@ void acpigen_write_CPPC_method(void) { char pscope[16]; - snprintf(pscope, sizeof(pscope), - "\\_SB." CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, 0); + snprintf(pscope, sizeof(pscope), "\\_SB." CONFIG_ACPI_CPU_STRING "." CPPC_PACKAGE_NAME, + 0); acpigen_write_method("_CPC", 0); acpigen_emit_byte(RETURN_OP); @@ -2280,66 +2273,67 @@ void acpigen_resource_producer_bus_number(u16 bus_base, u16 bus_limit) { acpigen_resource_word(RSRC_TYPE_BUS, /* res_type */ - ADDR_SPACE_GENERAL_FLAG_MAX_FIXED - | ADDR_SPACE_GENERAL_FLAG_MIN_FIXED - | ADDR_SPACE_GENERAL_FLAG_DEC_POS - | ADDR_SPACE_GENERAL_FLAG_PRODUCER, /* gen_flags */ - BUS_NUM_RANGE_RESOURCE_FLAG, /* type_flags */ - 0, /* gran */ - bus_base, /* range_min */ - bus_limit, /* range_max */ - 0x0, /* translation */ - bus_limit - bus_base + 1); /* length */ + ADDR_SPACE_GENERAL_FLAG_MAX_FIXED | + ADDR_SPACE_GENERAL_FLAG_MIN_FIXED | + ADDR_SPACE_GENERAL_FLAG_DEC_POS | + ADDR_SPACE_GENERAL_FLAG_PRODUCER, /* gen_flags */ + BUS_NUM_RANGE_RESOURCE_FLAG, /* type_flags */ + 0, /* gran */ + bus_base, /* range_min */ + bus_limit, /* range_max */ + 0x0, /* translation */ + bus_limit - bus_base + 1); /* length */ } void acpigen_resource_producer_io(u16 io_base, u16 io_limit) { acpigen_resource_dword(RSRC_TYPE_IO, /* res_type */ - ADDR_SPACE_GENERAL_FLAG_MAX_FIXED - | ADDR_SPACE_GENERAL_FLAG_MIN_FIXED - | ADDR_SPACE_GENERAL_FLAG_DEC_POS - | ADDR_SPACE_GENERAL_FLAG_PRODUCER, /* gen_flags */ - IO_RSRC_FLAG_ENTIRE_RANGE, /* type_flags */ - 0, /* gran */ - io_base, /* range_min */ - io_limit, /* range_max */ - 0x0, /* translation */ - io_limit - io_base + 1); /* length */ + ADDR_SPACE_GENERAL_FLAG_MAX_FIXED | + ADDR_SPACE_GENERAL_FLAG_MIN_FIXED | + ADDR_SPACE_GENERAL_FLAG_DEC_POS | + ADDR_SPACE_GENERAL_FLAG_PRODUCER, /* gen_flags */ + IO_RSRC_FLAG_ENTIRE_RANGE, /* type_flags */ + 0, /* gran */ + io_base, /* range_min */ + io_limit, /* range_max */ + 0x0, /* translation */ + io_limit - io_base + 1); /* length */ } static void acpigen_resource_mmio32(u32 mmio_base, u32 mmio_limit, u16 gen_flags, u16 type_flags) { - acpigen_resource_dword(RSRC_TYPE_MEM, /* res_type */ - gen_flags, /* gen_flags */ - type_flags, /* type_flags */ - 0, /* gran */ - mmio_base, /* range_min */ - mmio_limit, /* range_max */ - 0x0, /* translation */ + acpigen_resource_dword(RSRC_TYPE_MEM, /* res_type */ + gen_flags, /* gen_flags */ + type_flags, /* type_flags */ + 0, /* gran */ + mmio_base, /* range_min */ + mmio_limit, /* range_max */ + 0x0, /* translation */ mmio_limit - mmio_base + 1); /* length */ } static void acpigen_resource_mmio64(u64 mmio_base, u64 mmio_limit, u16 gen_flags, u16 type_flags) { - acpigen_resource_qword(RSRC_TYPE_MEM, /* res_type */ - gen_flags, /* gen_flags */ - type_flags, /* type_flags */ - 0, /* gran */ - mmio_base, /* range_min */ - mmio_limit, /* range_max */ - 0x0, /* translation */ + acpigen_resource_qword(RSRC_TYPE_MEM, /* res_type */ + gen_flags, /* gen_flags */ + type_flags, /* type_flags */ + 0, /* gran */ + mmio_base, /* range_min */ + mmio_limit, /* range_max */ + 0x0, /* translation */ mmio_limit - mmio_base + 1); /* length */ } -static void acpigen_resource_mmio(u64 mmio_base, u64 mmio_limit, bool is_producer, u16 type_flags) +static void acpigen_resource_mmio(u64 mmio_base, u64 mmio_limit, bool is_producer, + u16 type_flags) { - const u16 gen_flags = ADDR_SPACE_GENERAL_FLAG_MAX_FIXED - | ADDR_SPACE_GENERAL_FLAG_MIN_FIXED - | ADDR_SPACE_GENERAL_FLAG_DEC_POS - | (is_producer ? ADDR_SPACE_GENERAL_FLAG_PRODUCER - : ADDR_SPACE_GENERAL_FLAG_CONSUMER); + const u16 gen_flags = ADDR_SPACE_GENERAL_FLAG_MAX_FIXED | + ADDR_SPACE_GENERAL_FLAG_MIN_FIXED | + ADDR_SPACE_GENERAL_FLAG_DEC_POS | + (is_producer ? ADDR_SPACE_GENERAL_FLAG_PRODUCER : + ADDR_SPACE_GENERAL_FLAG_CONSUMER); if (mmio_base < 4ULL * GiB && mmio_limit < 4ULL * GiB) acpigen_resource_mmio32(mmio_base, mmio_limit, gen_flags, type_flags); @@ -2497,8 +2491,7 @@ if (name) { acpigen_write_if_lequal_op_op(LOCAL7_OP, ZERO_OP); - acpigen_write_debug_sprintf("WARN: Wait loop timeout for variable %s", - name); + acpigen_write_debug_sprintf("WARN: Wait loop timeout for variable %s", name); acpigen_pop_len(); /* If */ } } @@ -2511,8 +2504,8 @@ assert(!(enable_s4 && CONFIG(DISABLE_ACPI_HIBERNATE))); acpigen_write_scope("\\"); - uint32_t sleep_enable = (enable_s1 << 0) | (enable_s2 << 1) - | (enable_s3 << 2) | (enable_s4 << 3); + uint32_t sleep_enable = (enable_s1 << 0) | (enable_s2 << 1) | (enable_s3 << 2) | + (enable_s4 << 3); acpigen_write_name_dword("OSFG", sleep_enable); acpigen_pop_len(); } diff --git a/src/acpi/acpigen_dptf.c b/src/acpi/acpigen_dptf.c index aa8de1e..6b3cb8f 100644 --- a/src/acpi/acpigen_dptf.c +++ b/src/acpi/acpigen_dptf.c @@ -6,23 +6,23 @@ #include <stdint.h> /* Defaults */ -#define DEFAULT_RAW_UNIT "ma" +#define DEFAULT_RAW_UNIT "ma" /* DPTF-specific UUIDs */ -#define DPTF_PASSIVE_POLICY_1_0_UUID "42A441D6-AE6A-462B-A84B-4A8CE79027D3" -#define DPTF_CRITICAL_POLICY_UUID "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" -#define DPTF_ACTIVE_POLICY_UUID "3A95C389-E4B8-4629-A526-C52C88626BAE" +#define DPTF_PASSIVE_POLICY_1_0_UUID "42A441D6-AE6A-462B-A84B-4A8CE79027D3" +#define DPTF_CRITICAL_POLICY_UUID "97C68AE7-15FA-499c-B8C9-5DA81D606E0A" +#define DPTF_ACTIVE_POLICY_UUID "3A95C389-E4B8-4629-A526-C52C88626BAE" enum { - ART_REVISION = 0, - DEFAULT_PRIORITY = 100, - DEFAULT_TRIP_POINT = 0xFFFFFFFFull, - DEFAULT_WEIGHT = 100, - DPTF_MAX_ART_THRESHOLDS = 10, - FPS_REVISION = 0, - PPCC_REVISION = 2, - RAPL_PL1_INDEX = 0, - RAPL_PL2_INDEX = 1, + ART_REVISION = 0, + DEFAULT_PRIORITY = 100, + DEFAULT_TRIP_POINT = 0xFFFFFFFFull, + DEFAULT_WEIGHT = 100, + DPTF_MAX_ART_THRESHOLDS = 10, + FPS_REVISION = 0, + PPCC_REVISION = 2, + RAPL_PL1_INDEX = 0, + RAPL_PL2_INDEX = 1, }; /* Convert degrees C to 1/10 degree Kelvin for ACPI */ @@ -203,16 +203,16 @@ break; snprintf(name, sizeof(name), "_AC%1X", j); - write_simple_return_method(name, to_acpi_temp( - policies[i].thresholds[j].temp)); + write_simple_return_method( + name, to_acpi_temp(policies[i].thresholds[j].temp)); } acpigen_pop_len(); /* Scope */ } } -void dptf_write_active_policies(const struct dptf_active_policy *policies, - int max_count, bool dptf_multifan_support) +void dptf_write_active_policies(const struct dptf_active_policy *policies, int max_count, + bool dptf_multifan_support) { write_active_relationship_table(policies, max_count, dptf_multifan_support); write_active_cooling_methods(policies, max_count); @@ -313,8 +313,9 @@ dptf_write_scope(policies[i].source); /* Choose _CRT or _HOT */ - write_simple_return_method(policies[i].type == DPTF_CRITICAL_SHUTDOWN ? - "_CRT" : "_HOT", to_acpi_temp(policies[i].temp)); + write_simple_return_method(policies[i].type == DPTF_CRITICAL_SHUTDOWN ? "_CRT" : + "_HOT", + to_acpi_temp(policies[i].temp)); acpigen_pop_len(); /* Scope */ } @@ -360,7 +361,7 @@ } int dptf_write_fan_perf_fps(uint8_t percent, uint16_t power, uint16_t speed, - uint16_t noise_level) + uint16_t noise_level) { /* * Some _FPS tables do include a last entry where Percent is 0, but Power is @@ -381,7 +382,7 @@ } void dptf_write_fan_perf(const struct dptf_fan_perf *states, int max_count, - enum dptf_participant participant) + enum dptf_participant participant) { char *pkg_count; int i; @@ -395,12 +396,12 @@ acpigen_write_name("_FPS"); pkg_count = acpigen_write_package(1); /* 1 for Revision */ - acpigen_write_integer(FPS_REVISION); /* revision */ + acpigen_write_integer(FPS_REVISION); /* revision */ for (i = 0; i < max_count; ++i) { (*pkg_count)++; - if (dptf_write_fan_perf_fps(states[i].percent, states[i].power, - states[i].speed, states[i].noise_level)) + if (dptf_write_fan_perf_fps(states[i].percent, states[i].power, states[i].speed, + states[i].noise_level)) break; } @@ -408,10 +409,9 @@ acpigen_pop_len(); /* Scope */ } -void dptf_write_multifan_perf( - const struct dptf_multifan_perf - states[DPTF_MAX_FAN_PARTICIPANTS][DPTF_MAX_FAN_PERF_STATES], - int max_count, enum dptf_participant participant, int fan_num) +void dptf_write_multifan_perf(const struct dptf_multifan_perf states[DPTF_MAX_FAN_PARTICIPANTS] + [DPTF_MAX_FAN_PERF_STATES], + int max_count, enum dptf_participant participant, int fan_num) { char *pkg_count; int i; @@ -425,12 +425,13 @@ acpigen_write_name("_FPS"); pkg_count = acpigen_write_package(1); /* 1 for Revision */ - acpigen_write_integer(FPS_REVISION); /* revision */ + acpigen_write_integer(FPS_REVISION); /* revision */ for (i = 0; i < max_count; ++i) { (*pkg_count)++; - if (dptf_write_fan_perf_fps(states[fan_num][i].percent, states[fan_num][i].power, - states[fan_num][i].speed, states[fan_num][i].noise_level)) + if (dptf_write_fan_perf_fps(states[fan_num][i].percent, + states[fan_num][i].power, states[fan_num][i].speed, + states[fan_num][i].noise_level)) break; } diff --git a/src/acpi/acpigen_dsm.c b/src/acpi/acpigen_dsm.c index d51d643..0b8e903 100644 --- a/src/acpi/acpigen_dsm.c +++ b/src/acpi/acpigen_dsm.c @@ -5,7 +5,7 @@ /* ------------------- I2C HID DSM ---------------------------- */ -#define ACPI_DSM_I2C_HID_UUID "3CDFF6F7-4267-4555-AD05-B30A3D8938DE" +#define ACPI_DSM_I2C_HID_UUID "3CDFF6F7-4267-4555-AD05-B30A3D8938DE" /* I2C HID currently supports revision 1 only, for which, only 1 additional * function is supported. Thus, the query function should return 0x3: @@ -26,7 +26,7 @@ acpigen_write_else(); /* Return (Buffer (One) { 0x0 }) */ acpigen_write_return_singleton_buffer(0x0); - acpigen_pop_len(); /* Pop : Else */ + acpigen_pop_len(); /* Pop : Else */ } static void i2c_hid_func1_cb(void *arg) @@ -48,7 +48,7 @@ /* ------------------- End: I2C HID DSM ------------------------- */ -#define USB_DSM_UUID "CE2EE385-00E6-48CB-9F05-2EDB927C4899" +#define USB_DSM_UUID "CE2EE385-00E6-48CB-9F05-2EDB927C4899" static void usb_dsm_func5_cb(void *arg) { @@ -57,16 +57,11 @@ } static void (*usb_dsm_callbacks[6])(void *) = { - NULL, - NULL, - NULL, - NULL, - NULL, - usb_dsm_func5_cb, + NULL, NULL, NULL, NULL, NULL, usb_dsm_func5_cb, }; void acpigen_write_dsm_usb(struct dsm_usb_config *config) { - acpigen_write_dsm(USB_DSM_UUID, usb_dsm_callbacks, - ARRAY_SIZE(usb_dsm_callbacks), config); + acpigen_write_dsm(USB_DSM_UUID, usb_dsm_callbacks, ARRAY_SIZE(usb_dsm_callbacks), + config); } diff --git a/src/acpi/acpigen_ps2_keybd.c b/src/acpi/acpigen_ps2_keybd.c index 67e92a9..7941994 100644 --- a/src/acpi/acpigen_ps2_keybd.c +++ b/src/acpi/acpigen_ps2_keybd.c @@ -8,25 +8,15 @@ #include <stdint.h> #define KEYMAP(scancode, keycode) (((uint32_t)(scancode) << 16) | (keycode & 0xFFFF)) -#define SCANCODE(keymap) ((keymap >> 16) & 0xFFFF) +#define SCANCODE(keymap) ((keymap >> 16) & 0xFFFF) /* Possible keymaps for function keys in the top row */ static const uint32_t function_keymaps[] = { - KEYMAP(0x3b, KEY_F1), - KEYMAP(0x3c, KEY_F2), - KEYMAP(0x3d, KEY_F3), - KEYMAP(0x3e, KEY_F4), - KEYMAP(0x3f, KEY_F5), - KEYMAP(0x40, KEY_F6), - KEYMAP(0x41, KEY_F7), - KEYMAP(0x42, KEY_F8), - KEYMAP(0x43, KEY_F9), - KEYMAP(0x44, KEY_F10), - KEYMAP(0x57, KEY_F11), - KEYMAP(0x58, KEY_F12), - KEYMAP(0x59, KEY_F13), - KEYMAP(0x5a, KEY_F14), - KEYMAP(0x5b, KEY_F15), + KEYMAP(0x3b, KEY_F1), KEYMAP(0x3c, KEY_F2), KEYMAP(0x3d, KEY_F3), + KEYMAP(0x3e, KEY_F4), KEYMAP(0x3f, KEY_F5), KEYMAP(0x40, KEY_F6), + KEYMAP(0x41, KEY_F7), KEYMAP(0x42, KEY_F8), KEYMAP(0x43, KEY_F9), + KEYMAP(0x44, KEY_F10), KEYMAP(0x57, KEY_F11), KEYMAP(0x58, KEY_F12), + KEYMAP(0x59, KEY_F13), KEYMAP(0x5a, KEY_F14), KEYMAP(0x5b, KEY_F15), }; /* @@ -35,27 +25,27 @@ * The scancodes are true / condensed 1 byte scancodes from set-1 */ static const uint32_t action_keymaps[] = { - [PS2_KEY_BACK] = KEYMAP(0xea, KEY_BACK), /* e06a */ - [PS2_KEY_FORWARD] = KEYMAP(0xe9, KEY_FORWARD), /* e069 */ - [PS2_KEY_REFRESH] = KEYMAP(0xe7, KEY_REFRESH), /* e067 */ - [PS2_KEY_FULLSCREEN] = KEYMAP(0x91, KEY_FULL_SCREEN), /* e011 */ - [PS2_KEY_OVERVIEW] = KEYMAP(0x92, KEY_SCALE), /* e012 */ - [PS2_KEY_VOL_MUTE] = KEYMAP(0xa0, KEY_MUTE), /* e020 */ - [PS2_KEY_VOL_DOWN] = KEYMAP(0xae, KEY_VOLUMEDOWN), /* e02e */ - [PS2_KEY_VOL_UP] = KEYMAP(0xb0, KEY_VOLUMEUP), /* e030 */ - [PS2_KEY_PLAY_PAUSE] = KEYMAP(0x9a, KEY_PLAYPAUSE), /* e01a */ - [PS2_KEY_NEXT_TRACK] = KEYMAP(0x99, KEY_NEXTSONG), /* e019 */ - [PS2_KEY_PREV_TRACK] = KEYMAP(0x90, KEY_PREVIOUSSONG), /* e010 */ - [PS2_KEY_SNAPSHOT] = KEYMAP(0x93, KEY_SYSRQ), /* e013 */ - [PS2_KEY_BRIGHTNESS_DOWN] = KEYMAP(0x94, KEY_BRIGHTNESSDOWN), /* e014 */ - [PS2_KEY_BRIGHTNESS_UP] = KEYMAP(0x95, KEY_BRIGHTNESSUP), /* e015 */ - [PS2_KEY_KBD_BKLIGHT_DOWN] = KEYMAP(0x97, KEY_KBDILLUMDOWN), /* e017 */ - [PS2_KEY_KBD_BKLIGHT_UP] = KEYMAP(0x98, KEY_KBDILLUMUP), /* e018 */ - [PS2_KEY_PRIVACY_SCRN_TOGGLE] = KEYMAP(0x96, /* e016 */ - KEY_PRIVACY_SCREEN_TOGGLE), - [PS2_KEY_MICMUTE] = KEYMAP(0x9b, KEY_MICMUTE), /* e01b */ - [PS2_KEY_KBD_BKLIGHT_TOGGLE] = KEYMAP(0x9e, KEY_KBDILLUMTOGGLE), /* e01e */ - [PS2_KEY_MENU] = KEYMAP(0xdd, KEY_CONTROLPANEL), /* e0d5 */ + [PS2_KEY_BACK] = KEYMAP(0xea, KEY_BACK), /* e06a */ + [PS2_KEY_FORWARD] = KEYMAP(0xe9, KEY_FORWARD), /* e069 */ + [PS2_KEY_REFRESH] = KEYMAP(0xe7, KEY_REFRESH), /* e067 */ + [PS2_KEY_FULLSCREEN] = KEYMAP(0x91, KEY_FULL_SCREEN), /* e011 */ + [PS2_KEY_OVERVIEW] = KEYMAP(0x92, KEY_SCALE), /* e012 */ + [PS2_KEY_VOL_MUTE] = KEYMAP(0xa0, KEY_MUTE), /* e020 */ + [PS2_KEY_VOL_DOWN] = KEYMAP(0xae, KEY_VOLUMEDOWN), /* e02e */ + [PS2_KEY_VOL_UP] = KEYMAP(0xb0, KEY_VOLUMEUP), /* e030 */ + [PS2_KEY_PLAY_PAUSE] = KEYMAP(0x9a, KEY_PLAYPAUSE), /* e01a */ + [PS2_KEY_NEXT_TRACK] = KEYMAP(0x99, KEY_NEXTSONG), /* e019 */ + [PS2_KEY_PREV_TRACK] = KEYMAP(0x90, KEY_PREVIOUSSONG), /* e010 */ + [PS2_KEY_SNAPSHOT] = KEYMAP(0x93, KEY_SYSRQ), /* e013 */ + [PS2_KEY_BRIGHTNESS_DOWN] = KEYMAP(0x94, KEY_BRIGHTNESSDOWN), /* e014 */ + [PS2_KEY_BRIGHTNESS_UP] = KEYMAP(0x95, KEY_BRIGHTNESSUP), /* e015 */ + [PS2_KEY_KBD_BKLIGHT_DOWN] = KEYMAP(0x97, KEY_KBDILLUMDOWN), /* e017 */ + [PS2_KEY_KBD_BKLIGHT_UP] = KEYMAP(0x98, KEY_KBDILLUMUP), /* e018 */ + [PS2_KEY_PRIVACY_SCRN_TOGGLE] = KEYMAP(0x96, /* e016 */ + KEY_PRIVACY_SCREEN_TOGGLE), + [PS2_KEY_MICMUTE] = KEYMAP(0x9b, KEY_MICMUTE), /* e01b */ + [PS2_KEY_KBD_BKLIGHT_TOGGLE] = KEYMAP(0x9e, KEY_KBDILLUMTOGGLE), /* e01e */ + [PS2_KEY_MENU] = KEYMAP(0xdd, KEY_CONTROLPANEL), /* e0d5 */ }; /* Keymap for numeric keypad keys */ @@ -110,7 +100,7 @@ KEYMAP(0x0b, KEY_0), KEYMAP(0x0c, KEY_MINUS), KEYMAP(0x0d, KEY_EQUAL), - KEYMAP(0x7d, KEY_YEN), /* JP keyboards only */ + KEYMAP(0x7d, KEY_YEN), /* JP keyboards only */ KEYMAP(0x0e, KEY_BACKSPACE), /* Row-2 */ KEYMAP(0x0f, KEY_TAB), @@ -128,7 +118,7 @@ KEYMAP(0x1b, KEY_RIGHTBRACE), KEYMAP(0x2b, KEY_BACKSLASH), /* Row-3 */ - KEYMAP(0xdb, KEY_LEFTMETA), /* Search Key */ + KEYMAP(0xdb, KEY_LEFTMETA), /* Search Key */ KEYMAP(0x1e, KEY_A), KEYMAP(0x1f, KEY_S), KEYMAP(0x20, KEY_D), @@ -143,7 +133,7 @@ KEYMAP(0x1c, KEY_ENTER), /* Row-4 */ KEYMAP(0x2a, KEY_LEFTSHIFT), - KEYMAP(0x56, KEY_102ND), /* UK keyboards only */ + KEYMAP(0x56, KEY_102ND), /* UK keyboards only */ KEYMAP(0x2c, KEY_Z), KEYMAP(0x2d, KEY_X), KEYMAP(0x2e, KEY_C), @@ -154,14 +144,14 @@ KEYMAP(0x33, KEY_COMMA), KEYMAP(0x34, KEY_DOT), KEYMAP(0x35, KEY_SLASH), - KEYMAP(0x73, KEY_RO), /* JP keyboards only */ + KEYMAP(0x73, KEY_RO), /* JP keyboards only */ KEYMAP(0x36, KEY_RIGHTSHIFT), /* Row-5 */ KEYMAP(0x1d, KEY_LEFTCTRL), KEYMAP(0x38, KEY_LEFTALT), - KEYMAP(0x7b, KEY_MUHENKAN), /* JP keyboards only */ + KEYMAP(0x7b, KEY_MUHENKAN), /* JP keyboards only */ KEYMAP(0x39, KEY_SPACE), - KEYMAP(0x79, KEY_HENKAN), /* JP keyboards only */ + KEYMAP(0x79, KEY_HENKAN), /* JP keyboards only */ KEYMAP(0xb8, KEY_RIGHTALT), KEYMAP(0x9d, KEY_RIGHTCTRL), /* Arrow keys */ @@ -193,9 +183,8 @@ keymap = action_keymaps[key]; } else { keymap = 0; - printk(BIOS_ERR, - "PS2K: invalid top-action-key-%u: %u(skipped)\n", - i, key); + printk(BIOS_ERR, "PS2K: invalid top-action-key-%u: %u(skipped)\n", i, + key); } acpi_dp_add_integer(dp_array, NULL, SCANCODE(keymap)); printk(BIOS_INFO, " %X", SCANCODE(keymap)); @@ -206,10 +195,8 @@ } static void ssdt_generate_keymap(struct acpi_dp *dp, uint8_t num_top_row_keys, - enum ps2_action_key action_keys[], - bool can_send_function_keys, - bool has_numeric_keypad, - bool has_scrnlock_key, + enum ps2_action_key action_keys[], bool can_send_function_keys, + bool has_numeric_keypad, bool has_scrnlock_key, bool has_alpha_num_punct_keys) { struct acpi_dp *dp_array; @@ -227,8 +214,7 @@ for (i = 0; i < num_top_row_keys; i++) { key = action_keys[i]; if (!key || key >= ARRAY_SIZE(action_keymaps)) { - printk(BIOS_ERR, - "PS2K: invalid top-action-key-%u: %u\n", i, key); + printk(BIOS_ERR, "PS2K: invalid top-action-key-%u: %u\n", i, key); continue; } keymap = action_keymaps[key]; @@ -279,16 +265,13 @@ } void acpigen_ps2_keyboard_dsd(const char *scope, uint8_t num_top_row_keys, - enum ps2_action_key action_keys[], - bool can_send_function_keys, - bool has_numeric_keypad, - bool has_scrnlock_key, + enum ps2_action_key action_keys[], bool can_send_function_keys, + bool has_numeric_keypad, bool has_scrnlock_key, bool has_alpha_num_punct_keys) { struct acpi_dp *dsd; - if (!scope || - num_top_row_keys < PS2_MIN_TOP_ROW_KEYS || + if (!scope || num_top_row_keys < PS2_MIN_TOP_ROW_KEYS || num_top_row_keys > PS2_MAX_TOP_ROW_KEYS) { printk(BIOS_ERR, "PS2K: %s: invalid args\n", __func__); return; @@ -302,9 +285,8 @@ acpigen_write_scope(scope); ssdt_generate_physmap(dsd, num_top_row_keys, action_keys); - ssdt_generate_keymap(dsd, num_top_row_keys, action_keys, - can_send_function_keys, has_numeric_keypad, - has_scrnlock_key, has_alpha_num_punct_keys); + ssdt_generate_keymap(dsd, num_top_row_keys, action_keys, can_send_function_keys, + has_numeric_keypad, has_scrnlock_key, has_alpha_num_punct_keys); acpi_dp_write(dsd); acpigen_pop_len(); /* Scope */ } diff --git a/src/acpi/acpigen_usb.c b/src/acpi/acpigen_usb.c index 221a215..b334176 100644 --- a/src/acpi/acpigen_usb.c +++ b/src/acpi/acpigen_usb.c @@ -65,9 +65,7 @@ try_power_role_to_str(config->try_power_role)); } -static void add_device_ref(struct acpi_dp *dsd, - const char *prop_name, - const struct device *dev) +static void add_device_ref(struct acpi_dp *dsd, const char *prop_name, const struct device *dev) { const char *path; char *fresh; diff --git a/src/acpi/device.c b/src/acpi/device.c index 92000a3..8515b97 100644 --- a/src/acpi/device.c +++ b/src/acpi/device.c @@ -16,8 +16,8 @@ #include <gpio.h> #endif -#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301" -#define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b" +#define ACPI_DP_UUID "daffd814-6eba-4d8c-8a91-bc9bbf4aa301" +#define ACPI_DP_CHILD_UUID "dbb8e3e6-5886-4ba6-8795-1319f52a966b" /* * Below properties are defined at @@ -130,8 +130,8 @@ } /* Recursive function to find the root device and print a path from there */ -static ssize_t acpi_device_path_fill(const struct device *dev, char *buf, - size_t buf_len, size_t cur) +static ssize_t acpi_device_path_fill(const struct device *dev, char *buf, size_t buf_len, + size_t cur) { const char *name = acpi_device_name(dev); ssize_t next = 0; @@ -154,9 +154,8 @@ /* Fill in the path from the root device */ next += snprintf(buf + next, buf_len - next, "%s%s", - (dev->path.type == DEVICE_PATH_ROOT - || (strlen(name) == 0)) ? - "" : ".", name); + (dev->path.type == DEVICE_PATH_ROOT || (strlen(name) == 0)) ? "" : ".", + name); return next; } @@ -407,7 +406,7 @@ /* Resource Source Name String */ #if CONFIG(GENERIC_GPIO_LIB) - acpigen_emit_string(gpio->resource ? : gpio_acpi_path(gpio->pins[0])); + acpigen_emit_string(gpio->resource ?: gpio_acpi_path(gpio->pins[0])); #else acpigen_emit_string(gpio->resource); #endif @@ -622,8 +621,8 @@ acpi_device_fill_len(desc_length); } -#define ACPI_POWER_RESOURCE_STATUS_ON_OP ONE_OP -#define ACPI_POWER_RESOURCE_STATUS_OFF_OP ZERO_OP +#define ACPI_POWER_RESOURCE_STATUS_ON_OP ONE_OP +#define ACPI_POWER_RESOURCE_STATUS_OFF_OP ZERO_OP /** * Writes an ACPI fragment that will check the GPIO and return 0 if the GPIO @@ -670,7 +669,7 @@ void acpi_device_add_power_res(const struct acpi_power_res_params *params) { static uint8_t id; - static const char * const power_res_dev_states[] = { "_PR0", "_PR3" }; + static const char *const power_res_dev_states[] = {"_PR0", "_PR3"}; unsigned int reset_gpio = params->reset_gpio ? params->reset_gpio->pins[0] : 0; unsigned int enable_gpio = params->enable_gpio ? params->enable_gpio->pins[0] : 0; unsigned int stop_gpio = params->stop_gpio ? params->stop_gpio->pins[0] : 0; @@ -724,7 +723,7 @@ if (params->stop_delay_ms) acpigen_write_sleep(params->stop_delay_ms); } - acpigen_pop_len(); /* _ON method */ + acpigen_pop_len(); /* _ON method */ /* Method (_OFF, 0, Serialized) */ acpigen_write_method_serialized("_OFF", 0); @@ -743,9 +742,9 @@ if (params->enable_off_delay_ms) acpigen_write_sleep(params->enable_off_delay_ms); } - acpigen_pop_len(); /* _OFF method */ + acpigen_pop_len(); /* _OFF method */ - acpigen_pop_len(); /* PowerResource PR## */ + acpigen_pop_len(); /* PowerResource PR## */ } static void acpi_dp_write_array(const struct acpi_dp *array); @@ -829,8 +828,7 @@ /* Print base properties */ for (dp = prop; dp; dp = dp->next) { - if (dp->type == ACPI_DP_TYPE_TABLE || - dp->type == ACPI_DP_TYPE_CHILD || + if (dp->type == ACPI_DP_TYPE_TABLE || dp->type == ACPI_DP_TYPE_CHILD || dp->type == ACPI_DP_TYPE_PACKAGE) continue; @@ -927,8 +925,7 @@ acpi_dp_free(table); } -static struct acpi_dp *acpi_dp_new(struct acpi_dp *dp, enum acpi_dp_type type, - const char *name) +static struct acpi_dp *acpi_dp_new(struct acpi_dp *dp, enum acpi_dp_type type, const char *name) { struct acpi_dp *new; @@ -956,8 +953,7 @@ return acpi_dp_new(NULL, ACPI_DP_TYPE_TABLE, name); } -size_t acpi_dp_add_property_list(struct acpi_dp *dp, - const struct acpi_dp *property_list, +size_t acpi_dp_add_property_list(struct acpi_dp *dp, const struct acpi_dp *property_list, size_t property_count) { const struct acpi_dp *prop; @@ -998,8 +994,7 @@ return properties_added; } -struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, - uint64_t value) +struct acpi_dp *acpi_dp_add_integer(struct acpi_dp *dp, const char *name, uint64_t value) { if (!dp) return NULL; @@ -1012,8 +1007,7 @@ return new; } -struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, - const char *string) +struct acpi_dp *acpi_dp_add_string(struct acpi_dp *dp, const char *name, const char *string) { if (!dp) return NULL; @@ -1040,8 +1034,7 @@ return new; } -struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, - struct acpi_dp *child) +struct acpi_dp *acpi_dp_add_child(struct acpi_dp *dp, const char *name, struct acpi_dp *child) { struct acpi_dp *new; @@ -1159,13 +1152,10 @@ acpi_dp_add_array(dp, gpio); return gpio; - } - -struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, - const char *ref, int index, int pin, - int active_low) +struct acpi_dp *acpi_dp_add_gpio(struct acpi_dp *dp, const char *name, const char *ref, + int index, int pin, int active_low) { struct acpi_gpio_res_params param = { .ref = ref, @@ -1218,10 +1208,8 @@ * name - Pointer to the property name string. * value - Value of the integer property. */ -static void acpi_device_add_integer_property_with_uuid(struct acpi_dp *dsd, - const char *uuid, - const char *name, - uint64_t value) +static void acpi_device_add_integer_property_with_uuid(struct acpi_dp *dsd, const char *uuid, + const char *name, uint64_t value) { struct acpi_dp *prev_dsd = dsd, *pkg; if (prev_dsd == NULL) @@ -1236,35 +1224,27 @@ /* _DSD with ExternalFacingPort */ void acpi_device_add_external_facing_port(struct acpi_dp *dsd) { - acpi_device_add_integer_property_with_uuid(dsd, - ACPI_DSD_EXTERNAL_FACING_PORT_UUID, - ACPI_DSD_EXTERNAL_FACING_PORT_NAME, - 1); + acpi_device_add_integer_property_with_uuid(dsd, ACPI_DSD_EXTERNAL_FACING_PORT_UUID, + ACPI_DSD_EXTERNAL_FACING_PORT_NAME, 1); } /* _DSD with HotPlugSupportInD3 */ void acpi_device_add_hotplug_support_in_d3(struct acpi_dp *dsd) { - acpi_device_add_integer_property_with_uuid(dsd, - ACPI_DSD_HOTPLUG_IN_D3_UUID, - ACPI_DSD_HOTPLUG_IN_D3_NAME, - 1); + acpi_device_add_integer_property_with_uuid(dsd, ACPI_DSD_HOTPLUG_IN_D3_UUID, + ACPI_DSD_HOTPLUG_IN_D3_NAME, 1); } /* _DSD with DmaProperty */ void acpi_device_add_dma_property(struct acpi_dp *dsd) { - acpi_device_add_integer_property_with_uuid(dsd, - ACPI_DSD_DMA_PROPERTY_UUID, - ACPI_DSD_DMA_PROPERTY_NAME, - 1); + acpi_device_add_integer_property_with_uuid(dsd, ACPI_DSD_DMA_PROPERTY_UUID, + ACPI_DSD_DMA_PROPERTY_NAME, 1); } /* _DSD with StorageD3Enable */ void acpi_device_add_storage_d3_enable(struct acpi_dp *dsd) { - acpi_device_add_integer_property_with_uuid(dsd, - ACPI_DSD_STORAGE_D3_UUID, - ACPI_DSD_STORAGE_D3_NAME, - 1); + acpi_device_add_integer_property_with_uuid(dsd, ACPI_DSD_STORAGE_D3_UUID, + ACPI_DSD_STORAGE_D3_NAME, 1); } diff --git a/src/acpi/fadt_filler.c b/src/acpi/fadt_filler.c index af65dbb..3e40280 100644 --- a/src/acpi/fadt_filler.c +++ b/src/acpi/fadt_filler.c @@ -19,7 +19,11 @@ printk(BIOS_ERR, "ACPI: FADT error detected, %s line %d.\n", func, line); } -#define fadt_sanity(x) do { if (!(x)) do_sanity_error(__func__, __LINE__); } while (0) +#define fadt_sanity(x) \ + do { \ + if (!(x)) \ + do_sanity_error(__func__, __LINE__); \ + } while (0) void fill_fadt_extended_pm_io(acpi_fadt_t *fadt) { @@ -28,11 +32,11 @@ /* Upper word is reserved and Linux complains about 32 bit. */ fadt_sanity(fadt->pm1a_cnt_blk && (fadt->pm1_cnt_len == 2)); - fill_x_pm_io(&fadt->x_pm1a_evt_blk, ACPI_ACCESS_SIZE_WORD_ACCESS, - fadt->pm1a_evt_blk, fadt->pm1_evt_len); + fill_x_pm_io(&fadt->x_pm1a_evt_blk, ACPI_ACCESS_SIZE_WORD_ACCESS, fadt->pm1a_evt_blk, + fadt->pm1_evt_len); - fill_x_pm_io(&fadt->x_pm1a_cnt_blk, ACPI_ACCESS_SIZE_WORD_ACCESS, - fadt->pm1a_cnt_blk, fadt->pm1_cnt_len); + fill_x_pm_io(&fadt->x_pm1a_cnt_blk, ACPI_ACCESS_SIZE_WORD_ACCESS, fadt->pm1a_cnt_blk, + fadt->pm1_cnt_len); if (fadt->pm1b_evt_blk) fill_x_pm_io(&fadt->x_pm1b_evt_blk, ACPI_ACCESS_SIZE_WORD_ACCESS, @@ -63,10 +67,10 @@ */ if (fadt->gpe0_blk) - fill_x_pm_io(&fadt->x_gpe0_blk, ACPI_ACCESS_SIZE_BYTE_ACCESS, - fadt->gpe0_blk, fadt->gpe0_blk_len); + fill_x_pm_io(&fadt->x_gpe0_blk, ACPI_ACCESS_SIZE_BYTE_ACCESS, fadt->gpe0_blk, + fadt->gpe0_blk_len); if (fadt->gpe1_blk) - fill_x_pm_io(&fadt->x_gpe1_blk, ACPI_ACCESS_SIZE_BYTE_ACCESS, - fadt->gpe1_blk, fadt->gpe1_blk_len); + fill_x_pm_io(&fadt->x_gpe1_blk, ACPI_ACCESS_SIZE_BYTE_ACCESS, fadt->gpe1_blk, + fadt->gpe1_blk_len); } diff --git a/src/acpi/gnvs.c b/src/acpi/gnvs.c index 827cd2d..5d3be60 100644 --- a/src/acpi/gnvs.c +++ b/src/acpi/gnvs.c @@ -30,7 +30,6 @@ if (dnvs_size) dnvs = (char *)gnvs + gnvs_size; - } BOOT_STATE_INIT_ENTRY(BS_PRE_DEVICE, BS_ON_EXIT, acpi_create_gnvs, NULL); @@ -54,17 +53,24 @@ } /* Implemented under platform. */ -__weak void soc_fill_gnvs(struct global_nvs *gnvs_) { } -__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) { } -__weak size_t size_of_dnvs(void) { return 0; } +__weak void soc_fill_gnvs(struct global_nvs *gnvs_) +{ +} +__weak void mainboard_fill_gnvs(struct global_nvs *gnvs_) +{ +} +__weak size_t size_of_dnvs(void) +{ + return 0; +} /* Called from write_acpi_tables() only on normal boot path. */ void acpi_fill_gnvs(void) { - const struct opregion gnvs_op = OPREGION("GNVS", SYSTEMMEMORY, (uintptr_t)gnvs, - sizeof(struct global_nvs)); - const struct opregion dnvs_op = OPREGION("DNVS", SYSTEMMEMORY, (uintptr_t)dnvs, - size_of_dnvs()); + const struct opregion gnvs_op = + OPREGION("GNVS", SYSTEMMEMORY, (uintptr_t)gnvs, sizeof(struct global_nvs)); + const struct opregion dnvs_op = + OPREGION("DNVS", SYSTEMMEMORY, (uintptr_t)dnvs, size_of_dnvs()); if (!gnvs) return; diff --git a/src/acpi/soundwire.c b/src/acpi/soundwire.c index 961f45b..3862e28 100644 --- a/src/acpi/soundwire.c +++ b/src/acpi/soundwire.c @@ -11,8 +11,7 @@ #define SDW_PFX "mipi-sdw-" /* Generate SoundWire property for integer. */ -#define SDW_INT(__key, __val) \ - acpi_dp_add_integer(dsd, SDW_PFX __key, __val) +#define SDW_INT(__key, __val) acpi_dp_add_integer(dsd, SDW_PFX __key, __val) /* Generate SoundWire property for integer array. */ #define SDW_INT_ARRAY(__key, __val) \ @@ -29,107 +28,83 @@ }; static const struct soundwire_name_map bra_mode_names[] = { - { "BRA0", SDW_PFX "port-bra-mode-0" }, - { "BRA1", SDW_PFX "port-bra-mode-1" }, - { "BRA2", SDW_PFX "port-bra-mode-2" }, - { "BRA3", SDW_PFX "port-bra-mode-3" }, + {"BRA0", SDW_PFX "port-bra-mode-0"}, + {"BRA1", SDW_PFX "port-bra-mode-1"}, + {"BRA2", SDW_PFX "port-bra-mode-2"}, + {"BRA3", SDW_PFX "port-bra-mode-3"}, }; static const struct soundwire_name_map audio_mode_names[] = { - { "MOD0", SDW_PFX "port-audio-mode-0" }, - { "MOD1", SDW_PFX "port-audio-mode-1" }, - { "MOD2", SDW_PFX "port-audio-mode-2" }, - { "MOD3", SDW_PFX "port-audio-mode-3" }, + {"MOD0", SDW_PFX "port-audio-mode-0"}, + {"MOD1", SDW_PFX "port-audio-mode-1"}, + {"MOD2", SDW_PFX "port-audio-mode-2"}, + {"MOD3", SDW_PFX "port-audio-mode-3"}, }; static const struct soundwire_name_map dpn_source_names[] = { - { "DP0", SDW_PFX "dp-0-subproperties" }, - { "SRC1", SDW_PFX "dp-1-source-subproperties" }, - { "SRC2", SDW_PFX "dp-2-source-subproperties" }, - { "SRC3", SDW_PFX "dp-3-source-subproperties" }, - { "SRC4", SDW_PFX "dp-4-source-subproperties" }, - { "SRC5", SDW_PFX "dp-5-source-subproperties" }, - { "SRC6", SDW_PFX "dp-6-source-subproperties" }, - { "SRC7", SDW_PFX "dp-7-source-subproperties" }, - { "SRC8", SDW_PFX "dp-8-source-subproperties" }, - { "SRC9", SDW_PFX "dp-9-source-subproperties" }, - { "SRCA", SDW_PFX "dp-10-source-subproperties" }, - { "SRCB", SDW_PFX "dp-11-source-subproperties" }, - { "SRCC", SDW_PFX "dp-12-source-subproperties" }, - { "SRCD", SDW_PFX "dp-13-source-subproperties" } + {"DP0", SDW_PFX "dp-0-subproperties" }, + {"SRC1", SDW_PFX "dp-1-source-subproperties" }, + {"SRC2", SDW_PFX "dp-2-source-subproperties" }, + {"SRC3", SDW_PFX "dp-3-source-subproperties" }, + {"SRC4", SDW_PFX "dp-4-source-subproperties" }, + {"SRC5", SDW_PFX "dp-5-source-subproperties" }, + {"SRC6", SDW_PFX "dp-6-source-subproperties" }, + {"SRC7", SDW_PFX "dp-7-source-subproperties" }, + {"SRC8", SDW_PFX "dp-8-source-subproperties" }, + {"SRC9", SDW_PFX "dp-9-source-subproperties" }, + {"SRCA", SDW_PFX "dp-10-source-subproperties"}, + {"SRCB", SDW_PFX "dp-11-source-subproperties"}, + {"SRCC", SDW_PFX "dp-12-source-subproperties"}, + {"SRCD", SDW_PFX "dp-13-source-subproperties"} }; static const struct soundwire_name_map dpn_sink_names[] = { - { "DP0", SDW_PFX "dp-0-subproperties" }, - { "SNK1", SDW_PFX "dp-1-sink-subproperties" }, - { "SNK2", SDW_PFX "dp-2-sink-subproperties" }, - { "SNK3", SDW_PFX "dp-3-sink-subproperties" }, - { "SNK4", SDW_PFX "dp-4-sink-subproperties" }, - { "SNK5", SDW_PFX "dp-5-sink-subproperties" }, - { "SNK6", SDW_PFX "dp-6-sink-subproperties" }, - { "SNK7", SDW_PFX "dp-7-sink-subproperties" }, - { "SNK8", SDW_PFX "dp-8-sink-subproperties" }, - { "SNK9", SDW_PFX "dp-9-sink-subproperties" }, - { "SNKA", SDW_PFX "dp-10-sink-subproperties" }, - { "SNKB", SDW_PFX "dp-11-sink-subproperties" }, - { "SNKC", SDW_PFX "dp-12-sink-subproperties" }, - { "SNKD", SDW_PFX "dp-13-sink-subproperties" } + {"DP0", SDW_PFX "dp-0-subproperties" }, + {"SNK1", SDW_PFX "dp-1-sink-subproperties" }, + {"SNK2", SDW_PFX "dp-2-sink-subproperties" }, + {"SNK3", SDW_PFX "dp-3-sink-subproperties" }, + {"SNK4", SDW_PFX "dp-4-sink-subproperties" }, + {"SNK5", SDW_PFX "dp-5-sink-subproperties" }, + {"SNK6", SDW_PFX "dp-6-sink-subproperties" }, + {"SNK7", SDW_PFX "dp-7-sink-subproperties" }, + {"SNK8", SDW_PFX "dp-8-sink-subproperties" }, + {"SNK9", SDW_PFX "dp-9-sink-subproperties" }, + {"SNKA", SDW_PFX "dp-10-sink-subproperties"}, + {"SNKB", SDW_PFX "dp-11-sink-subproperties"}, + {"SNKC", SDW_PFX "dp-12-sink-subproperties"}, + {"SNKD", SDW_PFX "dp-13-sink-subproperties"} }; static const struct soundwire_name_map link_names[] = { - { "LNK0", SDW_PFX "link-0-subproperties" }, - { "LNK1", SDW_PFX "link-1-subproperties" }, - { "LNK2", SDW_PFX "link-2-subproperties" }, - { "LNK3", SDW_PFX "link-3-subproperties" }, - { "LNK4", SDW_PFX "link-4-subproperties" }, - { "LNK5", SDW_PFX "link-5-subproperties" }, - { "LNK6", SDW_PFX "link-6-subproperties" }, - { "LNK7", SDW_PFX "link-7-subproperties" } + {"LNK0", SDW_PFX "link-0-subproperties"}, + {"LNK1", SDW_PFX "link-1-subproperties"}, + {"LNK2", SDW_PFX "link-2-subproperties"}, + {"LNK3", SDW_PFX "link-3-subproperties"}, + {"LNK4", SDW_PFX "link-4-subproperties"}, + {"LNK5", SDW_PFX "link-5-subproperties"}, + {"LNK6", SDW_PFX "link-6-subproperties"}, + {"LNK7", SDW_PFX "link-7-subproperties"} }; -static const char * const multilane_names[] = { - SDW_PFX "lane-1-mapping", - SDW_PFX "lane-2-mapping", - SDW_PFX "lane-3-mapping", - SDW_PFX "lane-4-mapping", - SDW_PFX "lane-5-mapping", - SDW_PFX "lane-6-mapping", - SDW_PFX "lane-7-mapping", - SDW_PFX "lane-8-mapping" -}; +static const char *const multilane_names[] = { + SDW_PFX "lane-1-mapping", SDW_PFX "lane-2-mapping", SDW_PFX "lane-3-mapping", + SDW_PFX "lane-4-mapping", SDW_PFX "lane-5-mapping", SDW_PFX "lane-6-mapping", + SDW_PFX "lane-7-mapping", SDW_PFX "lane-8-mapping"}; -static const char * const multilane_master_lane_names[] = { - SDW_PFX "master-lane-1", - SDW_PFX "master-lane-2", - SDW_PFX "master-lane-3", - SDW_PFX "master-lane-4", - SDW_PFX "master-lane-5", - SDW_PFX "master-lane-6", - SDW_PFX "master-lane-7", - SDW_PFX "master-lane-8" -}; +static const char *const multilane_master_lane_names[] = { + SDW_PFX "master-lane-1", SDW_PFX "master-lane-2", SDW_PFX "master-lane-3", + SDW_PFX "master-lane-4", SDW_PFX "master-lane-5", SDW_PFX "master-lane-6", + SDW_PFX "master-lane-7", SDW_PFX "master-lane-8"}; -static const char * const multilane_slave_link_names[] = { - SDW_PFX "slave-link-A", - SDW_PFX "slave-link-B", - SDW_PFX "slave-link-C", - SDW_PFX "slave-link-D", - SDW_PFX "slave-link-E", - SDW_PFX "slave-link-F", - SDW_PFX "slave-link-G", - SDW_PFX "slave-link-I" -}; +static const char *const multilane_slave_link_names[] = { + SDW_PFX "slave-link-A", SDW_PFX "slave-link-B", SDW_PFX "slave-link-C", + SDW_PFX "slave-link-D", SDW_PFX "slave-link-E", SDW_PFX "slave-link-F", + SDW_PFX "slave-link-G", SDW_PFX "slave-link-I"}; -static const char * const multilane_bus_holder_names[] = { - SDW_PFX "lane-1-bus-holder", - SDW_PFX "lane-2-bus-holder", - SDW_PFX "lane-3-bus-holder", - SDW_PFX "lane-4-bus-holder", - SDW_PFX "lane-5-bus-holder", - SDW_PFX "lane-6-bus-holder", - SDW_PFX "lane-7-bus-holder", - SDW_PFX "lane-8-bus-holder" -}; +static const char *const multilane_bus_holder_names[] = { + SDW_PFX "lane-1-bus-holder", SDW_PFX "lane-2-bus-holder", SDW_PFX "lane-3-bus-holder", + SDW_PFX "lane-4-bus-holder", SDW_PFX "lane-5-bus-holder", SDW_PFX "lane-6-bus-holder", + SDW_PFX "lane-7-bus-holder", SDW_PFX "lane-8-bus-holder"}; static void soundwire_gen_interface_revision(struct acpi_dp *dsd) { @@ -193,8 +168,7 @@ SDW_INT("clock-stop-mode1-supported", prop->clock_stop_mode1_supported); if (prop->clock_frequencies_supported_count > 0 && prop->clock_frequencies_supported_count < SOUNDWIRE_MAX) { - SDW_INT_ARRAY("clock-frequencies-supported", - prop->clock_frequencies_supported); + SDW_INT_ARRAY("clock-frequencies-supported", prop->clock_frequencies_supported); } SDW_INT("default-frame-rate", prop->default_frame_rate); SDW_INT("default-frame-row-size", prop->default_frame_row_size); -- To view, visit https://review.coreboot.org/c/coreboot/+/80007?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I5814fc7f04544a4968d3328e19cf67264a5f39d8 Gerrit-Change-Number: 80007 Gerrit-PatchSet: 1 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: newchange

1 0

[XS] Change in coreboot[main]: include/memlayout.h: Add OPENSBI linker macro
by Julius Werner (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Maximilian Brune, Patrick Rudolph, Philipp Hug, ron minnich. Julius Werner has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77974?usp=email ) Change subject: include/memlayout.h: Add OPENSBI linker macro ...................................................................... Patch Set 5: Code-Review+2 (2 comments) File src/arch/riscv/include/arch/memlayout.h: https://review.coreboot.org/c/coreboot/+/77974/comment/53bb7a5f_a1d30f2d : PS5, Line 27: opensbi > I am actually a little uncertain about that. If I choose to use: […] +1 to what Max said, I think we should stick to the convention that all macros always take address and size. We could instead eliminate the redundant Kconfig as I suggested above, so that the address defined in memlayout becomes meaningful on its own. File src/arch/riscv/include/arch/memlayout.h: https://review.coreboot.org/c/coreboot/+/77974/comment/320fa5e6_fbecf362 : PS3, Line 24: #if CONFIG(RISCV_OPENSBI) > Honestly I am not a fan of the whole static addressing approach. […] Well, the original idea behind having the address everywhere was that memlayout files can serve as both definition and documentation at once, so that if you want to know which address a certain region is mapped at you can simply look it up in the file. Of course, that requires that you write absolute offsets rather than your `FU540_L2LIM + ...` notation. (I don't think it's error-prone because any typos you make that would lead to overlaps get caught at build-time.) You're not generally supposed to do the if-else thing for optional features. It only really makes sense when you really have an exclusive-or situation (where only one or the other case can be active, but not both). This normally only happens for stages (e.g. how `OVERLAP_VERSTAGE_ROMSTAGE()` is implemented), or for very rare cases where there's an exclusive choice of implementations (e.g. if we had support for both TF-A and another Secure Monitor on arm64, then overlapping the regions for them like this might make sense). But for anything that's independently optional, we want all of those regions in the layout unconditionally because we don't want to get into a situation where a certain board only builds when you enable a limited subset of optional features, but doesn't fit the available space when you enable all of them at once. -- To view, visit https://review.coreboot.org/c/coreboot/+/77974?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f138de685c6bfb3cdbf79d63787eb0c5aab8590 Gerrit-Change-Number: 77974 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Julius Werner <jwerner(a)chromium.org> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Jan 2024 22:19:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Comment-In-Reply-To: Maximilian Brune <maximilian.brune(a)9elements.com> Comment-In-Reply-To: Julius Werner <jwerner(a)chromium.org> Gerrit-MessageType: comment

1 0

[S] Change in coreboot[main]: mb/google/brox: Set up FW_CONFIG
by Shelley Chen (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Eric Lai, Nick Vaccaro, Paul Menzel. Shelley Chen has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79854?usp=email ) Change subject: mb/google/brox: Set up FW_CONFIG ...................................................................... Patch Set 8: (6 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79854/comment/86923c2c_51ba326d : PS2, Line 10: making > Imperative mood: make Done https://review.coreboot.org/c/coreboot/+/79854/comment/858a6a88_e366b3e9 : PS2, Line 11: moving > move Removed. https://review.coreboot.org/c/coreboot/+/79854/comment/2409d673_6a507c38 : PS2, Line 11: Also, moving the storage devices to brox : overridetree.cb as they are specific to this board. > A separate commit would be nice. Moved to https://review.coreboot.org/c/coreboot/+/79995 File src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79854/comment/7d57f07c_082b94cd : PS2, Line 180: device ref pcie4_0 on > Probably separate the PCIE with another CL? Moved to https://review.coreboot.org/c/coreboot/+/79995 File src/mainboard/google/brox/variants/brox/overridetree.cb: https://review.coreboot.org/c/coreboot/+/79854/comment/05684750_7f0e8eb8 : PS1, Line 8: option STORAGE_UFS 0 > If you think emmc might be added later, might be better to make this […] Done https://review.coreboot.org/c/coreboot/+/79854/comment/69a34347_747bf570 : PS1, Line 11: end > 1) It will likely need a field for WiFi Device (not sure if kernel will need a field for WLAN type a […] Nick, can you review these fw config settings to make sure that they cover your conerns? -- To view, visit https://review.coreboot.org/c/coreboot/+/79854?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f Gerrit-Change-Number: 79854 Gerrit-PatchSet: 8 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-Comment-Date: Tue, 16 Jan 2024 21:54:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Eric Lai <ericllai(a)google.com> Comment-In-Reply-To: Paul Menzel <paulepanter(a)mailbox.org> Comment-In-Reply-To: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[main]: mb/google/brox: Set up FW_CONFIG
by Shelley Chen (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Shelley Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79854?usp=email to look at the new patch set (#8). Change subject: mb/google/brox: Set up FW_CONFIG ...................................................................... mb/google/brox: Set up FW_CONFIG Brox project has FW_CONFIG bits already set up in the project file for the retimer and for storage, so make sure that the brox device tree matches those settings. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/brox/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/79854/8 -- To view, visit https://review.coreboot.org/c/coreboot/+/79854?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f Gerrit-Change-Number: 79854 Gerrit-PatchSet: 8 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[S] Change in coreboot[main]: mb/google/brox: Move storage devices to overridetree
by Shelley Chen (Code Review) 16 Jan '24

16 Jan '24

Shelley Chen has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79995?usp=email ) Change subject: mb/google/brox: Move storage devices to overridetree ...................................................................... mb/google/brox: Move storage devices to overridetree These are specific to the brox board, so moving devices to the brox variant. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183 Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb M src/mainboard/google/brox/variants/brox/overridetree.cb 2 files changed, 19 insertions(+), 15 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/79995/1 diff --git a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb index 23db754..c1c561b 100644 --- a/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb +++ b/src/mainboard/google/brox/variants/baseboard/brox/devicetree.cb @@ -173,21 +173,6 @@ end device ref heci1 on end device ref sata on end - device ref pcie4_0 on - # Enable CPU PCIE RP 1 using CLK 3 - register "cpu_pcie_rp[CPU_RP(1)]" = "{ - .clk_req = 3, - .clk_src = 3, - .flags = PCIE_RP_LTR | PCIE_RP_AER, - }" - end - device ref ish on - chip drivers/intel/ish - register "add_acpi_dma_property" = "true" - device generic 0 on end - end - end - device ref ufs on end device ref uart0 on end device ref gspi1 on end device ref pch_espi on diff --git a/src/mainboard/google/brox/variants/brox/overridetree.cb b/src/mainboard/google/brox/variants/brox/overridetree.cb index 48c7b3d..c399634 100644 --- a/src/mainboard/google/brox/variants/brox/overridetree.cb +++ b/src/mainboard/google/brox/variants/brox/overridetree.cb @@ -170,5 +170,24 @@ device generic 0 on end end end + device ref pcie4_0 on + # Enable CPU PCIE RP 1 using CLK 3 + register "cpu_pcie_rp[CPU_RP(1)]" = "{ + .clk_req = 3, + .clk_src = 3, + .flags = PCIE_RP_LTR | PCIE_RP_AER, + }" + probe STORAGE STORAGE_NVME + end + device ref ish on + chip drivers/intel/ish + register "add_acpi_dma_property" = "true" + device generic 0 on end + end + probe STORAGE STORAGE_UFS + end + device ref ufs on + probe STORAGE STORAGE_UFS + end end end -- To view, visit https://review.coreboot.org/c/coreboot/+/79995?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I18d096040c293abfd4cd0b1bb5f50ba6dcc2e183 Gerrit-Change-Number: 79995 Gerrit-PatchSet: 1 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: mb/google/brox: Set up FW_CONFIG
by Shelley Chen (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Shelley Chen. Hello build bot (Jenkins), I'd like you to reexamine a change. Please visit https://review.coreboot.org/c/coreboot/+/79854?usp=email to look at the new patch set (#7). The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: mb/google/brox: Set up FW_CONFIG ...................................................................... mb/google/brox: Set up FW_CONFIG Brox project has FW_CONFIG bits already set up in the project file for the retimer and for storage, so making sure that the brox device tree matches those settings. BUG=b:311450057,b:300690448,b:319058143 BRANCH=None TEST=emerge-brox coreboot chromeos-bootimage will check if this helps detect the storage device in the factory Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f Signed-off-by: Shelley Chen <shchen(a)google.com> --- M src/mainboard/google/brox/variants/brox/overridetree.cb 1 file changed, 23 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/54/79854/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/79854?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Iaf43003b7e8210eee9016d779839d7048c15825f Gerrit-Change-Number: 79854 Gerrit-PatchSet: 7 Gerrit-Owner: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Eric Lai <ericllai(a)google.com> Gerrit-CC: Nick Vaccaro <nvaccaro(a)google.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[main]: arch/x86/mpspec: turn compile-time check into Kconfig dependency
by Martin Roth (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Felix Held, Jérémy Compostella. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79994?usp=email ) Change subject: arch/x86/mpspec: turn compile-time check into Kconfig dependency ...................................................................... Patch Set 1: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79994?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie532a401ad0161890d0fb4ca2889af022d5f6b47 Gerrit-Change-Number: 79994 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Attention: Jérémy Compostella <jeremy.compostella(a)intel.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Jan 2024 19:57:51 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/x86/mpspec: turn compile-time check into Kconfig dependency
by Felix Held (Code Review) 16 Jan '24

16 Jan '24

Felix Held has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/79994?usp=email ) Change subject: arch/x86/mpspec: turn compile-time check into Kconfig dependency ...................................................................... arch/x86/mpspec: turn compile-time check into Kconfig dependency Instead of checking if there is more than one PCI segment group and erroring out in that case during the build, add this requirement as a dependency to the GENERATE_MP_TABLE Kconfig option. The mpspec.c source file only gets included in the build if GENERATE_MP_TABLE is selected. Signed-off-by: Felix Held <felix-coreboot(a)felixheld.de> Suggested-by: Martin Roth <gaumless(a)gmail.com> Change-Id: Ie532a401ad0161890d0fb4ca2889af022d5f6b47 --- M src/Kconfig M src/arch/x86/mpspec.c 2 files changed, 1 insertion(+), 4 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/94/79994/1 diff --git a/src/Kconfig b/src/Kconfig index 5cb9a1a..9797624 100644 --- a/src/Kconfig +++ b/src/Kconfig @@ -907,6 +907,7 @@ config GENERATE_MP_TABLE prompt "Generate an MP table" if HAVE_MP_TABLE bool + depends on !ECAM_MMCONF_SUPPORT || ECAM_MMCONF_BUS_NUMBER <= 256 default HAVE_MP_TABLE help Generate an MP table (conforming to the Intel MultiProcessor diff --git a/src/arch/x86/mpspec.c b/src/arch/x86/mpspec.c index 3b4c8ad..7744f68 100644 --- a/src/arch/x86/mpspec.c +++ b/src/arch/x86/mpspec.c @@ -14,10 +14,6 @@ #include <stdint.h> #include <string.h> -#if CONFIG(ECAM_MMCONF_SUPPORT) && PCI_SEGMENT_GROUP_COUNT > 1 -#error "MPTable doesn't support systems with multiple PCI segment groups" -#endif - /* Initialize the specified "mc" struct with initial values. */ void mptable_init(struct mp_config_table *mc) { -- To view, visit https://review.coreboot.org/c/coreboot/+/79994?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ie532a401ad0161890d0fb4ca2889af022d5f6b47 Gerrit-Change-Number: 79994 Gerrit-PatchSet: 1 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newchange

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[S] Change in coreboot[main]: device/device_const: add pcidev_path_on_segbus
by Martin Roth (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Felix Held, Patrick Rudolph. Martin Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79980?usp=email ) Change subject: device/device_const: add pcidev_path_on_segbus ...................................................................... Patch Set 2: Code-Review+2 -- To view, visit https://review.coreboot.org/c/coreboot/+/79980?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ibbbee9966abc997ded6389e72912e621c1f0bdbf Gerrit-Change-Number: 79980 Gerrit-PatchSet: 2 Gerrit-Owner: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Martin Roth <martin.roth(a)amd.corp-partner.google.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Jan 2024 19:46:50 +0000 Gerrit-HasComments: No Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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