coreboot-gerrit January 2024

coreboot-gerrit@coreboot.org

1 participants
3044 discussions

[M] Change in coreboot[main]: mb/google/nissa/var/craaskov: Modify thermal table
by Paul Menzel (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Eric Lai, Ian Feng, Kenny Pan, Nick Vaccaro, Rex Chou, Shou-Chieh Hsu, Sumeet R Pawnikar. Paul Menzel has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79890?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: mb/google/nissa/var/craaskov: Modify thermal table ...................................................................... Patch Set 6: (4 comments) Commit Message: https://review.coreboot.org/c/coreboot/+/79890/comment/f3ff4b70_69839052 : PS6, Line 8: Please describe the problem. https://review.coreboot.org/c/coreboot/+/79890/comment/20eaa4af_10d4a83d : PS6, Line 9: b:290705146#comment41 I am not allowed to read this comment. https://review.coreboot.org/c/coreboot/+/79890/comment/01680f7c_79993d2b : PS6, Line 10: change increase https://review.coreboot.org/c/coreboot/+/79890/comment/0bab2dc8_5f6338ba : PS6, Line 10: power(Watts) Please add a space before the (. -- To view, visit https://review.coreboot.org/c/coreboot/+/79890?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I15fa4b8f7c7088ff56da6493659ae45572913b5a Gerrit-Change-Number: 79890 Gerrit-PatchSet: 6 Gerrit-Owner: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Reviewer: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Kenny Pan <kennypan(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-Attention: Eric Lai <ericllai(a)google.com> Gerrit-Attention: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Attention: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Kenny Pan <kennypan(a)google.com> Gerrit-Attention: Shou-Chieh Hsu <shouchieh(a)google.com> Gerrit-Comment-Date: Tue, 16 Jan 2024 16:25:16 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[L] Change in coreboot[main]: soc/intel/skylake: Drop redundant PcieRpEnable
by Jonathon Hall (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Angel Pons, Erik van den Bogaert, Frans Hendriks, Jan Samek, Jeremy Soller, Michael Niewöhner, Michał Żygowski, Nicholas Sudsgaard, Nico Huber, Piotr Król, Sean Rhodes, Tim Crawford. Jonathon Hall has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79917?usp=email ) Change subject: soc/intel/skylake: Drop redundant PcieRpEnable ...................................................................... Patch Set 2: (1 comment) File src/mainboard/purism/librem_skl/devicetree.cb: https://review.coreboot.org/c/coreboot/+/79917/comment/7f7ece87_62f2009c : PS2, Line 141: register "PcieRpEnable[4]" = "1" I don't know why librem_skl has pcie_rp1 in the device tree, but enables PcieRpEnable[4] here. RP9 is for NVMe, RP5 is for WLAN - both of which worked. Maybe the device tree had pcie_rp1 because RP5 will get promoted to PCI function 0? Other boards don't do this, was this necessary in older coreboot releases? My guess is that it should change to pcie_rp5, but I will confirm. I'll test this CL on it and check it out. -- To view, visit https://review.coreboot.org/c/coreboot/+/79917?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I2f7e3e1dc6b3d8d6159bd4701e6fd90f4b0f67f4 Gerrit-Change-Number: 79917 Gerrit-PatchSet: 2 Gerrit-Owner: Nico Huber <nico.h(a)gmx.de> Gerrit-Reviewer: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Reviewer: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Reviewer: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Reviewer: Jan Samek <jan.samek(a)siemens.com> Gerrit-Reviewer: Jeremy Soller <jeremy(a)system76.com> Gerrit-Reviewer: Jonathon Hall <jonathon.hall(a)puri.sm> Gerrit-Reviewer: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Reviewer: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Reviewer: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Reviewer: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Reviewer: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Reviewer: Tim Crawford <tcrawford(a)system76.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Attention: Erik van den Bogaert <ebogaert(a)eltan.com> Gerrit-Attention: Tim Crawford <tcrawford(a)system76.com> Gerrit-Attention: Nico Huber <nico.h(a)gmx.de> Gerrit-Attention: Sean Rhodes <sean(a)starlabs.systems> Gerrit-Attention: Michał Żygowski <michal.zygowski(a)3mdeb.com> Gerrit-Attention: Frans Hendriks <fhendriks(a)eltan.com> Gerrit-Attention: Jeremy Soller <jeremy(a)system76.com> Gerrit-Attention: Angel Pons <th3fanbus(a)gmail.com> Gerrit-Attention: Nicholas Sudsgaard <devel+coreboot(a)nsudsgaard.com> Gerrit-Attention: Michael Niewöhner <foss(a)mniewoehner.de> Gerrit-Attention: Jan Samek <jan.samek(a)siemens.com> Gerrit-Attention: Piotr Król <piotr.krol(a)3mdeb.com> Gerrit-Comment-Date: Tue, 16 Jan 2024 16:03:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: include/memlayout.h: Add OPENSBI linker macro
by Maximilian Brune (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Julius Werner, Patrick Rudolph, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77974?usp=email ) Change subject: include/memlayout.h: Add OPENSBI linker macro ...................................................................... Patch Set 5: (1 comment) File src/arch/riscv/include/arch/memlayout.h: https://review.coreboot.org/c/coreboot/+/77974/comment/d682dce2_ad328cef : PS5, Line 27: opensbi > why not `REGION(opensbi, CONFIG_OPENSBI_TEXT_START, size, 4K)` ? I am actually a little uncertain about that. If I choose to use: `REGION(opensbi, CONFIG_OPENSBI_TEXT_START, size, 4K)` then it would look like this in a memlayout file: ``` SECTIONS { DRAM_START(FU540_DRAM) OPENSBI(128K) RAMSTAGE(FU540_DRAM + 128K, 2M) MEM_STACK(FU540_DRAM + 128K + 2M, 20K) POSTRAM_CBFS_CACHE(FU540_DRAM + 3M, 29M) } ``` And that is very inconsistent, because all macros usually get an address and a size. As a reader I would look at this file and think that the OPENSBI macro is placed exactly at the location `FU540_DRAM`. But this may not be the case since I define it to be always at `CONFIG_OPENSBI_TEXT_START`. Without looking inside the macro itself it is very confusing on where it is placed. Bottom line: I chose not to use `REGION(opensbi, CONFIG_OPENSBI_TEXT_START, size, 4K)` for readability reasons. -- To view, visit https://review.coreboot.org/c/coreboot/+/77974?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I4f138de685c6bfb3cdbf79d63787eb0c5aab8590 Gerrit-Change-Number: 77974 Gerrit-PatchSet: 5 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-CC: Julius Werner <jwerner(a)chromium.org> Gerrit-CC: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: Julius Werner <jwerner(a)chromium.org> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Jan 2024 15:17:47 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: arch/riscv/boot.c: Add comment for clarity
by Maximilian Brune (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Patrick Rudolph, Philipp Hug, ron minnich. Maximilian Brune has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79949?usp=email ) Change subject: arch/riscv/boot.c: Add comment for clarity ...................................................................... Patch Set 1: (1 comment) File src/arch/riscv/boot.c: https://review.coreboot.org/c/coreboot/+/79949/comment/1e1af7fc_211b139f : PS1, Line 35: // tell OpenSBI to switch to Supervisor mode before jumping to payload > please use C style comments `/* ` It is a single line comment so I choose C99 single line comment style. -- To view, visit https://review.coreboot.org/c/coreboot/+/79949?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: Ib62be0c2ff59361200df4c65f9aca5f7456a0ada Gerrit-Change-Number: 79949 Gerrit-PatchSet: 1 Gerrit-Owner: Maximilian Brune <maximilian.brune(a)9elements.com> Gerrit-Reviewer: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Reviewer: Philipp Hug <philipp(a)hug.cx> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: ron minnich <rminnich(a)gmail.com> Gerrit-Attention: Philipp Hug <philipp(a)hug.cx> Gerrit-Attention: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-Attention: ron minnich <rminnich(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Jan 2024 15:03:23 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Patrick Rudolph <patrick.rudolph(a)9elements.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config
by Patrick Georgi (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Felix Held, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Shelley Chen, Subrata Banik, Tarun. Patrick Georgi has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79936?usp=email ) The change is no longer submittable: All-Comments-Resolved is unsatisfied now. Change subject: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config ...................................................................... Patch Set 3: (1 comment) File src/soc/intel/alderlake/Kconfig: https://review.coreboot.org/c/coreboot/+/79936/comment/645964f7_4f154e7e : PS3, Line 221: default 0x100000 if BMP_LOGO So 1MB. Should we make that the default across the tree? SMM/resume shouldn't break on that anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/79936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If34b1ef497d38ba561221c584aab5399cfc5de82 Gerrit-Change-Number: 79936 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-CC: Patrick Georgi <patrick(a)coreboot.org> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Jan 2024 14:48:54 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config
by Arthur Heymans (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Felix Held, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Shelley Chen, Subrata Banik, Tarun. Arthur Heymans has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79936?usp=email ) Change subject: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config ...................................................................... Patch Set 3: Code-Review+2 (1 comment) Patchset: PS3: Btw would it make sense to add the BLT buffer to cbmem rather than heap, just like BMP? That avoids those if BMP_LOGO lines in Kconfig. -- To view, visit https://review.coreboot.org/c/coreboot/+/79936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If34b1ef497d38ba561221c584aab5399cfc5de82 Gerrit-Change-Number: 79936 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Jan 2024 14:36:39 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config
by Subrata Banik (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Felix Held, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Shelley Chen, Tarun. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79936?usp=email ) Change subject: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: > not sure if adl and mtl still support s3, but if they do: did you check that this doesn't break s3 resume? see CB:78850 latest Intel platform doesn't have support for S3 anymore. -- To view, visit https://review.coreboot.org/c/coreboot/+/79936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If34b1ef497d38ba561221c584aab5399cfc5de82 Gerrit-Change-Number: 79936 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Tue, 16 Jan 2024 14:15:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config
by Felix Held (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Nick Vaccaro, Shelley Chen, Subrata Banik, Tarun. Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79936?usp=email ) Change subject: soc/intel/{adl, mtl}: Increase heap size (HEAP_SIZE) config ...................................................................... Patch Set 3: (1 comment) Patchset: PS3: not sure if adl and mtl still support s3, but if they do: did you check that this doesn't break s3 resume? see CB:78850 -- To view, visit https://review.coreboot.org/c/coreboot/+/79936?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: If34b1ef497d38ba561221c584aab5399cfc5de82 Gerrit-Change-Number: 79936 Gerrit-PatchSet: 3 Gerrit-Owner: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Shelley Chen <shchen(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Attention: Shelley Chen <shchen(a)google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Subrata Banik <subratabanik(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Jan 2024 13:35:05 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[main]: mb/google/nissa/var/craaskov: Add Micron MT62F1G32D4DR-031 to mem_parts
by Felix Held (Code Review) 16 Jan '24

16 Jan '24

Felix Held has submitted this change. ( https://review.coreboot.org/c/coreboot/+/79914?usp=email ) Change subject: mb/google/nissa/var/craaskov: Add Micron MT62F1G32D4DR-031 to mem_parts ...................................................................... mb/google/nissa/var/craaskov: Add Micron MT62F1G32D4DR-031 to mem_parts Add new memory Micron MT62F1G32D4DR-031 WT:B. DRAM Part Name ID to assign MT62F1G32D4DR-031 WT:B 2 (0010) BUG=b:319778218 BRANCH=firmware-nissa-15217.B TEST=emerge-nissa coreboot Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7 Signed-off-by: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79914 Reviewed-by: Eric Lai <ericllai(a)google.com> Reviewed-by: Paul Menzel <paulepanter(a)mailbox.org> Tested-by: build bot (Jenkins) <no-reply(a)coreboot.org> --- M src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc M src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt M src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt 3 files changed, 3 insertions(+), 1 deletion(-) Approvals: Eric Lai: Looks good to me, approved build bot (Jenkins): Verified Paul Menzel: Looks good to me, but someone else must approve diff --git a/src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc b/src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc index 1f61b57..11778cf 100644 --- a/src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc +++ b/src/mainboard/google/brya/variants/craaskov/memory/Makefile.inc @@ -6,4 +6,4 @@ SPD_SOURCES = SPD_SOURCES += spd/lp5/set-0/spd-1.hex # ID = 0(0b0000) Parts = MT62F512M32D2DR-031 WT:B, H9JCNNNBK3MLYR-N6E SPD_SOURCES += spd/lp5/set-0/spd-3.hex # ID = 1(0b0001) Parts = K3LKBKB0BM-MGCP -SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 2(0b0010) Parts = H9JCNNNCP3MLYR-N6E +SPD_SOURCES += spd/lp5/set-0/spd-2.hex # ID = 2(0b0010) Parts = H9JCNNNCP3MLYR-N6E, MT62F1G32D4DR-031 WT:B diff --git a/src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt b/src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt index d659743..5438504 100644 --- a/src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt +++ b/src/mainboard/google/brya/variants/craaskov/memory/dram_id.generated.txt @@ -8,3 +8,4 @@ H9JCNNNBK3MLYR-N6E 0 (0000) K3LKBKB0BM-MGCP 1 (0001) H9JCNNNCP3MLYR-N6E 2 (0010) +MT62F1G32D4DR-031 WT:B 2 (0010) diff --git a/src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt b/src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt index 126d067..6a61490 100644 --- a/src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt +++ b/src/mainboard/google/brya/variants/craaskov/memory/mem_parts_used.txt @@ -13,3 +13,4 @@ H9JCNNNBK3MLYR-N6E K3LKBKB0BM-MGCP H9JCNNNCP3MLYR-N6E +MT62F1G32D4DR-031 WT:B -- To view, visit https://review.coreboot.org/c/coreboot/+/79914?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9e54958490228beb7039d531c709d56ec244b9e7 Gerrit-Change-Number: 79914 Gerrit-PatchSet: 3 Gerrit-Owner: Ian Feng <ian_feng(a)compal.corp-partner.google.com> Gerrit-Reviewer: Eric Lai <ericllai(a)google.com> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Nick Vaccaro <nvaccaro(a)chromium.org> Gerrit-Reviewer: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Dtrain Hsu <dtrain_hsu(a)compal.corp-partner.google.com> Gerrit-CC: Rex Chou <rex_chou(a)compal.corp-partner.google.com> Gerrit-CC: Van Chen <van_chen(a)compal.corp-partner.google.com> Gerrit-MessageType: merged

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[XS] Change in coreboot[main]: soc/intel/meteorlake: Set TCC to 100°C
by Subrata Banik (Code Review) 16 Jan '24

16 Jan '24

Attention is currently required from: Dinesh Gehlot, Eran Mitrani, Jakub Czapiga, Kapil Porwal, Sumeet R Pawnikar, Tarun, yunhao wang. Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/79992?usp=email ) Change subject: soc/intel/meteorlake: Set TCC to 100°C ...................................................................... Patch Set 2: (1 comment) Commit Message: https://review.coreboot.org/c/coreboot/+/79992/comment/ad85dffb_4bd7ce7c : PS1, Line 9: Set tcc_offset value to 10 in devicetree for Thermal Control : Circuit (TCC) activation feature for rex. > We are seeing the same issue on Screebo mentioned on this bug. I'm updating Screebo bug and planning to propose the same change for Screebo as well. please make sure you are reaching out to the ODM team sooner as we are reaching to the FSI phase and this CL can be tagged for FCS. -- To view, visit https://review.coreboot.org/c/coreboot/+/79992?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: main Gerrit-Change-Id: I9012984016ab3213102214025d6d8dc07c5d8974 Gerrit-Change-Number: 79992 Gerrit-PatchSet: 2 Gerrit-Owner: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Reviewer: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <czapiga(a)google.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Reviewer: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: yunhao wang <wangyunhao(a)huaqin.corp-partner.google.com> Gerrit-Attention: Eran Mitrani <mitrani(a)google.com> Gerrit-Attention: Jakub Czapiga <czapiga(a)google.com> Gerrit-Attention: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Attention: Dinesh Gehlot <digehlot(a)google.com> Gerrit-Attention: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-Attention: Tarun <tstuli(a)gmail.com> Gerrit-Comment-Date: Tue, 16 Jan 2024 12:35:57 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Subrata Banik <subratabanik(a)google.com> Comment-In-Reply-To: Sumeet R Pawnikar <sumeet.r.pawnikar(a)intel.com> Gerrit-MessageType: comment

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