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Change subject: soc/intel/common: Add cleanup and rearm functions
......................................................................
soc/intel/common: Add cleanup and rearm functions
Introduce cpu_cl_cleanup() and cpu_cl_rearm() functions
for CPU crashlog flow. Also add default weak implementations.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: Iad68d3fdaf7061148b184371f7ef87d83f2b2b38
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/common/block/crashlog/crashlog.c
M src/soc/intel/common/block/include/intelblocks/crashlog.h
2 files changed, 16 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/38/77238/6
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Change subject: soc/intel/common: Make common cpu_cl_clear_data() weak
......................................................................
soc/intel/common: Make common cpu_cl_clear_data() weak
Not all SOC follow the same programming to clear crashlog
data. So make common implementation of cpu_cl_clear_data()
weak.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: Ic2b4631d57703abff0ab1880fb272ef67bb1b8e9
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/common/block/crashlog/crashlog.c
1 file changed, 1 insertion(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/37/77237/5
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Change subject: soc/intel/common: Rename crashlog macros
......................................................................
soc/intel/common: Rename crashlog macros
Remove MAILBOX word from CPU_CRASHLOG_MAILBOX_WAIT_STALL
and CPU_CRASHLOG_MAILBOX_WAIT_TIMEOUT macros, because they
can be used for other interface as well.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: I62b04fa4b05c427db494a536ca6504db02dfeb68
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/common/block/crashlog/crashlog.c
M src/soc/intel/common/block/include/intelblocks/crashlog.h
2 files changed, 5 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/36/77236/5
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Change subject: soc/intel/meteorlake: Skip crashlog region with metadata tag
......................................................................
soc/intel/meteorlake: Skip crashlog region with metadata tag
Region with metadata tag contains information about BDF entry for
SOC PMC SRAM and IOE SRAM. We don't need to parse this as we already
define BDFs in soc/pci_devs.h for these SRAMs. Also we need to skip
to region as it does not contain any crashlog data.
BUG=b:262501347
TEST=Able to build google/rex. Able to trigger crashlog and decode
correctly.
Change-Id: Id8ed40b865cde8e89045f5c9e713398fcbff5890
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/meteorlake/crashlog.c
1 file changed, 12 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/34/76834/6
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Change subject: soc/intel/common: Add metadata tag definition for crashlog
......................................................................
soc/intel/common: Add metadata tag definition for crashlog
When parsing descriptor table the record can have tag type = 7.
This tag contains metadata depending on SOC. The platform may
choose to parse it based on implementation of crashlog.
BUG=b:262501347
TEST=Able to build google/rex.
Change-Id: I60dda06950974f7949fa5635141e4b7798c4d1f2
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/common/block/include/intelblocks/crashlog.h
1 file changed, 10 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/76833/6
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Change subject: soc/intel/meteorlake: Validate CPU crashlog discovery table and records
......................................................................
soc/intel/meteorlake: Validate CPU crashlog discovery table and records
CPU crashlog discovery table and crashlog record is considered
invalid if first 32bits of the table is either 0x0 (no crashlog)
or 0xdeadbeef (invalid crashlog).
Crashlog record is considered consumed if bit 31 is set. So in this
case stop processing the subsequent records.
BUG=b:289600699
TEST=Able to build and verified invalid records are skipped on google/rex.
Change-Id: Ia81bd293a533217425e44473ae85b2115c85faf6
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/meteorlake/crashlog.c
1 file changed, 24 insertions(+), 1 deletion(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/33/76333/18
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Change subject: soc/intel/meteorlake: Adjust discovery table offset based on CPUID
......................................................................
soc/intel/meteorlake: Adjust discovery table offset based on CPUID
CPUID CPUID_METEORLAKE_B0 onwards the discovery table offset needs
to be left-shifted by 3.
Reference: EDS Vol 1 (640228)
BUG=b:289600699
TEST=Able to boot google/rex with crashlog enabled.
Change-Id: I90647fb6190a52b42298398263978beaf931b035
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/meteorlake/crashlog.c
1 file changed, 14 insertions(+), 7 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/76400/16
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Subrata Banik has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77596?usp=email )
The change is no longer submittable: All-Comments-Resolved is unsatisfied now.
Change subject: mb/google/rex/var/screebo: remove SD_ABSENT
......................................................................
Patch Set 2:
(1 comment)
File src/mainboard/google/rex/variants/screebo/overridetree.cb:
https://review.coreboot.org/c/coreboot/+/77596/comment/72cb1a7b_0da1f466 :
PS2, Line 21: 11 12
do we need 2 bits for SD DB now ?
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