Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77599?usp=email )
Change subject: device/Kconfig: Add an option to allocate above 4G by default
......................................................................
device/Kconfig: Add an option to allocate above 4G by default
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: Ie0cbebde57cf4f9bc576826039333dba3dad0eb9
---
M src/device/Kconfig
M src/device/resource_allocator_v4.c
2 files changed, 12 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/99/77599/1
diff --git a/src/device/Kconfig b/src/device/Kconfig
index 8c6c734..29d7a17 100644
--- a/src/device/Kconfig
+++ b/src/device/Kconfig
@@ -1004,6 +1004,15 @@
undeclared resources. EDK2 is currently reported to also have
problems on some platforms, at least with Intel's IGD.
+config RESOURCE_IGNORE_FLAG_IORESOURCE_ABOVE_4G
+ bool
+ default n if ARCH_X86
+ default y
+ help
+ Don't limit mem resources to 4G, but to their actual limit.
+ This can break both coreboot and the payload if they try to
+ access resources above 4G in 32bit mode.
+
config XHCI_UTILS
def_bool n
help
diff --git a/src/device/resource_allocator_v4.c b/src/device/resource_allocator_v4.c
index c3132f4..872e788 100644
--- a/src/device/resource_allocator_v4.c
+++ b/src/device/resource_allocator_v4.c
@@ -84,6 +84,9 @@
static resource_t effective_limit(const struct resource *const res)
{
+ if (CONFIG(RESOURCE_IGNORE_FLAG_IORESOURCE_ABOVE_4G))
+ return res->limit;
+
/* Always allow bridge resources above 4G. */
if (res->flags & IORESOURCE_BRIDGE)
return res->limit;
--
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Code-Review+1 by Felix Held, Code-Review+1 by Felix Singer, Code-Review+1 by Tim Wawrzynczak, Verified+1 by build bot (Jenkins)
Change subject: device/device.h: Drop acpi_inject_dsdt
......................................................................
device/device.h: Drop acpi_inject_dsdt
This is now unused in the tree and filling SSDT should always be used.
Change-Id: Id1e100cf650b3654240dbf19e1ee3069980fbe93
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/acpi/acpi.c
M src/include/device/device.h
2 files changed, 0 insertions(+), 4 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/02/70502/6
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Change subject: soc/intel/xeon_sp: Add IIO resources via SSDT
......................................................................
soc/intel/xeon_sp: Add IIO resources via SSDT
There is no need to inject this code in DSDT. Just generating a _CRS
Name in SSDT containing a resource template works well and reduces the
need to sync up on names being used to return _CRS names in DSDT.
Change-Id: I188090819023ca83f14c4610266d215ba34379b8
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/soc/intel/xeon_sp/acpi/iiostack.asl
M src/soc/intel/xeon_sp/cpx/soc_acpi.c
M src/soc/intel/xeon_sp/include/soc/acpi.h
M src/soc/intel/xeon_sp/skx/soc_acpi.c
M src/soc/intel/xeon_sp/spr/acpi/cxl_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/dino_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/iiostack.asl
M src/soc/intel/xeon_sp/spr/acpi/pci_resource.asl
M src/soc/intel/xeon_sp/spr/acpi/ubox_resource.asl
M src/soc/intel/xeon_sp/spr/soc_acpi.c
M src/soc/intel/xeon_sp/uncore.c
11 files changed, 44 insertions(+), 71 deletions(-)
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Change subject: soc/intel/xeon_sp: Redesign resource allocation
......................................................................
soc/intel/xeon_sp: Redesign resource allocation
The xeon_sp code worked around the coreboot allocator rather than using
it. Now the allocator is able to deal with the multiple IIOs so this is
not necessary anymore.
Instead do the following:
- Parse the FPS HOB information about IIO into coreboot PCI domains
- Use existing scan_bus and read_resource
- When a stack contains multiple host bridges as sometimes the case for
DINO stacks, add host bridges for each bus.
TEST: See that all resources are properly allocated on intel/archercity.
Change-Id: If55c215fe078892e422a21ec1ca234faf8965542
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
---
M src/device/pci_device.c
M src/include/device/device.h
M src/soc/intel/xeon_sp/acpi.c
M src/soc/intel/xeon_sp/chip_common.c
M src/soc/intel/xeon_sp/cpx/chip.c
M src/soc/intel/xeon_sp/cpx/soc_util.c
M src/soc/intel/xeon_sp/include/soc/chip_common.h
M src/soc/intel/xeon_sp/include/soc/util.h
M src/soc/intel/xeon_sp/memmap.c
M src/soc/intel/xeon_sp/skx/chip.c
M src/soc/intel/xeon_sp/skx/soc_util.c
M src/soc/intel/xeon_sp/spr/chip.c
M src/soc/intel/xeon_sp/spr/soc_util.c
M src/soc/intel/xeon_sp/util.c
14 files changed, 172 insertions(+), 534 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/20/67020/8
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Hello Angel Pons, Christian Walter, Eran Mitrani, Felix Held, Fred Reitberger, Hung-Te Lin, Jakub Czapiga, Jason Glenesk, Jeff Daly, Johnny Lin, Kapil Porwal, Lean Sheng Tan, Matt DeVillier, Nick Vaccaro, Nico Huber, Raul Rangel, Sean Rhodes, Subrata Banik, Tarun, Tim Chu, Vanessa Eusebio, Werner Zeh, Yidi Lin, Yu-Ping Wu,
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Change subject: device/device.h: Rename pci_domain_scan_bus
......................................................................
device/device.h: Rename pci_domain_scan_bus
On all targets the domain works as a host bridge. Xeon-sp code intends
to feature multiple host bridges below a domain, hence rename the
function to pci_host_bridge_scan_bus.
Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz>
Change-Id: I252343788001e277ec5a125cdd31cf95f2505185
---
M src/device/pci_device.c
M src/include/device/device.h
M src/mainboard/emulation/qemu-aarch64/mainboard.c
M src/mainboard/emulation/qemu-i440fx/northbridge.c
M src/northbridge/amd/pi/00730F01/northbridge.c
M src/northbridge/intel/e7505/northbridge.c
M src/northbridge/intel/gm45/northbridge.c
M src/northbridge/intel/haswell/northbridge.c
M src/northbridge/intel/i440bx/northbridge.c
M src/northbridge/intel/i945/northbridge.c
M src/northbridge/intel/ironlake/northbridge.c
M src/northbridge/intel/pineview/northbridge.c
M src/northbridge/intel/sandybridge/northbridge.c
M src/northbridge/intel/x4x/northbridge.c
M src/soc/amd/common/block/data_fabric/domain.c
M src/soc/amd/stoneyridge/chip.c
M src/soc/cavium/cn81xx/ecam0.c
M src/soc/intel/alderlake/chip.c
M src/soc/intel/apollolake/chip.c
M src/soc/intel/baytrail/chip.c
M src/soc/intel/braswell/chip.c
M src/soc/intel/broadwell/northbridge.c
M src/soc/intel/cannonlake/chip.c
M src/soc/intel/denverton_ns/chip.c
M src/soc/intel/elkhartlake/chip.c
M src/soc/intel/jasperlake/chip.c
M src/soc/intel/meteorlake/chip.c
M src/soc/intel/skylake/chip.c
M src/soc/intel/tigerlake/chip.c
M src/soc/mediatek/mt8195/soc.c
M src/soc/qualcomm/sc7280/soc.c
31 files changed, 32 insertions(+), 32 deletions(-)
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Change subject: mb/google/rex/var/screebo: add hook for WiFi SAR table
......................................................................
mb/google/rex/var/screebo: add hook for WiFi SAR table
As a preparation for WiFi SAR table addition, adding hook for it.
BUG=b:291155207
TEST=emerge-rex coreboot
Change-Id: Ia313cfddec278e6bf8498407b242c027a5891deb
Signed-off-by: YH Lin <yueherngl(a)google.com>
---
M src/mainboard/google/rex/Kconfig
M src/mainboard/google/rex/variants/screebo/overridetree.cb
M src/mainboard/google/rex/variants/screebo/variant.c
3 files changed, 11 insertions(+), 0 deletions(-)
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Change subject: mb/google/rex/var/screebo: remove SD_ABSENT
......................................................................
mb/google/rex/var/screebo: remove SD_ABSENT
Remove SD_ABSENT since it's not being used, and CBI FW_CONFIG
in current build does not reflect this config neither.
BUG=b:291155207
TEST=emerge-rex coreboot
Change-Id: Icfa472ff5570ac728038ec67a762289407760812
Signed-off-by: YH Lin <yueherngl(a)google.com>
---
M src/mainboard/google/rex/variants/screebo/overridetree.cb
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Felix Held has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76497?usp=email )
Change subject: mb/amd/onyx: Add FMD file and update romsize
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
> adding this part of the next patch to this patch will likely solve the build failure: […]
after thinking a bit more about that, that part of the makefile would be best added in the previous patch that adds the usage of this variable to have both parts added in one patch
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Gerrit-Change-Id: Idd6f711f5ca5c8a421c0c38edd404b1900bb29b4
Gerrit-Change-Number: 76497
Gerrit-PatchSet: 5
Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz>
Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de>
Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com>
Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org>
Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com>
Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com>
Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com>
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Gerrit-Comment-Date: Thu, 31 Aug 2023 16:40:03 +0000
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