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Change subject: soc/intel/common: Add metadata tag definition for crashlog
......................................................................
Patch Set 6: Code-Review+2
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Change subject: soc/intel/meteorlake: Validate CPU crashlog discovery table and records
......................................................................
Patch Set 18: Code-Review+2
(1 comment)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76333/comment/1795679a_81cc69d2 :
PS18, Line 17: TEST=Able to build and verified invalid records are skipped on google/rex.
> `Possible unwrapped commit description (prefer a maximum 72 chars per line)`
Please fix.
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Change subject: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
......................................................................
Patch Set 5:
(1 comment)
Patchset:
PS5:
Fixed my "restore_agesa.sh" again VS a coreboot master (at cost of 3 more git reverts) - and also added "--no-edit" to all the git revert lines so that I don't have to hold "Ctrl+X" for confirming all these commit messages...
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Change subject: drivers/intel/fsp2_0: Introduce early MRC cache store
......................................................................
Patch Set 4:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77556/comment/0415bd48_1ed782c2 :
PS3, Line 43: +--------------------+--------------------------+--------------------------+-------------------------+
> Not sure if the long tables are necessary as only a single item changes.
This CL is meant to change the order in while the MRC cache being handled and will get handled, hence, its better to capture the change in details.
The thing that is problematic is the gerrit review is unable to handle the long length ascii rows which shouldn't be a problem in git log
https://review.coreboot.org/c/coreboot/+/77556/comment/c7c626d5_28fd9c74 :
PS3, Line 47:
> Maybe mention that this effectively undoes commit 7b5a93153a17, and why,
> i.e. what changed since then (CSE sync, CBMEM caching).
done
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Hello Andrey Petrov, Felix Held, Fred Reitberger, Jason Glenesk, Kapil Porwal, Lean Sheng Tan, Martin L Roth, Matt DeVillier, Nico Huber, Raul Rangel, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: drivers/intel/fsp2_0: Introduce early MRC cache store
......................................................................
drivers/intel/fsp2_0: Introduce early MRC cache store
This patch refactors the existing MRC cache storing logic, which was
spread between the ROM and RAM stages, into a single early MRC cache
store stage.
It reverts all the logic introduced by commit 7b5a93153a17 (drivers/intel/fsp2_0: Update MRC cache in ramstage) because it is no longer required due to improved memory caching at the pre-RAM phase (with the ramtop implementation). Therefore, the original purpose of doing MRC cache early in ramstage is no longer beneficial, and it is better to do the same operation late in romstage (after RAM initialization).
In this updated logic, the romstage (post FSP-M) will attempt to save
the MRC cache. Depending on whether the MRC_STASH_TO_CBMEM config is
enabled, the MRC cache will either be written directly to NVRAM at the
romstage or stashed into CBMEM for a late NVRAM write at ramstage.
Below table captures the change in the boot state w/ and w/o this
patch for storing the MRC cache. Overall the goal is to ensure the
platform behavior is remain unchanged before and after this patch.
w/o this patch:
+---------------------+--------------------------+--------------------------+-------------------------+
| | Save MRC Cache | Finalize MRC Cache | Lock the Boot Medium |
+---------------------+--------------------------+--------------------------+-------------------------+
| MRC_WRITE_NV_LATE | BS_OS_RESUME_CHECK_ENTRY | BS_OS_RESUME_CHECK_ENTRY | BS_OS_RESUME_CHECK_EXIT |
+---------------------+--------------------------+--------------------------+-------------------------+
| MRC_STASH_TO_CBMEM | BS_DEV_ENUMERATE_EXIT | BS_DEV_ENUMERATE_EXIT | BS_DEV_RESOURCES_ENTRY |
+---------------------+--------------------------+--------------------------+-------------------------+
| Platform w/o above | BS_PRE_DEVICE_ENTRY | BS_DEV_ENUMERATE_EXIT | BS_DEV_RESOURCES_ENTRY |
| configs (FSP 2.0 | | | |
| platforms) | | | |
+---------------------+--------------------------+--------------------------+-------------------------+
w/ this patch:
+--------------------+--------------------------+--------------------------+-------------------------+
| | Save MRC Cache | Finalize MRC Cache | Lock the Boot Medium |
+--------------------+--------------------------+--------------------------+-------------------------+
| MRC_WRITE_NV_LATE | BS_OS_RESUME_CHECK_ENTRY | BS_OS_RESUME_CHECK_ENTRY | BS_OS_RESUME_CHECK_EXIT |
+--------------------+--------------------------+--------------------------+-------------------------+
| MRC_STASH_TO_CBMEM | BS_DEV_ENUMERATE_EXIT | BS_DEV_ENUMERATE_EXIT | BS_DEV_RESOURCES_ENTRY |
+--------------------+--------------------------+--------------------------+-------------------------+
| Platform w/o above | Post FSP-M (romstage) | BS_DEV_ENUMERATE_EXIT | BS_DEV_RESOURCES_ENTRY |
| configs (FSP 2.0 | | | |
| platforms) | | | |
+--------------------+--------------------------+--------------------------+-------------------------+
Allows all the FSP2.0 based platform to perform the MRC cache save
operation early from romstage.
BUG=b:296704537
TEST=Able to build and boot google/rex without any boot time impact.
Change-Id: Id1e91d25916594f59d1e467a142f5042c6138b51
Signed-off-by: Subrata Banik <subratabanik(a)google.com>
---
M src/drivers/intel/fsp2_0/memory_init.c
1 file changed, 18 insertions(+), 15 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/56/77556/4
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Change subject: util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
......................................................................
util/scripts/restore_agesa.sh - restores the opensource AMD AGESA boards
This script reverts the opensource AGESA AMD boards removal that happened
after 5e8e911b7caee021faff96c4e82a77a42544ea62 (0 point of history, or 0 PoH)
- by git-reverting:
1) the "bad commits" (marked as "CBF" = coreboot build failure)
- that either remove or break a code needed for our boards
2) the "unlucky commits" (marked as "GRF" = git revert failure)
- that are a roadblock for git-reverting the "bad commits"
Right now at f3ae1a120973da374ecbd2488b56b6a8fbbc82b5 (4266 PoH), it takes
38 CBF git reverts - just 1% of 4266 commits since the OSS AGESA removal! -
- making this removal look questionable and the idea of restoration viable.
SUCCESSFUL TESTS for the opensource AGESA boards which I own (Lenovo G505S -
- fam15 laptop, ASUS A88XM-E - fam15 desktop, ASUS AM1I-A - fam16 desktop) :
1) only build:
69ffebf5ccf123bc0b3fb28b485985af0597761d (3698 PoH) for AM1I-A,
most likely boot works too but I didn't have the time to test
2) build & boot:
69ffebf5ccf123bc0b3fb28b485985af0597761d (3698 PoH) for G505S and A88XM-E
11ba8ebbcc662ebd1dc8e14372a020eb32f26561 (3741 PoH) for G505S test only
Change-Id: Ib4658dcaf4ff6fbac36070529284f2c982ed73c3
Signed-off-by: Mike Banon <mikebdp2(a)gmail.com>
---
A util/scripts/restore_agesa.sh
1 file changed, 194 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/32/76832/5
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