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Change subject: soc/amd/common: Use CBFSTOOL_ADD_CMD_OPTIONS when adding psp image
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Patch Set 6: Code-Review+2
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Change subject: mb/amd/onyx: Add minimal code for onyx compilation
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Patch Set 1: Code-Review+2
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Change subject: soc/amd/genoa: Add minimal viable code for compilation
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Patch Set 7:
(2 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76495/comment/6e041fe7_5b80d2f7 :
PS7, Line 9: and mainboard (onyx)
Sorry - remove this?
File src/soc/amd/genoa/Makefile.inc:
https://review.coreboot.org/c/coreboot/+/76495/comment/51d203bf_0cf1ed83 :
PS7, Line 1: ## SPDX-License-Identifier: GPL-2.0-only
If you wanted to, you could add a blank line after this, but it's not required.
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Change subject: mb/google/rex/var/karis: Enable ELAN touchscreen
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Patch Set 1: Code-Review+2
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Change subject: drivers/intel/fsp2_0: Remove unused save_mrc_data implementation
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Patch Set 10: Code-Review+1
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Change subject: drivers/intel/fsp2_0: Introduce early MRC cache store
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Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77556/comment/e83bc6e1_2b9e2457 :
PS3, Line 43: +--------------------+--------------------------+--------------------------+-------------------------+
Not sure if the long tables are necessary as only a single item changes.
https://review.coreboot.org/c/coreboot/+/77556/comment/48fb50e5_c58a8682 :
PS3, Line 47:
Maybe mention that this effectively undoes commit 7b5a93153a17, and why,
i.e. what changed since then (CSE sync, CBMEM caching).
File src/drivers/mrc_cache/mrc_cache.c:
https://review.coreboot.org/c/coreboot/+/77556/comment/316716ff_c210ab1e :
PS1, Line 742: BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, finalize_mrc_cache, NULL);
> > > > > This changes the order for devices with MRC_STASH_TO_CBMEM but without […]
Closing as the nature of the patch changed.
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Change subject: soc/intel/meteorlake: Enable crashlog
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Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77583/comment/5c82945a_c9b2f069 :
PS2, Line 9: Enable crashlog for Meteor Lake SOC.
> this line is redundant
Done
https://review.coreboot.org/c/coreboot/+/77583/comment/7d4f6feb_2852e372 :
PS2, Line 10:
> please mention that SOC_INTEL_IOE_DIE_SUPPORT also enabled in this CL
Done
https://review.coreboot.org/c/coreboot/+/77583/comment/f848d6a9_7ecd94f9 :
PS2, Line 12: REX
> google/rex
Done
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