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Change subject: drivers/intel/fsp2_0: Introduce early MRC cache store
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77556/comment/e83bc6e1_2b9e2457 :
PS3, Line 43: +--------------------+--------------------------+--------------------------+-------------------------+
Not sure if the long tables are necessary as only a single item changes.
https://review.coreboot.org/c/coreboot/+/77556/comment/48fb50e5_c58a8682 :
PS3, Line 47:
Maybe mention that this effectively undoes commit 7b5a93153a17, and why,
i.e. what changed since then (CSE sync, CBMEM caching).
File src/drivers/mrc_cache/mrc_cache.c:
https://review.coreboot.org/c/coreboot/+/77556/comment/316716ff_c210ab1e :
PS1, Line 742: BOOT_STATE_INIT_ENTRY(BS_OS_RESUME_CHECK, BS_ON_ENTRY, finalize_mrc_cache, NULL);
> > > > > This changes the order for devices with MRC_STASH_TO_CBMEM but without […]
Closing as the nature of the patch changed.
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Change subject: soc/intel/meteorlake: Enable crashlog
......................................................................
Patch Set 3:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/77583/comment/5c82945a_c9b2f069 :
PS2, Line 9: Enable crashlog for Meteor Lake SOC.
> this line is redundant
Done
https://review.coreboot.org/c/coreboot/+/77583/comment/7d4f6feb_2852e372 :
PS2, Line 10:
> please mention that SOC_INTEL_IOE_DIE_SUPPORT also enabled in this CL
Done
https://review.coreboot.org/c/coreboot/+/77583/comment/f848d6a9_7ecd94f9 :
PS2, Line 12: REX
> google/rex
Done
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Change subject: soc/intel/common: Add metadata tag definition for crashlog
......................................................................
Patch Set 6:
(1 comment)
File src/soc/intel/common/block/include/intelblocks/crashlog.h:
https://review.coreboot.org/c/coreboot/+/76833/comment/ec2d52d6_07c84871 :
PS5, Line 32: * then region is for SOC PMC, if the TAG is 0x1 then the region is for IOE PMC. The TAG
> > `Possible repeated word: 'then'` […]
Done
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Change subject: soc/intel/meteorlake: Validate CPU crashlog discovery table and records
......................................................................
Patch Set 18:
(3 comments)
Commit Message:
https://review.coreboot.org/c/coreboot/+/76333/comment/ac76cbbd_4f63fa6b :
PS17, Line 17: REX
> nit: google/rex
Done
File src/soc/intel/meteorlake/crashlog.c:
https://review.coreboot.org/c/coreboot/+/76333/comment/8a3bfe7d_98bf9a01 :
PS17, Line 385: {
> u don't need brace around single statement
Done
https://review.coreboot.org/c/coreboot/+/76333/comment/8920419d_9d9ad635 :
PS17, Line 401: printk(BIOS_DEBUG, "invalid cpu crashlog record[0x%x] dw0: 0x%x\n", i, dw0);
> same as https://review.coreboot. […]
Done
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Hello Eran Mitrani, Jakub Czapiga, Kapil Porwal, Subrata Banik, Tarun, build bot (Jenkins),
I'd like you to reexamine a change. Please visit
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Change subject: soc/intel/meteorlake: Enable crashlog
......................................................................
soc/intel/meteorlake: Enable crashlog
Enable SOC_INTEL_CRASHLOG and SOC_INTEL_IOE_DIE_SUPPORT Kconfig
options.
BUG=b:262501347
TEST=Able to build google/rex. Able to trigger and decode crashlog.
Change-Id: I4beef7393090889fde8d67827035c3b57a3dbb34
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/meteorlake/Kconfig
1 file changed, 2 insertions(+), 0 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/83/77583/3
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Change subject: soc/intel/meteorlake: Implement cleanup and rearm functions
......................................................................
soc/intel/meteorlake: Implement cleanup and rearm functions
cpu_cl_cleanup() function checks if the SOC supports storage-off
feature. This feature allows to turn off PUNIT SSRAM to save power.
Enable the storage-off if it's supported. Enabling it also clears the
crashlog records from PUNIT SSRAM.
cpu_cl_rearm() function rearms the CPU crashlog.
BUG=b:262501347
TEST=Able to build google/rex. Verified both features get asserted.
Change-Id: Id9ba0f5db0b5d2bd57a7a21f178ef1e86ca63fae
Signed-off-by: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.com>
---
M src/soc/intel/meteorlake/crashlog.c
M src/soc/intel/meteorlake/include/soc/crashlog.h
2 files changed, 100 insertions(+), 10 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/39/77239/9
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Hello Subrata Banik, build bot (Jenkins),
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Change subject: soc/intel/common: Add more fields for CPU crashlog header
......................................................................
soc/intel/common: Add more fields for CPU crashlog header
Add more details in CPU crashlog header structure, such as
storage off status and support, re-arm status etc. These fields
are used to check of particular feature is supported or not and
if supported what is the status of the feature.
BUG=b:262501347
TEST=Able to build google/rex.
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---
M src/soc/intel/common/block/include/intelblocks/crashlog.h
1 file changed, 11 insertions(+), 5 deletions(-)
git pull ssh://review.coreboot.org:29418/coreboot refs/changes/62/77562/3
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