coreboot-gerrit August 2023

coreboot-gerrit@coreboot.org

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[S] Change in coreboot[master]: soc/intel/meteorlake: Use read64 instead of two read32
by Pratikkumar V Prajapati (Code Review) 31 Aug '23

31 Aug '23

Pratikkumar V Prajapati has abandoned this change. ( https://review.coreboot.org/c/coreboot/+/77240?usp=email ) Change subject: soc/intel/meteorlake: Use read64 instead of two read32 ...................................................................... Abandoned -- To view, visit https://review.coreboot.org/c/coreboot/+/77240?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ic33593dd678146bc415b43671d1d9bf45de407a9 Gerrit-Change-Number: 77240 Gerrit-PatchSet: 9 Gerrit-Owner: Pratikkumar V Prajapati <pratikkumar.v.prajapati(a)intel.com> Gerrit-Reviewer: Eran Mitrani <mitrani(a)google.com> Gerrit-Reviewer: Jakub Czapiga <jacz(a)semihalf.com> Gerrit-Reviewer: Kapil Porwal <kapilporwal(a)google.com> Gerrit-Reviewer: Subrata Banik <subratabanik(a)google.com> Gerrit-Reviewer: Tarun <tstuli(a)gmail.com> Gerrit-Reviewer: Tarun Tuli <taruntuli(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Elyes Haouas <ehaouas(a)noos.fr> Gerrit-CC: Eric Lai <eric_lai(a)quanta.corp-partner.google.com> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Kyösti Mälkki <kyosti.malkki(a)gmail.com> Gerrit-CC: Paul Menzel <paulepanter(a)mailbox.org> Gerrit-CC: Pratikkumar Prajapati <pratikkumar.v.prajapati(a)intel.corp-partner.google.com> Gerrit-MessageType: abandon

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[M] Change in coreboot[master]: soc/amd/genoa: Add minimal viable code for compilation
by Varshit Pandya (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Arthur Heymans, Felix Held, Martin L Roth. Varshit Pandya has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/76495?usp=email ) Change subject: soc/amd/genoa: Add minimal viable code for compilation ...................................................................... Patch Set 7: (2 comments) Patchset: PS6: > This patch could should probably be split into two - one for the soc code first, then the mainboard […] Done File src/mainboard/amd/onyx/board_info.txt: https://review.coreboot.org/c/coreboot/+/76495/comment/08df138a_bc1ef99c : PS6, Line 1: misc > Nit: shouldn't this be eval? Done -- To view, visit https://review.coreboot.org/c/coreboot/+/76495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 Gerrit-Change-Number: 76495 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Comment-Date: Thu, 31 Aug 2023 17:39:20 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: mb/amd/onyx: Add minimal code for onyx compilation
by Varshit Pandya (Code Review) 31 Aug '23

31 Aug '23

Varshit Pandya has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77601?usp=email ) Change subject: mb/amd/onyx: Add minimal code for onyx compilation ...................................................................... mb/amd/onyx: Add minimal code for onyx compilation Change-Id: I25807e116869d1bd7b8324525bc5ae1691e072e4 Signed-off-by: Varshit Pandya <pandyavarshit(a)gmail.com> --- A src/mainboard/amd/onyx/Kconfig A src/mainboard/amd/onyx/Kconfig.name A src/mainboard/amd/onyx/board_info.txt A src/mainboard/amd/onyx/devicetree.cb A src/mainboard/amd/onyx/dsdt.asl 5 files changed, 36 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/01/77601/1 diff --git a/src/mainboard/amd/onyx/Kconfig b/src/mainboard/amd/onyx/Kconfig new file mode 100644 index 0000000..ce1b980 --- /dev/null +++ b/src/mainboard/amd/onyx/Kconfig @@ -0,0 +1,14 @@ +if BOARD_AMD_ONYX + +config BOARD_SPECIFIC_OPTIONS + def_bool y + select SOC_AMD_GENOA + select MISSING_BOARD_RESET + +config MAINBOARD_DIR + default "amd/onyx" + +config MAINBOARD_PART_NUMBER + default "Onyx" + +endif diff --git a/src/mainboard/amd/onyx/Kconfig.name b/src/mainboard/amd/onyx/Kconfig.name new file mode 100644 index 0000000..0dc99a7 --- /dev/null +++ b/src/mainboard/amd/onyx/Kconfig.name @@ -0,0 +1,2 @@ +config BOARD_AMD_ONYX + bool "Onyx" diff --git a/src/mainboard/amd/onyx/board_info.txt b/src/mainboard/amd/onyx/board_info.txt new file mode 100644 index 0000000..b351b8e --- /dev/null +++ b/src/mainboard/amd/onyx/board_info.txt @@ -0,0 +1 @@ +Category: eval diff --git a/src/mainboard/amd/onyx/devicetree.cb b/src/mainboard/amd/onyx/devicetree.cb new file mode 100644 index 0000000..5f447b2 --- /dev/null +++ b/src/mainboard/amd/onyx/devicetree.cb @@ -0,0 +1,6 @@ +chip soc/amd/genoa + + device domain 0 on + end + +end diff --git a/src/mainboard/amd/onyx/dsdt.asl b/src/mainboard/amd/onyx/dsdt.asl new file mode 100644 index 0000000..ecfe7a5 --- /dev/null +++ b/src/mainboard/amd/onyx/dsdt.asl @@ -0,0 +1,13 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +/* DefinitionBlock Statement */ +#include <acpi/acpi.h> +DefinitionBlock ( + "dsdt.aml", + "DSDT", + ACPI_DSDT_REV_2, + OEM_ID, + ACPI_TABLE_CREATOR, + 0x00010001 /* OEM Revision */ +) +} /* End of ASL file */ -- To view, visit https://review.coreboot.org/c/coreboot/+/77601?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I25807e116869d1bd7b8324525bc5ae1691e072e4 Gerrit-Change-Number: 77601 Gerrit-PatchSet: 1 Gerrit-Owner: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-MessageType: newchange

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[XS] Change in coreboot[master]: soc/amd/common: Use CBFSTOOL_ADD_CMD_OPTIONS when adding psp image
by Varshit Pandya (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Arthur Heymans, Felix Held, Fred Reitberger, Jason Glenesk, Martin L Roth, Matt DeVillier, Raul Rangel, Varshit Pandya. Varshit Pandya has uploaded a new patch set (#6) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76496?usp=email ) The following approvals got outdated and were removed: Code-Review+2 by Martin L Roth, Verified+1 by build bot (Jenkins) The change is no longer submittable: Code-Review and Verified are unsatisfied now. Change subject: soc/amd/common: Use CBFSTOOL_ADD_CMD_OPTIONS when adding psp image ...................................................................... soc/amd/common: Use CBFSTOOL_ADD_CMD_OPTIONS when adding psp image Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I639fb1e911a7449d0db0d2bfcfbb6f4f225b0cef --- M src/soc/amd/common/Makefile.inc M src/soc/amd/genoa/Makefile.inc 2 files changed, 7 insertions(+), 1 deletion(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/96/76496/6 -- To view, visit https://review.coreboot.org/c/coreboot/+/76496?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I639fb1e911a7449d0db0d2bfcfbb6f4f225b0cef Gerrit-Change-Number: 76496 Gerrit-PatchSet: 6 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Reviewer: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Reviewer: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Reviewer: Raul Rangel <rrangel(a)chromium.org> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Bao Zheng <fishbaozi(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Jason Glenesk <jason.glenesk(a)gmail.com> Gerrit-Attention: Raul Rangel <rrangel(a)chromium.org> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Matt DeVillier <matt.devillier(a)amd.corp-partner.google.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Fred Reitberger <reitbergerfred(a)gmail.com> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[M] Change in coreboot[master]: soc/amd/genoa: Add minimal viable code for compilation
by Varshit Pandya (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Arthur Heymans, Felix Held, Varshit Pandya. Varshit Pandya has uploaded a new patch set (#7) to the change originally created by Arthur Heymans. ( https://review.coreboot.org/c/coreboot/+/76495?usp=email ) The following approvals got outdated and were removed: Verified+1 by build bot (Jenkins) Change subject: soc/amd/genoa: Add minimal viable code for compilation ...................................................................... soc/amd/genoa: Add minimal viable code for compilation This adds a dummy soc (genoa) and mainboard (onyx) based on EXAMPLE_MIN86 with amd linker script hooked up. Default to 64bit code as that will be a sensible default for this platform (high memory access required for RAS setup). Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 --- A src/soc/amd/genoa/Kconfig A src/soc/amd/genoa/Makefile.inc A src/soc/amd/genoa/chip.c A src/soc/amd/genoa/early_fch.c A src/soc/amd/genoa/include/soc/iomap.h A src/soc/amd/genoa/include/soc/southbridge.h A src/soc/amd/genoa/romstage.c A src/soc/amd/genoa/timer.c 8 files changed, 167 insertions(+), 0 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/95/76495/7 -- To view, visit https://review.coreboot.org/c/coreboot/+/76495?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: I69253466084d17c4359d7e824d69f12490b076e4 Gerrit-Change-Number: 76495 Gerrit-PatchSet: 7 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Martin L Roth <gaumless(a)gmail.com> Gerrit-CC: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Varshit Pandya <pandyavarshit(a)gmail.com> Gerrit-Attention: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Attention: Felix Held <felix-coreboot(a)felixheld.de> Gerrit-MessageType: newpatchset

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[XS] Change in coreboot[master]: Update amd_blobs submodule to upstream master
by Karthik Ramasubramanian (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Martin L Roth, Robert Zieba. Karthik Ramasubramanian has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77541?usp=email ) Change subject: Update amd_blobs submodule to upstream master ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: > Thanks for catching that Karthik. I've removed the origin/main branch from the amd_blobs repo. No Problem. Thanks for getting to the bottom of this and your thorough explanation. -- To view, visit https://review.coreboot.org/c/coreboot/+/77541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb8334a4ca89745dfbeedf6d3e72a1b9d74d708 Gerrit-Change-Number: 77541 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 17:36:13 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: Update amd_blobs submodule to upstream master
by Felix Singer (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Karthik Ramasubramanian, Martin L Roth, Robert Zieba. Felix Singer has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77541?usp=email ) Change subject: Update amd_blobs submodule to upstream master ...................................................................... Patch Set 4: Code-Review+2 (1 comment) Patchset: PS4: Looks good to me now -- To view, visit https://review.coreboot.org/c/coreboot/+/77541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb8334a4ca89745dfbeedf6d3e72a1b9d74d708 Gerrit-Change-Number: 77541 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Martin L Roth <gaumless(a)gmail.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 17:33:55 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: Yes Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: Update amd_blobs submodule to upstream master
by Martin L Roth (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Karthik Ramasubramanian, Robert Zieba. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77541?usp=email ) Change subject: Update amd_blobs submodule to upstream master ...................................................................... Patch Set 4: (1 comment) Patchset: PS4: Thanks for catching that Karthik. I've removed the origin/main branch from the amd_blobs repo. -- To view, visit https://review.coreboot.org/c/coreboot/+/77541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb8334a4ca89745dfbeedf6d3e72a1b9d74d708 Gerrit-Change-Number: 77541 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 17:33:15 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Gerrit-MessageType: comment

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[XS] Change in coreboot[master]: Update amd_blobs submodule to upstream master
by Martin L Roth (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Karthik Ramasubramanian, Robert Zieba. Martin L Roth has posted comments on this change. ( https://review.coreboot.org/c/coreboot/+/77541?usp=email ) Change subject: Update amd_blobs submodule to upstream master ...................................................................... Patch Set 4: (1 comment) This change is ready for review. File 3rdparty/amd_blobs: https://review.coreboot.org/c/coreboot/+/77541/comment/b77192e5_035b377e : PS3, Line 1: 1cd6ea5cc5c22d3f4e439652ede85d21488232e4 > All of these issues are due to master/main problems. […] Done -- To view, visit https://review.coreboot.org/c/coreboot/+/77541?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Iebb8334a4ca89745dfbeedf6d3e72a1b9d74d708 Gerrit-Change-Number: 77541 Gerrit-PatchSet: 4 Gerrit-Owner: Martin L Roth <gaumless(a)gmail.com> Gerrit-Reviewer: Robert Zieba <robertzieba(a)google.com> Gerrit-Reviewer: build bot (Jenkins) <no-reply(a)coreboot.org> Gerrit-CC: Felix Singer <service+coreboot-gerrit(a)felixsinger.de> Gerrit-CC: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Attention: Robert Zieba <robertzieba(a)google.com> Gerrit-Attention: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-Comment-Date: Thu, 31 Aug 2023 17:29:31 +0000 Gerrit-HasComments: Yes Gerrit-Has-Labels: No Comment-In-Reply-To: Martin L Roth <gaumless(a)gmail.com> Comment-In-Reply-To: Karthik Ramasubramanian <kramasub(a)google.com> Gerrit-MessageType: comment

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[S] Change in coreboot[master]: soc/intel/xeon_sp: Scan and allocate resources on all stacks
by Arthur Heymans (Code Review) 31 Aug '23

31 Aug '23

Attention is currently required from: Christian Walter, Johnny Lin, Tim Chu. Arthur Heymans has uploaded this change for review. ( https://review.coreboot.org/c/coreboot/+/77600?usp=email ) Change subject: soc/intel/xeon_sp: Scan and allocate resources on all stacks ...................................................................... soc/intel/xeon_sp: Scan and allocate resources on all stacks The code can now deal with stacks that have no resources so just hook them all up. Signed-off-by: Arthur Heymans <arthur(a)aheymans.xyz> Change-Id: Ie3e19bbd4683237ecfc427d32aa29f55964d80a5 --- M src/soc/intel/xeon_sp/acpi.c M src/soc/intel/xeon_sp/chip_common.c M src/soc/intel/xeon_sp/cpx/soc_util.c M src/soc/intel/xeon_sp/include/soc/util.h M src/soc/intel/xeon_sp/memmap.c M src/soc/intel/xeon_sp/skx/soc_util.c M src/soc/intel/xeon_sp/spr/soc_util.c M src/soc/intel/xeon_sp/util.c 8 files changed, 8 insertions(+), 24 deletions(-) git pull ssh://review.coreboot.org:29418/coreboot refs/changes/00/77600/1 diff --git a/src/soc/intel/xeon_sp/acpi.c b/src/soc/intel/xeon_sp/acpi.c index 61d5186..80c95de 100644 --- a/src/soc/intel/xeon_sp/acpi.c +++ b/src/soc/intel/xeon_sp/acpi.c @@ -104,9 +104,9 @@ for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - if (!stack_needs_resource_alloc(ri)) - continue; uint32_t ioapic_base = ri->IoApicBase; + if (ioapic_base == 0) + continue; assert(index < ARRAY_SIZE(xeonsp_ioapic_bases)); xeonsp_ioapic_bases[index++] = ioapic_base; if (!CONFIG(XEON_SP_HAVE_IIO_IOAPIC)) diff --git a/src/soc/intel/xeon_sp/chip_common.c b/src/soc/intel/xeon_sp/chip_common.c index 8e4533e..38562a7 100644 --- a/src/soc/intel/xeon_sp/chip_common.c +++ b/src/soc/intel/xeon_sp/chip_common.c @@ -122,7 +122,7 @@ continue; const STACK_RES *ri = &hob->PlatformData.IIO_resource[s].StackRes[x]; - if (!stack_needs_resource_alloc(ri)) + if (ri->BusBase < ri->BusLimit) continue; struct device_path path; path.type = DEVICE_PATH_DOMAIN; diff --git a/src/soc/intel/xeon_sp/cpx/soc_util.c b/src/soc/intel/xeon_sp/cpx/soc_util.c index fb76014..64efb61 100644 --- a/src/soc/intel/xeon_sp/cpx/soc_util.c +++ b/src/soc/intel/xeon_sp/cpx/soc_util.c @@ -25,14 +25,9 @@ return *memmap_addr; } -bool stack_needs_resource_alloc(const STACK_RES *res) -{ - return res->Personality == TYPE_UBOX_IIO; -} - bool is_iio_stack_res(const STACK_RES *res) { - return stack_needs_resource_alloc(res); + return res->Personality == TYPE_UBOX_IIO; } uint8_t get_stack_busno(const uint8_t stack) diff --git a/src/soc/intel/xeon_sp/include/soc/util.h b/src/soc/intel/xeon_sp/include/soc/util.h index 8482efd..8e80c64 100644 --- a/src/soc/intel/xeon_sp/include/soc/util.h +++ b/src/soc/intel/xeon_sp/include/soc/util.h @@ -23,7 +23,6 @@ }; void get_iiostack_info(struct iiostack_resource *info); -bool stack_needs_resource_alloc(const STACK_RES *res); bool is_iio_stack_res(const STACK_RES *res); void bios_done_msr(void *unused); diff --git a/src/soc/intel/xeon_sp/memmap.c b/src/soc/intel/xeon_sp/memmap.c index e73143f..a9236a9 100644 --- a/src/soc/intel/xeon_sp/memmap.c +++ b/src/soc/intel/xeon_sp/memmap.c @@ -74,7 +74,7 @@ for (int stack = 0; stack < MAX_IIO_STACK; ++stack) { const STACK_RES *ri = &hob->PlatformData.IIO_resource[socket].StackRes[stack]; - if (!stack_needs_resource_alloc(ri)) + if (ri->VtdBarAddress == 0) continue; uint8_t bus = ri->BusBase; dev = VTD_DEV(bus); diff --git a/src/soc/intel/xeon_sp/skx/soc_util.c b/src/soc/intel/xeon_sp/skx/soc_util.c index d7e3efc1..93f28d0 100644 --- a/src/soc/intel/xeon_sp/skx/soc_util.c +++ b/src/soc/intel/xeon_sp/skx/soc_util.c @@ -54,15 +54,9 @@ return memmap_addr; } -bool stack_needs_resource_alloc(const STACK_RES *res) -{ - // TODO: do we have situation with only bux 0 and one stack? - return res->BusBase < res->BusLimit; -} - bool is_iio_stack_res(const STACK_RES *res) { - return stack_needs_resource_alloc(res); + return res->BusBase < res->BusLimit; } uint8_t get_stack_busno(const uint8_t stack) diff --git a/src/soc/intel/xeon_sp/spr/soc_util.c b/src/soc/intel/xeon_sp/spr/soc_util.c index e885bba..c87a8b0 100644 --- a/src/soc/intel/xeon_sp/spr/soc_util.c +++ b/src/soc/intel/xeon_sp/spr/soc_util.c @@ -68,11 +68,6 @@ return hob->Element; } -bool stack_needs_resource_alloc(const STACK_RES *res) -{ - return res->Personality == TYPE_UBOX_IIO || res->Personality == TYPE_DINO; -} - bool is_iio_stack_res(const STACK_RES *res) { return res->Personality == TYPE_UBOX_IIO; diff --git a/src/soc/intel/xeon_sp/util.c b/src/soc/intel/xeon_sp/util.c index c9f4c55..3780afb 100644 --- a/src/soc/intel/xeon_sp/util.c +++ b/src/soc/intel/xeon_sp/util.c @@ -1,5 +1,6 @@ /* SPDX-License-Identifier: GPL-2.0-only */ +#include "include/soc/util.h" #include <assert.h> #include <commonlib/sort.h> #include <console/console.h> @@ -114,7 +115,7 @@ for (int x = 0; x < MAX_IIO_STACK; ++x) { const STACK_RES *ri; ri = &hob->PlatformData.IIO_resource[socket].StackRes[x]; - if (!stack_needs_resource_alloc(ri)) + if (!is_iio_stack_res(ri)) continue; assert(info->no_of_stacks < (CONFIG_MAX_SOCKET * MAX_IIO_STACK)); memcpy(&info->res[info->no_of_stacks++], ri, sizeof(STACK_RES)); -- To view, visit https://review.coreboot.org/c/coreboot/+/77600?usp=email To unsubscribe, or for help writing mail filters, visit https://review.coreboot.org/settings Gerrit-Project: coreboot Gerrit-Branch: master Gerrit-Change-Id: Ie3e19bbd4683237ecfc427d32aa29f55964d80a5 Gerrit-Change-Number: 77600 Gerrit-PatchSet: 1 Gerrit-Owner: Arthur Heymans <arthur(a)aheymans.xyz> Gerrit-Reviewer: Christian Walter <christian.walter(a)9elements.com> Gerrit-Reviewer: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Reviewer: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-Attention: Johnny Lin <Johnny_Lin(a)wiwynn.com> Gerrit-Attention: Christian Walter <christian.walter(a)9elements.com> Gerrit-Attention: Tim Chu <Tim.Chu(a)quantatw.com> Gerrit-MessageType: newchange

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coreboot-gerrit August 2023